KR20000004712A - Semiconductor memory device with address pad being reduced - Google Patents

Abstract

PURPOSE: The device is to eliminate difficulties in designing and manufacturing a probe card caused by that the number of needles on the probe card is increased in proportion to the number of test devices. CONSTITUTION: The device comprises an address buffer for temporally storing an address signal, a shifting resistor(30) for selecting a low address and column address of the device, and a switching element(20) for selecting an address pad input and an output of the shifting resistor according to condition of a voltage across a terminal for selecting a specific address.

Description

Semiconductor memory device for address pad reduction

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, as the number of simultaneous measurement devices increases during wafer testing, the needle on the probe card increases, so that the semiconductor memory for address pad reduction to reduce the difficulties associated with the design and manufacture of the probe card. Relates to a device.

In general, with the development of electronic technology, the semiconductor field is rapidly developing to meet the trend of high integration, high efficiency, and high performance. Among these semiconductor devices, wafer testing of memory devices transfers electrical signals between the test system and the wafer. Although the probe card is essential, the number of needles on the probe card increases as the number of memory devices and the memory size to be measured simultaneously increase.

In detail, the increase in the number of needles on the probe card described above, for example, in the case of DRAM or SRAM, the address pad occupies the largest portion of the pads required for device testing. For 16-mega SDRAM, for example, 4 × 4 In this case, if there are 10 address pins, 4 clock pins, 4 DQ pins, and the address pins are major in the number of needles required on the probe card during wafer test, and the 8 simultaneous measurement devices are address pads 80 needles must be planted in the probe card.

Therefore, as described above, it is difficult to design a needle on a probe card as the number of simultaneous measurement devices increases or memory size increases, and at the same time, a decrease in output per unit time due to a decrease in measurable elements is presented as a problem. It became.

An object of the present invention to solve the above problems is to increase the number of simultaneous measurement devices during wafer testing, the needle (NEEDLE) on the probe card increases to reduce the address pad to reduce the difficulties associated with the design and manufacture of the probe card It is to provide a semiconductor memory device.

1 is a schematic circuit diagram of a semiconductor memory device for address pad reduction according to the present invention;

<Description of the symbols for the main parts of the drawings>

10: memory array 11: row decoder

12: sense amplifier 13: column decoder

30: shifting register section 20: switching section

According to an aspect of the present invention, a memory array in which memory cells of a semiconductor memory are arranged in a matrix form, a row decoder for activating a word line of the memory array, and a row decoder A semiconductor memory device comprising a sense amplifier for amplifying data contained in a bit line accessed by an active word line, and a column decoder for activating a specific bit line among bit lines through the sense amplifier. The address pad input and the address buffer according to a state of an address buffer for receiving and temporarily storing an address, a shift register unit for selecting row addresses and column addresses of the semiconductor device, and a voltage applied to a terminal for selecting a specific address from the outside; Shifting register section output It is to include a selection switch to.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic circuit diagram of a semiconductor memory device for reducing an address pad according to an embodiment of the present invention, in which memory cells of a semiconductor memory are arranged in a matrix form, and words of the memory array 10 are shown. ROW decoder 11 for activating the line and amplifying data contained in the accessed bit line among the bit lines hung on the active word line by driving the ROW decoder 11 A semiconductor device comprising a sense amplifier 12 for performing the operation, a column decoder 13 for activating a specific bit line among the bit lines through the sense amplifier 12, and a row address of the semiconductor device. And a shifting register section 30 for selecting a column address and an address signal received from a semiconductor device inspection apparatus and temporarily stored therein. The address pad signal output from the address buffer 40 and the output of the shifting register unit 30 are selected according to the state of the voltage applied to the response buffer 40 and the terminal SA for selecting a specific address from the outside. It consists of a switching unit 20.

The preferred operation of the semiconductor memory device having the address switching configuration for address pad reduction according to the present invention configured as described above is as follows.

First, the switching operation for reducing the address pad according to the present invention can be summarized as shown in Table 1 below.

SA A0 A1 A2 A3 A4-A9 Operation mode 0 X X X X X Normal address adjustment One 0 X 0 X X Keep old One One 0 0 X X Row address increment One 0 X One C X Column address increment One One X One X X Row / Column Address Clear

As shown in Table 1, when the signal applied to the terminal SA for selecting a specific address is in a low state, the off state of the first NMOS transistor N1 of the switching unit 20 is maintained. 20, since the first PMOS P1 and the second PMOS P2 inside are kept in the on state, while the second NMOS N2 and the third NMOS N3 are in the off state, they are output from the address buffer. An address is provided to the column decoder 13 and the row decoder 11 to enter the normal normal operation mode.

On the other hand, when the signal applied to the terminal SA for selecting a specific address is in a high state, since the first NMOS N1 of the switching unit 20 remains on, the first inside of the switching unit 20 is maintained. Since the PMOS P1 and the second PMOS P2 remain in the off state, while the second NMOS N2 and the third NMOS N3 remain in the on state, the signal output from the shifting register unit 30 is reduced. It is provided to the column decoder 13 and the row decoder 11 to enter the operation mode according to the present invention.

In this case, the shifting register unit 30 includes only addresses corresponding to each of the column decoder 13 and the row decoder 11, so that the column decoder 13 and the row decoder 11 may be selectively selected. You can check the behavior.

Therefore, 10 terminals are output from the memory tester, but there is no need to connect 10 terminals when connecting the needle after seating the device on the probe card. Only two needles for connecting to the unit 30 and two needles for connecting the column output terminal and the row output terminal of the address buffer 4 need be provided.

Providing the semiconductor memory device for address pad reduction according to the present invention operating as described above, by reducing the number of needle (NEEDLE) on the probe card has the effect of reducing the trouble caused by the design and manufacture of the probe card.

Claims (1)

Access of a memory array in which memory cells of a semiconductor memory are arranged in a matrix form, a row decoder for activating word lines of the memory array, and a bit line hung on an active word line in response to driving of the row decoder A semiconductor memory device comprising a sense amplifier for amplifying data carried on a given bit line, and a column decoder for activating a specific bit line among bit lines through the sense amplifier. An address buffer which receives the address signal and temporarily stores the address signal; A shifting register unit for selecting a row address and a column address of the semiconductor device; Switching unit for selecting the address pad input and the output of the shifting register according to the state of the voltage applied to the terminal for selecting a specific address from the outside The semiconductor memory device for reducing the address pad, comprising a.