KR20000001490A - power-CONSUMPTION PREVENTION APPARATUS AND METHOD IN ELECTRONIC DEVICE - Google Patents

Abstract

PURPOSE: A power-consumption prevention apparatus and method in electronic device have various transitions toward a sleep mode and a stop mode, and have various returning steps from a stop mode to active state. CONSTITUTION: In a power-consumption prevention apparatus having a register and a sleep mode controller, a first logic operator performs a logic operation about a reset bar (RESETB) signal and a stop mode release request input (STOPRELB), and outputs a result signal. A second logic operator performs a logic operation about output signals of the register and the sleep mode controller as well as a peripheral device driving clock (PERI CLK), and outputs a result signal (STOPB). A third logic operator performs a logic operation about an oscillator signal (CLK) according to a signal(STOPB) of the second logic operator, and outputs a result signal. A fourth logic operator performs a logic operation about a signal of the third logic operator according to a signal (CLOCKFB) of a sleep mode controller, and outputs a result signal. A fifth logic operator performs a logic operation about a signal of the third logic operator according to a setting signal, and output a result signal.

Description

Apparatus and method for preventing power consumption in electronic devices

The present invention relates to an electronic device, and more particularly, to an apparatus and method for preventing power consumption in an electronic device.

Hereinafter, a method for preventing power consumption in an electronic device according to the prior art will be described with reference to the accompanying drawings.

1 is a view showing a transition state of a method for preventing power consumption in an electronic device according to the prior art.

First, when the power is turned on, the CPU enters an active state through an exception process in the exception state and performs a normal operation to execute a series of programs.

Here, the active state is an exception source for transitioning back to the active state when an error occurs when the transition from the exception state to the active state occurs. Output

After that, if there is no instruction for a certain time, the CPU outputs an instruction to transition to sleep mode to reduce power consumption, and then transitions to sleep mode to stop operation and registers. Or cache the contents of the previous state.

In this state, when an interrupt or reset is generated from the outside, the state transitions to the exception state in the sleep mode and then the exception process is performed to transition to the active state.

And if there is no instruction (Instrution) for a certain period of time, the CPU goes to the stop mode (Stop mode) to reduce power consumption and stops the operation of peripheral devices.

In addition, functions such as phase locked loops (PLL) and oscillators will stop.

In this state, when a reset or stop mode release request input occurs from the outside, the CPU transitions to the exception state in the stop mode and then the exception processing process (Exception). state) to transition to the active state.

However, the method for preventing power consumption in the electronic device according to the related art is returned to the active state only through an exception state in the stop mode.

Therefore, the present invention has been made to solve the above problems, the process of the transition to the sleep mode (Sleep) and stop mode (Stop mode) and return to the active state (Stop mode) to the active state (Stop mode) It is an object of the present invention to provide a device for preventing power consumption in an electronic device to be diversified.

Another object of the present invention is to provide a method for preventing power consumption in an electronic device corresponding to the above apparatus.

1 is a view showing a transition state of a method for preventing power consumption in an electronic device according to the prior art;

2 is a diagram illustrating a configuration of an apparatus for preventing power consumption in an electronic device according to the present invention.

3 is a view showing the transition state of FIG.

FIG. 4 is a diagram illustrating waveforms of respective parts in the stop mode of FIG. 2. FIG.

FIG. 5 is a diagram illustrating waveforms of each unit when the stop mode of FIG. 2 is released;

FIG. 6 is a diagram illustrating each sub waveform in an exception state when an interrupt occurs in FIG. 2; FIG.

Features of the power consumption preventing device in the electronic device according to the present invention for achieving the above object, in the power consumption prevention device in the electronic device consisting of a register and a sleep mode control unit, the reset bar (RESETB) signal and the stop A first logical operation means for performing a logic operation on the mode release request input STOPRELB and outputting a result signal, and a result of the logic operation on the signal of the register and the sleep mode controller and the peripheral device driving clock PERI CLK. A second logic calculating means for outputting the?), A third logic calculating means for performing a logic operation on the signal CLKI of the oscillator according to the signal STOPB of the second logic calculating means, and outputting a resultant signal, and the sleep mode. The fourth logic operation means for performing a logic operation on the signal of the third logic operation means according to the signal CLOCKFB of the controller and outputting the resultant signal, and according to the set signal And fifth logic calculating means for logically calculating the signal of the third logical calculating means and outputting the resultant signal.

A characteristic of the method for preventing power consumption in an electronic device according to the present invention for achieving the above object is a transition from an exception state to an active state or an exception state in a stop mode. In a method for preventing power consumption in an electronic device in which an error state is returned, the register state is set in the exception state to transition to a sleep mode, and an interrupt or reset occurs when an interrupt or reset occurs. Returning to the exception state, and automatically transitions to the stop mode after a predetermined time has elapsed in the sleep mode, and then sleeps when the stop mode release pin is operated. mode).

Hereinafter, a preferred embodiment of an apparatus and method for preventing power consumption in an electronic device according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a configuration of an apparatus for preventing power consumption in an electronic device according to an embodiment of the present invention, wherein a reset bar signal and a stop mode release request input STOPRELB are logically operated to output a result signal. A signal for controlling a sleep mode according to a signal of the register 120 including a logic operation unit 110, a sleep mode region and a stop mode region, and a signal of the register 120. And a logic operation of the sleep mode controller 130 for outputting (CLOCKFB), the signals of the register 120 and the sleep mode controller 130, and the peripheral device driving clock PERI CLK, and outputting the resultant signal STOPB. A third logic operator 150 for performing a logic operation on the signal CLKI of the oscillator according to the second logic operator 140 and the signal STOPB of the second logic operator 140, and outputting a resultant signal; To the signal CLOCKFB of the sleep mode controller 130. Accordingly, the fourth logical operation unit 160 for performing a logical operation on the signal of the third logical operation unit 160 and outputting the resultant signal, and performing a logical operation on the signal of the third logical operation unit 150 according to the set signal. As a result, a fifth logic operator 170 for outputting a signal, a core clock generator 180 for generating a core clock CORECLK according to the signal of the fourth logic operator 160, and the fifth logic operator ( The peripheral device driving clock generator 190 generates a driving clock PERI CLK of the peripheral device according to the signal of 170.

The first logic operation unit 110 includes an AND gate 110a that logically multiplies the reset bar signal and the stop mode release request input STOPRELB and outputs the resultant signal.

The second logic operation unit 140 performs a negative OR on the signal CLOCKFB of the sleep mode control unit 130 and the signal of the stop mode region of the register 120 and outputs a result signal of the NOR gate 140a. A first inverter 140b for inverting and outputting a signal of the NOR gate 140a, a second inverter 140c for inverting and outputting a clock of a peripheral device, the peripheral device driving clock PERI CLK, and a first inverter 140b. The third inverter 140d for inverting and outputting the signal of the first inverter 140b according to the second inverter 140c, and the signal of the first logic operation unit 110 and the signal of the second inverter 140c are outputted. NAND gate 140e that performs a negative AND and outputs the resultant signal STOPB, and a fourth inverter 140f that feeds back and inverts the signal of the first NAND gate 140e and outputs the resultant signal. And turn-on according to the peripheral device driving clock PERI CLK and the second inverter 140c. and a transfer gate 140g which is urn-on and outputs to the input terminal of the first NAND gate 150e.

The third logic operator 150 includes a second NAND gate 150a that negatively multiplies the clock of the oscillator and the signal STOPB of the second logic operator 140 and outputs a resultant signal.

The fourth logic operator 160 negatively multiplies the signal of the third logic operator 150 according to the signal CLOCKFB of the sleep mode controller 130 and outputs a resultant signal. It consists of.

The fifth logic operator 170 includes a fourth NAND gate 170a that negatively multiplies the signal of the third logic operator 150 according to a set signal and outputs a resultant signal.

FIG. 3 is a diagram illustrating a transition state of FIG. 2, FIG. 4 is a diagram illustrating waveforms of each unit in the stop mode of FIG. 2, FIG. 5 is a diagram of waveforms of each unit when the stop mode of FIG. 2 is released. FIG. 2 is a diagram illustrating each sub waveform in an exceptional state when an interrupt occurs in FIG. 2.

An apparatus and method for preventing power consumption in an electronic device according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, in order to transition from an exception state to a sleep mode, when the sleep mode region of the register 120 is set to "1" and the stop mode region is set to "0", the sleep mode controller 130 Outputs "0" with the CLOCKFB signal.

The first logical operation unit 110 performs a logical operation on the RESETB signal "1" and the STOPRELB signal "0" and outputs "0" as a result signal.

That is, the first AND gate 110a in the first logic calculator 110 multiplies the RESETB signal "1" and the STOPRELB signal "0" and outputs "0" as a result signal.

Then, the second logic operation unit 140 performs a logic operation on the signal of the register 110 and the sleep mode control unit 120 according to the signal of the first logic operation unit 110 and the peripheral device driving clock PERICLK and converts it into a STOPB signal. Outputs "1".

That is, the NOR gate 140a in the second logic operation unit 140 outputs "1" by negating the signal output from the "0" of the sleep mode controller 130 and the stop mode region of the register 120. The first inverter 140b inverts this and outputs "0".

In addition, the second inverter 140c inverts and outputs the peripheral device driving clock PERICLK.

Then, the third inverter 140d is turned on / off according to the signal inverted by the peripheral device driving clock PERICLK and the second inverter 140c to invert the signal of the first inverter 140a to output the output / Block it.

Subsequently, the first NAND gate 140e performs a negative logical multiplication regardless of the signal of the third inverter 140d according to "0" output from the first logic operation unit 110 and outputs "1" as a STOPB signal.

The fourth inverter 140f feeds back and inverts the signal of the first NAND gate 140e and outputs the same, and the transmission gate 140g is different from the third inverter 140d according to the peripheral device driving clock. When the third inverter 140d is cut off by performing the reverse operation, the signal inverted by the fourth inverter 140f is output to the first NAND gate 140e.

Accordingly, the third logic operation unit 150 performs a logic operation on the clock CLKI of the oscillator according to the STOPB signal " 1 " output from the second logic operation unit 140, thereby counter-signaling the signal CLK of the oscillator CLK. CLKIX).

That is, the second NAND gate 150a in the third logic operation unit 150 negatively multiplies the clock CLKI of the oscillator according to the STOPB signal "1" output from the second logic operation unit 140 to clock the oscillator. Outputs the opposite signal (CLKIX) of (CLKI).

Then, the fourth logic calculator 160 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the signal CLOCKFB of the sleep mode controller 130 and outputs the resultant signal. .

That is, the third NAND gate 160a in the fourth logic calculator 160 negates the signal CLKIX of the third logic calculator 150 according to "0", which is the signal CLOCKFB of the sleep mode controller 130. Logically multiplies and outputs "1".

Then, the core clock generator 180 fixes the core clock CORECLK according to "1" fixed by the first logic calculator 160.

In addition, the fifth logic calculator 170 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the set signal "1" and outputs the resultant signal.

That is, the fifth logic operation unit 170 negatively multiplies the signal CLKIX of the third logic operation unit 150 according to the set signal “1” to normally output the clock CLKI of the oscillator. .

Then, the peripheral device driving clock generator 190 normally outputs the peripheral device driving clock PERICLK according to the signal of the fifth logical operation unit 170.

In this state, when a reset or interrupt occurs, the RESETB signal becomes “0”, so the first logic operation unit 110 outputs “0” as a logic operation result signal.

Then, the second logic operation unit 140 outputs the signal of the register 120 according to the peripheral device driving clock PERICLK and the sleep mode control unit 130 according to "0" output from the first logic operation unit 110. Irrespective of signal CLOCKFB, "1" is output as STOPB signal.

Accordingly, the third logic operation unit 150 performs a logic operation on the clock CLKI of the oscillator according to the STOPB signal " 1 " output from the second logic operation unit 140, thereby counter-signaling the signal CLK of the oscillator CLK. CLKIX).

That is, the second NAND gate 150a in the third logic operation unit 150 negatively multiplies the clock CLKI of the oscillator according to the STOPB signal "1" output from the second logic operation unit 140 to clock the oscillator. Outputs the opposite signal (CLKIX) of (CLKI).

Subsequently, the fourth logic operation unit 160 performs a logic operation on the signal CLKIX of the third logic operation unit 150 according to the signal CLOCKFB of the sleep mode control unit 130 and outputs the resultant signal. .

That is, the third NAND gate 160a in the fourth logic calculator 160 negates the signal CLKIX of the third logic calculator 150 according to "0", which is the signal CLOCKFB of the sleep mode controller 130. Logically multiplies and outputs "1".

Then, the core clock generator 180 fixes the core clock CORECLK according to "1" fixed by the first logic calculator 160.

In addition, the fifth logic calculator 170 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the set signal "1" and outputs the resultant signal.

That is, the fifth logic operation unit 170 negatively multiplies the signal CLKIX of the third logic operation unit 150 according to the set signal “1” to normally output the clock CLKI of the oscillator. .

Then, the peripheral device driving clock generator 190 normally outputs the peripheral device driving clock PERICLK according to the signal of the fifth logical operation unit 170.

On the other hand, in the sleep mode described above, if a reset or interrupt does not occur and a predetermined time according to the CPU clock (CLOCK) as shown in FIG. 4A has elapsed, the stop mode is automatically stopped. The first logic operation unit 110 performs a logical operation on the STOPRELB signal and the RESETB signal as shown in FIG. 4B and outputs the resultant signal.

The register 120 sets the stop mode area to "0" as shown in FIG. 4F, and accordingly, the sleep mode controller 130 outputs "0" as a CLOCKFB signal as shown in FIG. 4C.

Then, the second logic operation unit 140 logically operates the signal of the stop mode region of the register 120 and the signal of the sleep mode controller 130 according to the peripheral device driving clock PERICLK as shown in FIG. 4D. As a result signal STOPB, " 0 " is output as shown in Fig. 4E.

In other words, the NOR gate 140a in the second logic operation unit 140 negates and combines "0" which is the signal STOPB of the sleep mode controller 130 and "0" of the stop mode region of the register 120 by "N". Output 1 ".

Then, the first inverter 140b inverts "1" of the NOR gate 140a and outputs "0".

Subsequently, the third inverter 140d inverts " 0 " outputted from the first inverter 104b according to the signal inverted by the peripheral device driving clock PERICLK and the second inverter 140c and then " 1 " Output or block

The first NAND gate 140e performs a negative AND on the " 1 " of the first logic calculator 1 and the " 1 " of the third inverter 140e, and outputs "0" as a STOPB signal.

Accordingly, the third logic operator 150 logically operates the clock CLKI of the oscillator according to the STOPB signal “0” of the second logic operator 140, and fixes the CLKIX signal to “1” and outputs the logic signal.

Then, the fourth logic calculator 160 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the signal CLOCKFB of the sleep mode controller 130 and outputs the resultant signal. .

That is, the third NAND gate 160a in the fourth logic calculator 160 negates the signal CLKIX of the third logic calculator 150 according to "0", which is the signal CLOCKFB of the sleep mode controller 130. Logically multiply and fix it to "1".

Then, the core clock generator 180 fixes the core clock CORECLK according to "1" fixed by the first logic calculator 160.

In addition, the fifth logic calculator 170 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the set signal "1" and outputs the resultant signal.

That is, the fifth logic operator 170 negatively multiplies the signal CLKIX of the third logic operator 150 according to the set signal “1” and fixes the signal CLKIX to “0” and outputs the same.

Then, the peripheral device driving clock generator 190 blocks the peripheral device driving clock PERICLK according to the signal of the fifth logic operation unit 170.

Meanwhile, as shown in FIG. 5A, when the stop-release pin is operated in the stop mode in which the CPU clock is “0”, the STOPRELB signal as shown in FIG. 5B is “0”. Since the output of the first logical operation unit 110 is "0".

Then, the sleep mode controller 130 outputs "0" as the output signal STOPB as shown in FIG. 5C and an interrupt signal as shown in FIG. 5G is applied.

Here, the stop mode area of the register 120 outputs a signal as shown in FIG. 5F.

In other words, the first NAND gate 140e in the second logic operation unit 140 has the NOR gate 140a, the first inverter 140b, and the third inverter 140d because the signal of the first logic operation unit 110 is "0". ) And " 1 " as shown in Fig. 5E as the STOPB signal regardless of the peripheral drive clock PERICLK as shown in Fig. 5D.

Then, the third logic operation unit 150 performs a logic operation on the clock CLKI of the oscillator according to the STOPB signal " 1 " output from the second logic operation unit 140, thereby counterclocking the signal CLKIX of the clock CLKI of the oscillator. )

That is, the second NAND gate 150a in the third logic operation unit 150 negatively multiplies the clock CLKI of the oscillator according to the STOPB signal "1" output from the second logic operation unit 140 to clock the oscillator. Outputs the opposite signal (CLKIX) of (CLKI).

Subsequently, the fourth logic operation unit 160 performs a logic operation on the signal CLKIX of the third logic operation unit 150 according to the signal CLOCKFB of the sleep mode control unit 130 and outputs the resultant signal. .

That is, the third NAND gate 160a in the fourth logic calculator 160 negates the signal CLKIX of the third logic calculator 150 according to "0", which is the signal CLOCKFB of the sleep mode controller 130. Logically multiplies and outputs "1".

Then, the core clock generator 180 fixes the core clock CORECLK according to "1" fixed by the first logic calculator 160.

In addition, the fifth logic calculator 170 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the set signal "1" and outputs the resultant signal.

That is, the fifth logic operation unit 170 negatively multiplies the signal CLKIX of the third logic operation unit 150 according to the set signal “1” to normally output the clock CLKI of the oscillator. .

Then, the peripheral device driving clock generator 190 normally outputs the peripheral device driving clock PERICLK according to the signal of the fifth logical operation unit 170.

In this state, when an interrupt occurs in the sleep mode controller 130 as shown in FIG. 6G, the output is changed to “1” as shown in FIG. 6C and is transferred to the first logic operation unit 110. A STOPRELB signal as shown in 6b is input, logically calculated, and output.

Then, since the signal of the first logic operation unit 110 is "0", the second logic operation unit 140 outputs the output as shown in FIG. 6E regardless of the peripheral device driving clock PERI CLK as shown in FIG. 6F. Outputs "1" as the signal STOPB.

Accordingly, the fourth logic operation unit 160 performs a logic operation on the signal CLKIX of the third logic operation unit 150 according to the signal CLOCKFB of the sleep mode control unit 130, and outputs the resultant signal. do.

That is, the third NAND gate 160a in the fourth logic calculator 160 negates the signal CLKIX of the third logic calculator 150 according to "1", which is the signal CLOCKFB of the sleep mode controller 130. Logically multiply and output the clock CLKI of the oscillator normally.

Then, the core clock generator 180 normally performs a core clock CORECLK according to the signal output from the first logic calculator 160.

In addition, the fifth logic calculator 170 performs a logic operation on the signal CLKIX of the third logic calculator 150 according to the set signal "1" and outputs the resultant signal.

That is, the fifth logic operation unit 170 negatively multiplies the signal CLKIX of the third logic operation unit 150 according to the set signal “1” to normally output the clock CLKI of the oscillator. .

Then, the peripheral device driving clock generator 190 normally outputs the peripheral device driving clock PERICLK according to the signal of the fifth logical operation unit 170.

The above operation will be described with reference to the transition state diagram as shown in FIG. 3.

First, when the power is turned on, the CPU enters an active state through an exception process in the exception state and performs a normal operation to execute a series of programs.

Here, the active state is an exception source for transitioning back to the active state when an error occurs when the transition from the exception state to the active state occurs. Output

Thereafter, if there is no instruction for a predetermined time in the active state, the CPU sets a register for transitioning to a sleep mode to reduce power consumption, and then sleep mode. Transition to to stop the operation and keep the contents of the register or cache in the previous state.

When the predetermined time elapses, the CPU automatically switches to the stop mode, stops the operation, and stops the peripheral device function.

In addition, the transition from the exception mode to the sleep mode is performed by setting a register as in the transition from the active state to the sleep mode. Will be a transition to).

In addition, functions such as phase locked loops (PLL) and oscillators will stop.

The release from the stop mode to the sleep mode is made possible by adjusting the stop-release pin of the CPU.

In this state, when a reset occurs from the outside, the CPU transitions to the exception state in the stop mode and the CPU transitions to the active state by performing an exception state. do.

As described above, the apparatus and method for preventing power consumption in the electronic device according to the present invention may transition from the exception state to the sleep mode as well as in the active state, and in the sleep mode. Transition and Stop to Sleep Mode and Stop Mode by Enabling Transition from Sleep Mode to Stop Mode and Transition from Stop Mode to Sleep Mode There is an effect that can diversify the process of returning to the active state from the stop mode.

Claims (7)

An apparatus for preventing power consumption in an electronic device including a resistor and a sleep mode controller, First logical operation means for performing a logical operation on the reset bar signal and the stop mode release request input STOPRELB and outputting a result signal; Second logical operation means for performing a logic operation on the signal of the register and the sleep mode controller and a peripheral device driving clock (PERI CLK) and outputting the resultant signal STOPB; Third logical operation means for performing a logic operation on the signal CLKI of the oscillator according to the signal STOPB of the second logic operation means, and outputting a resultant signal; Fourth logic calculating means for performing a logic operation on a signal of a third logic calculating means according to the signal CLOCKFB of the sleep mode controller and outputting a resultant signal; And fifth logic calculating means for logically calculating the signal of the third logic calculating means according to the set signal and outputting the resultant signal. The method of claim 1, And the first logic calculating means is an AND gate which multiplies a reset bar signal and a stop mode release request input STOPRELB and outputs a resultant signal. The method of claim 1, The second logic calculating means comprises: a NOR gate which negatively sums a signal CLOCKFB of the sleep mode controller and a signal of a stop mode region of a register and outputs a result signal; A first inverter for inverting and outputting a signal of the NOR gate; A second inverter for inverting and outputting a clock of a peripheral device; A third inverter for inverting and outputting a signal of the first inverter according to the peripheral device driving clock PERI CLK and a second inverter; A first NAND gate which negatively multiplies the signal of the first logic calculating means and the signal of the second inverter and outputs the resultant signal STOPB; A fourth inverter for feeding back and inverting the signal of the first NAND gate and outputting a resultant signal; Power consumption in the electronic device, characterized in that consisting of a transmission gate that is turned on according to the signal of the third inverter and the peripheral device driving clock (PERI CLK) to output to the input terminal of the first NAND gate Prevention device. The method of claim 1, And the third logic calculating means is a second NAND gate which negatively multiplies the clock of the oscillator and the signal STOPB of the third logic calculating means and outputs a resultant signal. The method of claim 1, And the fourth logic calculating means comprises a third NAND gate which negatively multiplies the signal CLOCKFB of the sleep mode controller and the signal of the third logic calculating means and outputs a resultant signal. Burnout prevention device. The method of claim 1, And the fifth logic calculating means is a fourth NAND gate which negatively multiplies the signal of the fourth logic calculating means and the set signal and outputs a resultant signal. In the method for preventing power consumption in an electronic device which transitions from an exception state to an active state or returns from the stop mode to the exception state, Setting a register in the exception state to transition to a sleep mode and returning to the exception state when an interrupt or reset occurs; After the predetermined time has elapsed in the sleep mode, the device automatically transitions to the stop mode and returns to the sleep mode when the stop mode release pin is operated. Method for preventing power consumption in electronic equipment, characterized in that.