KR20000001395A - Method of fabricating non-volatile memory device - Google Patents

Abstract

PURPOSE: A method enables to form a buried N+ diffusion layer uniformly in the whole region of a memory cell and to assure punch-through margin of a cell transistor by assuring the distance between the buried N+ diffusion layers to the utmost. CONSTITUTION: A method comprises the steps of: forming a pad oxide(101) and a silicon nitride film(102) on top of a semiconductor substrate(100) in sequence and defining an active region and a separation region by patterning the silicon nitride film; forming a field oxide(104) on the separation region by thermal oxidation process; forming a photoresist film pattern defining a region, where is a buried N+ diffusion layer(106); removing the photoresist film pattern after etching the silicon nitride film using the silicon nitride film as a mask; and removing the silicon nitride film after forming the N+ diffusion layer by ion implantation of N type impurity.

Description

Manufacturing method of nonvolatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to secure punch-through margins of a cell transistor and to form a buried N ⁺ diffusion layer uniformly in all regions of a memory cell array. The present invention relates to a method of manufacturing a NOR type flat-cell mask ROM.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output.

Among these ROM products, the cell structure of the mask ROM is largely classified into NOR type and NAND type. In the ROM ROM of 4Mb and 16Mb class, the NAND cell structure which is advantageous for high integration is adopted. Conventional NOR-type cells are easy to speed up due to high cell current, but have a disadvantage in that the cell area becomes large, and NAND-type cells have a big advantage that a small cell current but a small cell area can realize high integration. Accordingly, conventionally, the NAND type cell structure which is advantageous for high integration is mainly adopted.

Recently, however, NOR-type flat-cells (cells without a field oxide layer in the cell array for device isolation) have been developed that can be made as small as NAND-type cells while maintaining the advantages of the NOR-type cells. This NOR type flat-cell is not only capable of high speed and low voltage due to high cell current and cell uniformity, but also a multi-bit cell (MBC) storing multiple pieces of information in one cell or Facilitate the development of multi-level cells (MLC).

1 is a plan view of a conventional NOR type flat-cell mask ROM.

Referring to FIG. 1, a conventional NOR type flat-cell mask ROM is repeated in a horizontal direction while a plurality of buried N ⁺ diffusion layers 16 provided as a source / drain of a cell transistor on a surface of a semiconductor substrate extend in a vertical direction. And a plurality of word-lines 20, which serve as gate electrodes of the cell transistors, have a memory cell array of a matrix structure which extends orthogonally and overlaps the buried N ⁺ diffusion layer 16.

Referring to the operation of the unit cell in the NOR-type flat-cell mask ROM having the above-described structure, when the fixed voltage is applied to the selected word line and the low level voltage is applied to the unselected word line, the buried N ⁺ diffusion layer and the buried type If the threshold voltage (Vth) of the cell transistor is lower than the voltage of the select word line due to the difference in the impurity concentration in the channel region between the N ⁺ diffusion layers, the select cell is turned on and the data " 1 " Outputs On the contrary, if the threshold voltage of the cell transistor is higher than the voltage of the select word line, the select cell is turned off and outputs data "0".

Since the flat-cell mask ROM comprises only the entire region of the memory cell array as the active region, no field oxide film is formed between the buried N ⁺ diffusion layer and the buried N ⁺ diffusion layer. To achieve a process simplification to reduce the size of cells by the removal of this field oxide film, but, on the other hand a field oxide film is not due to become a device isolation property between the buried word line not covered type N ⁺ diffusion layer and the buried type N ⁺ diffusion layer vulnerable there is a problem. In addition, in the flat-cell mask ROM, the distance between adjacent buried N ⁺ diffusion layers means the channel length of the cell transistor. Therefore, securing the punch-through margin of the cell transistor by the definition of the channel length is the most important variable for the high integration of the cell. Becomes Therefore, a process of forming a buried N ⁺ diffusion layer, that is, a photolithography process of determining an ion implantation region when ion implanting N-type impurities using a photomask is very important.

2 to 4 are cross-sectional views illustrating a method of manufacturing a conventional NOR type flat-cell mask ROM.

Referring to FIG. 2, after forming a P-well in which a cell transistor and an NMOS transistor of a peripheral circuit part are to be formed in a predetermined portion of the ^P_ semiconductor substrate 10 by a conventional well forming process, a thermal oxidation process is formed on the resultant. The pad oxide film 11 is formed. A silicon nitride film (Si ₃ N ₄ ) 12 is formed on the pad oxide film 11 as an anti-oxidation film by low pressure chemical vapor deposition (LPCVD). The silicon nitride film 12 is dry-etched by a photolithography process and an etching process to define an active region and an isolation region, and then a thermal oxidation process is performed on the resultant to form the field oxide layer 14. At this time, the entire area of the memory cell array is composed only of the active area.

Referring to FIG. 3, after the silicon nitride film 12 is removed, the P-well region is opened through a photolithography process, and then N-field ion implantation and ion implantation for adjusting the threshold voltage of the NMOS transistor are sequentially performed. Subsequently, an N-well (not shown) in which a PMOS transistor of a peripheral circuit part is to be formed is formed in a predetermined portion of the substrate 10 by a normal well forming process. After opening the N well region through a photolithography process, an ion implantation process for adjusting the threshold voltage of the P-field ion implantation and the PMOS transistor is sequentially performed.

Referring to FIG. 4, after the photoresist film is coated on the resultant, the photoresist film pattern 15 is formed by exposing and developing the photoresist film. N-type impurities such as arsenic (As) are ion-implanted with energy of 50 keV and a dose of 1.0E15 # / cm ² using the photoresist film pattern 15 as an ion implantation mask to provide a source / drain of a cell transistor. An investment type N ⁺ diffusion layer 16 is formed.

Subsequently, after the photoresist film pattern 15 is removed, a gate oxide film (not shown) is grown on the substrate 10. By depositing and patterning a conductive layer on the gate oxide layer, a gate electrode of a cell transistor provided as a word line and a gate electrode (not shown) of a peripheral circuit transistor are formed.

According to the conventional method described above, in the photolithography process for forming the buried N ⁺ diffusion layer of FIG. 4, the space between the photoresist film pattern 15 and the photoresist film pattern 15 is buried N ⁺ diffusion layer ( 16), and the region covered by the photoresist film pattern 15 becomes the channel region of the cell transistor. In order to secure the punch-through margin of the cell transistor, the channel length must be increased, and thus the width of the buried N ⁺ diffusion layer 16, that is, the space between the photoresist layer patterns 15 should be reduced as much as possible. However, the space between the photoresist film patterns 15 cannot be reduced below the limit resolution of the photolithography process, and as shown in FIG. 5, the lower portion of the photoresist film pattern 15 is under-cut. The phenomenon occurs that the critical dimension (CD) of the space becomes large. As a result, the width of the buried N ⁺ diffusion layer 16 is increased to further weaken the punch-through margin of the cell transistor. The reason why the lower portion of the photoresist film pattern is undercut is that incident light is reflected and reflected by an insulating film such as an oxide film formed on the substrate as an N-type impurity ion implantation buffer layer during the photolithography process for forming the buried N ⁺ diffusion layer. This is because partial exposure interference occurs under the photoresist film pattern while being scattered. In order to solve this problem, the photolithography process may be performed in a bare state without any film on the substrate or in a state where an oxide film is formed to a thickness of 600 Å or more. Contamination may cause reliability problems. In the latter case, since the ion implantation energy of the N-type impurity must be increased, the buried N ⁺ diffusion layer is widened in the lateral direction so that the improvement effect on the undercut phenomenon cannot be obtained.

In addition, in the flat-cell mask ROM, the entire area of the memory cell array is composed of an active area, and thus, in the photolithography process for forming a buried N ⁺ diffusion layer, as shown in FIG. 6, the center and the edge of the memory cell array are shown. The difference in the thickness of the photoresist film 15 occurs due to the step of the field oxide film 14 in between. The difference in thickness of the photoresist film 15 affects the space between the photoresist film patterns during the photolithography process, resulting in poor uniformity of the space critical dimension CD between the center and the edge of the memory cell array. In other words, the difference in the thickness of the photoresist film causes a standing wave phenomenon during the photolithography process, which is caused by reinforcement interference and offset by the phase difference between the reflected light by the substrate under the photoresist film and the incident light for exposing the photoresist film. It means a phenomenon in which the photoresist film is exposed differently according to the step due to the interference. The non-uniformity of the space critical dimension caused by the standing wave phenomenon causes a problem in that the channel length of the cell transistor is changed for each specific position. The change width of the space critical dimension between the photoresist films is sensitive to the reflectance of the substrate type, the type and thickness of the photoresist film, and the like.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of uniformly forming a buried N ⁺ diffusion layer in all regions of a memory cell array. It is.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of securing a punch-through margin of a cell transistor by ensuring a maximum distance between an buried N ⁺ diffusion layer and an buried N ⁺ diffusion layer.

1 is a plan view of a conventional NOR type flat-cell mask ROM.

2 to 4 are cross-sectional views for explaining a method of manufacturing a conventional NOR type flat-cell mask ROM.

FIG. 5 is a cross-sectional view illustrating an undercut formed under a photoresist film pattern in a photolithography process for forming a buried N ⁺ diffusion layer of FIG. 4 ^; FIG.

FIG. 6 is a cross-sectional view illustrating a difference in thickness of a photoresist film between a center portion and an edge portion of a memory cell array in a photolithography process for forming a buried N ⁺ diffusion layer of FIG. 4; FIG.

7 to 10 are cross-sectional views illustrating a method of manufacturing a NOR type flat-cell mask ROM according to a first embodiment of the present invention.

11 is a cross-sectional view for explaining a method of etching a silicon nitride film according to a second embodiment of the present invention.

12 to 14 are cross-sectional views illustrating a method of manufacturing a NOR type flat-cell mask ROM according to a third embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 101 pad oxide film

102 silicon nitride film 104 field oxide film

105: insulating film 106: buried N ⁺ diffusion layer

In order to achieve the above object, the present invention includes forming a pad oxide film and a silicon nitride film sequentially on the semiconductor substrate, and patterning the silicon nitride film to define an active region and an isolation region; Forming a field oxide film in the device isolation region through a thermal oxidation process; Forming a photoresist film pattern defining a region in which an buried N ⁺ diffusion layer is to be formed on top of the resultant product; Etching the silicon nitride layer using the photoresist layer pattern as a mask; Removing the photoresist layer pattern and ion implanting N-type impurities into an exposed substrate using the silicon nitride layer as a mask to form a buried N ⁺ diffusion layer; And it provides a method of manufacturing a nonvolatile memory device comprising the step of removing the silicon nitride film.

Preferably, in the etching of the silicon nitride layer using the photoresist layer pattern as a mask, the silicon nitride layer is etched to generate a tail under the silicon nitride layer.

Preferably, in the step of etching the silicon nitride film using the photoresist film pattern as a mask, the silicon nitride film is etched obliquely at a predetermined angle.

According to an aspect of the present invention, there is provided a semiconductor device comprising: forming a pad oxide film and a silicon nitride film sequentially on a semiconductor substrate, and patterning the silicon nitride film to define an active region and an isolation region; Forming a field oxide film in the device isolation region through a thermal oxidation process; Forming a photoresist film pattern defining a region in which an buried N ⁺ diffusion layer is to be formed on top of the resultant product; Etching the silicon nitride layer using the photoresist layer pattern as a mask; Removing the photoresist film pattern; Forming insulating film spacers on sidewalls of the silicon nitride film; Forming a buried type N ⁺ diffusion layer by ion implanting N-type impurities into the exposed substrate using the silicon nitride film and the insulating film spacer as a mask; And removing the silicon nitride layer and the insulating layer spacer.

Preferably, the insulating film spacer is formed of a material having a high etching selectivity with respect to the silicon nitride film. More preferably, the insulating film spacer is formed of polysilicon.

As described above, according to the present invention, the photolithography process for forming the buried N ⁺ diffusion layer is performed without removing the silicon nitride film used as the antioxidant film when forming the field oxide film. Therefore, since the difference in the photoresist film thickness does not occur between the center portion and the edge portion of the memory cell array, the space critical dimension between the photoresist film patterns is uniform, so that the buried N ⁺ diffusion layer can be uniformly formed.

In addition, since the silicon nitride film is used as an ion implantation mask, ion implantation of N-type impurities is carried out, and ion implantation can be performed with a smaller space critical dimension than the critical dimension of the mask space obtained at the limit resolution of the photolithography process. As a result, since the width of the buried N ⁺ diffusion layer can be reduced, a punch-through margin can be secured by increasing the channel length of the cell transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

7 to 10 are cross-sectional views illustrating a method of manufacturing a NOR type flat-cell mask ROM according to a first embodiment of the present invention.

7 shows the step of forming the field oxide film 104. First, a P-well in which a cell transistor and an NMOS transistor of a peripheral circuit part are formed at a predetermined portion of the ^P_ semiconductor substrate 100 is formed by a conventional well forming process, and then a thermal oxidation process is performed on the resultant pad. An oxide film 101 is formed. A silicon nitride film (Si ₃ N ₄ ) 102 is formed on the pad oxide film 101 to have a thickness of about 1500 kPa by a low pressure chemical vapor deposition (LPCVD) method. The silicon nitride film 102 is dry-etched by a photolithography process and an etching process to define an active region and an isolation region, and then a thermal oxidation process is performed on the resultant to form the field oxide layer 104. At this time, the entire area of the memory cell array is composed only of the active area.

8 shows the step of forming an buried N ⁺ diffusion layer 106. After the field oxide film 104 is formed as described above, a photoresist film (not shown) is applied while the silicon nitride film 102 is not removed. In this case, the photoresist film is applied to a uniform thickness in all regions of the memory cell array. Subsequently, a photoresist film is exposed and developed by applying a mask for forming a buried N ⁺ diffusion layer to form a photoresist film pattern. The silicon nitride layer 102 is dry etched using the photoresist layer pattern as an etching mask. In this case, as shown in FIG. 9, a tail is generated under the silicon nitride film 102, thereby reducing the space between the silicon nitride films 102. Preferably, the channel length of the cell transistor may be increased by severely generating a tail under the silicon nitride layer 102 to minimize the critical dimension of the mask space during the subsequent implantation of the N-type impurity.

Subsequently, after the photoresist film pattern is removed, N-type impurities such as arsenic (As) are ion implanted with energy of 50 keV and a dose of 1.0E15 # / cm ² using the silicon nitride film 102 as an ion implantation mask. A buried N ⁺ diffusion layer 106 provided as the source / drain of the cell transistor is formed.

Referring to FIG. 10, after the silicon nitride film 102 is removed, the P-well region is opened through a photolithography process, and ion implantation for controlling the threshold voltage of the N-field ion implantation and the NMOS transistor is sequentially performed. Subsequently, an N-well (not shown) in which a PMOS transistor of a peripheral circuit part is to be formed is formed in a predetermined portion of the substrate 10 by a normal well forming process. After opening the N well region through a photolithography process, an ion implantation process for adjusting the threshold voltage of the P-field ion implantation and the PMOS transistor is sequentially performed. Next, after forming a gate oxide film (not shown) on the active region of the substrate 100, the gate electrode and the peripheral circuit of the cell transistor provided as a word line by depositing and patterning a conductive layer thereon A gate electrode (not shown) of the transistor is formed.

11 is a cross-sectional view for describing a method of etching a silicon nitride film according to a second embodiment of the present invention.

Referring to FIG. 11, after forming a field oxide film (not shown) in the same manner as in the first embodiment of the present invention described above, a photo for forming an buried N ⁺ diffusion layer on the silicon nitride film 102. A resist film pattern (not shown) is formed. Subsequently, the silicon nitride layer 102 is obliquely etched at a predetermined angle by using the photoresist layer pattern as an etching mask. Such oblique etching has an effect of reducing the space between the silicon nitride films 102. Therefore, by implanting N-type impurities using the inclined-etched silicon nitride film 102 as an ion implantation mask, the width of the buried N ⁺ diffusion layer 1060 may be reduced.

12 to 14 are cross-sectional views illustrating a method of manufacturing a NOR type flat-cell mask ROM according to a third embodiment of the present invention.

Referring to Fig. 12, after forming a field oxide film (not shown) in the same manner as in the first embodiment of the present invention described above, the buried type N ⁺ diffusion layer on top of the silicon nitride film 102 provided as an anti-oxidation film A photoresist film pattern (not shown) for formation of a film is formed. Subsequently, the silicon nitride layer 102 is dry etched using the photoresist layer pattern as an etching mask. After removing the photoresist layer pattern, an insulating layer 105 is formed on the resultant. Preferably, the insulating film 105 is formed of a material having a high etching selectivity with respect to the silicon nitride film 102. More preferably, the insulating film 105 is formed by depositing polysilicon by low pressure chemical vapor deposition (LPCVD).

Referring to FIG. 13, the insulating layer 105 is etched back to form insulating layer spacers 105a on both sidewalls of the silicon nitride layer 102.

Referring to FIG. 14, N-type impurities such as arsenic (As) are implanted with energy of 50 keV and a dose of 1.0E15 # / cm ² using the silicon nitride film 102 and the insulating film spacer 105a as ion implantation masks. This forms the buried N ⁺ diffusion layer 106 provided as a source / drain of the cell transistor.

According to the third embodiment of the present invention, the critical dimension of the mask space is reduced by the width of the insulating film spacer during the ion implantation process of the N-type impurity. Accordingly, the channel length of the cell transistor is increased by the width of the insulating layer spacer, thereby securing a punch-through margin. In addition, since the width of the insulating film spacer is determined according to the deposition thickness of the insulating film, the channel length can be easily adjusted during the deposition process of the insulating film for forming the spacer.

As described above, according to the method of manufacturing the nonvolatile memory device of the present invention, a photolithography process for forming an buried N ⁺ diffusion layer is performed without removing a silicon nitride film used as an antioxidant film during formation of a field oxide film. . Therefore, since the difference in the photoresist film thickness does not occur between the center portion and the edge portion of the memory cell array, the space critical dimension between the photoresist film patterns is uniform, so that the buried N ⁺ diffusion layer can be uniformly formed.

In addition, since the silicon nitride film is used as an ion implantation mask, ion implantation of N-type impurities is carried out, and ion implantation can be performed with a smaller space critical dimension than the critical dimension of the mask space obtained at the limit resolution of the photolithography process. As a result, since the width of the buried N ⁺ diffusion layer can be reduced, a punch-through margin can be secured by increasing the channel length of the cell transistor.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Sequentially forming a pad oxide film and a silicon nitride film on the semiconductor substrate, and patterning the silicon nitride film to define an active region and an isolation region; Forming a field oxide film in the device isolation region through a thermal oxidation process; Forming a photoresist film pattern defining a region in which an buried N ⁺ diffusion layer is to be formed on top of the resultant product; Etching the silicon nitride layer using the photoresist layer pattern as a mask; Removing the photoresist layer pattern and ion implanting N-type impurities into an exposed substrate using the silicon nitride layer as a mask to form a buried N ⁺ diffusion layer; And And removing the silicon nitride film. The non-volatile memory device of claim 1, wherein in the etching of the silicon nitride layer using the photoresist pattern as a mask, the silicon nitride layer is etched to generate a tail under the silicon nitride layer. Way. The method of claim 1, wherein in the etching of the silicon nitride layer using the photoresist pattern as a mask, the silicon nitride layer is obliquely etched at a predetermined angle. Sequentially forming a pad oxide film and a silicon nitride film on the semiconductor substrate, and patterning the silicon nitride film to define an active region and an isolation region; Forming a field oxide film in the device isolation region through a thermal oxidation process; Forming a photoresist film pattern defining a region in which an buried N ⁺ diffusion layer is to be formed on top of the resultant product; Etching the silicon nitride layer using the photoresist layer pattern as a mask; Removing the photoresist film pattern; Forming insulating film spacers on sidewalls of the silicon nitride film; Forming a buried type N ⁺ diffusion layer by ion implanting N-type impurities into the exposed substrate using the silicon nitride film and the insulating film spacer as a mask; And And removing the silicon nitride film and the insulating film spacer. The method of claim 4, wherein the insulation spacer is formed of a material having a high etching selectivity with respect to the silicon nitride layer. The method of claim 5, wherein the insulation spacer is formed of polysilicon.