KR20000001334A - Booting circuit for pipe line control processor - Google Patents

Abstract

PURPOSE: A booting circuit for a pipe line control processor is provided for a safe operation on power-on or reset. CONSTITUTION: The booting circuit for a pipe line control processor comprises:a counting device for executing a counting operation by responding to an outer clock and keeping a counted number on a certain cycle; an enable device for outputting an enable signal of a state machine by responding to a counting signal output from the outer clock and the counting device; a state machine(28) for outputting a first, a second, and a third reset signals by responding to the outer clock and the state machine enable.

Description

Boot Circuit for Pipeline Control Processor

TECHNICAL FIELD The present invention relates to a processor, and more particularly, to a booting circuit of a pipelined control processor for stable operation at power-on and reset.

A conventional sequential controlled processor fetches an instruction indicated by a program counter (hereinafter referred to as a PC), stores it in an instruction register (hereinafter referred to as IR), and decodes the instruction again. decoding) receives the instruction from the block, analyzes which instruction, and executes the instruction in an execution block inside the processor. The sequential control processor in turn takes one instruction to the IR, executes it, and then the next instruction back to the IR so that the IR only needs to accept new data once during the execution of the instruction. In this case, there is little possibility that dummy data enters the IR by sending a control signal for receiving new data for each instruction.

Unlike the sequential control processor, the pipeline control processor continuously receives new instructions to the IR every cycle for pipeline operation, and sends control signals to the IR when necessary. In other words, the IR automatically accepts new data every cycle unless the command specifically sends a control signal. However, this is not a problem during the pipeline, but when restarting the processor, for example at power-on or reset, the control may not know the IR data before the instructions specified by the PC are fetched into the IR. ) Or accept dummy data. If such erroneous data enters the decoding block and is performed, the operation of the processor is unpredictable.

1 shows a conventional timing diagram of a pipeline control processor at power-on. An example is described where a pipeline is composed of three stages and instructions are processed in the order of PC-IR-execution blocks. At the first clock 10, the PC starts to access the 0000h (hexa) address of the memory where the instruction is stored, and at the second clock 12, the command at the 0000h address designated by the PC enters the IR. However, due to pipeline control characteristics, IR and other registers also accept instructions unconditionally from the first clock 10. At this time, the received instructions are interpreted as other instructions or exist in conventional instruction codes when they are decoded into unknown data. If not, the processor may hang.

In conclusion, there is a problem that the IR and other registers accept error data before reading instructions designated by the PC at power-on or reset in the pipeline control processor, causing the processor to malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a booting circuit for a pipeline control processor to ensure the correct operation of the pipeline control processor when the pipeline is newly restarted, such as power-on and reset. There is a purpose.

1 is a timing diagram of a pipeline control processor at power-on according to the prior art.

2 is a boot circuit block diagram in accordance with the present invention.

3 is a state machine state diagram in accordance with the present invention.

4 is a timing diagram of a boot circuit in accordance with the present invention.

* Description of the main parts of the drawing

20: mode 8 counter 22, 26: logical gate

24: D-Flip-Flop 28: State Machine

30: synchronizer 32: three-phase buffer

The present invention for achieving the above object comprises a counting means for performing a counting operation in response to an external clock, and maintaining the counted value in any cycle; Enable means for outputting a state machine enable signal in response to a counting signal output from said external clock and said counting means; A state machine outputting a first reset signal, a second reset signal, and a third reset signal in response to the external clock and the state machine enable; And internal clock generation means for transmitting the external clock to the internal clock of the processor in response to a counting signal output from the counting means.

The present invention resets the registers that drive the operation of the processor, such as a PC or an IR, to the initial value at the processor reset when the pipeline is first started in the pipeline control processor so that dummy data cannot enter the IR and other registers. Again, it's about booting circuits that release the reset when they should work normally in the pipeline.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a boot circuit of the present invention, where 20 is a binary mode 8 counter, 21 is a state machine enable portion, 22 and 26 are AND gates, 24 is a D-flipflop, and 28 is a state A state machine, 30 denotes a synchronizer, 32 denotes a tri-state buffer, respectively.

The mode 8 counter 20 is a binary counter that counts from "0" to "7" and waits for the external clock to stabilize after the processor is powered on. When " 7 " is counted, the output signal of the AND gate 22 becomes " 1 ", and the output signal of " 1 " is fed back to the mode 8 counter 20 so that the counter holds " 7 " To keep the value.

The state machine enable unit 21 generates an enable signal ASM_enable that enables the state machine 28 in response to the output of the mode 8 counter 20, but only during those cycles in which the counter becomes " 7 ". Configured to remain in a "high" state. The state machine enable unit 21 outputs the D-flip flop 24 which latches the output signal of the AND gate 22 in synchronization with an external clock, and the AND gate 22 which ANDs the output signal of the counter. And an AND gate 26 that receives the inverted D-flip-flop 24 output and outputs ASM_enable.

The state machine 28 has a function of transitioning from the current state to the next state in response to an external clock and enable signal ASM_enable, and is used to reset the PC, IR and other registers of the pipeline control processor, respectively. The second and third reset signals are output.

The three-phase buffer 32 transfers an external clock to the internal clock of the microprocessor in response to the output of the mode 8 counter 20. In other words, when the counter counts "7", it is enabled and continues to deliver the external clock to the internal clock.

The synchronizer 30 finally outputs the first, second and third reset signals in synchronization with the internal clock signal. This is to pre-tune each register to the operating phase, since most processors that operate in a pipelined manner use multi-phase.

Next, when the state machine 28 is examined in detail, when the pipeline is first started in the pipeline control processor, the dummy data may be reset by initializing the registers that drive the operation of the processor, such as a PC or an IR, to an initial value of the processor. To prevent the PC from entering the IR and other registers and again to reset the point in time when they should be operating normally on the pipeline, the state machine 28 is responsible for all of the PC, IR, and other registers when the internal clock is not applied. Have initial value, only reset the IR and other registers on the 1st internal clock, reset the PC to normal operation (ie have a valid address for instruction access), and IR on the 2nd internal clock Undo the reset and reset all resets on the third internal clock.

3 is a state diagram for a state machine. Looking at the specific state transitions of state machine 28, first state 40 is an idle state, which is either before the pipelined microcontroller is powered on but before the pipeline operation has been performed, or before the pipelined operation. After startup, the pipeline is normally in progress, and the boot circuit does nothing. When the ASM_enable signal is input "high" in the first state 40, the state transitions to the second state 42 to start the operation of the full-fledged boot circuit. The second state 42 resets the PC, IR, and other registers by enabling the first, second, and third reset signals. At this time, the internal clock is applied from the second state 42 through the boot circuit. Transition from the second state 42 to the third and fourth states 44 and 46 in synchronization with the internal clock is performed. In the third state 44, only the first reset signal is disabled to access instructions to the PC. Allow a valid address to be accepted and the remaining second and third reset signals continue to enable so that the IR and other registers continue to reset. The fourth state 46 disables the second reset signal so that the fetched command can be stored in the IR. The fourth state 46 is shifted to the first state 40 in synchronization with the internal clock, and the third reset signal is disabled so that all registers normally receive data and perform a pipeline operation normally.

Figure 4 shows a timing diagram for the boot circuit of the present invention.

It is assumed that after the power-on and before the full pipeline operation is performed, the counting operation is performed until the external clock is stabilized by the mode 8 counter 20. At this time, the external clock continues to clock. When the counting result is "7", the three-phase buffer 32 is enabled and the external clock is transferred to the internal clock to proceed with the clocking operation of the internal clock, and the AND gate 22 outputs a "high" signal. do. The AND gate 26 is then the "low" signal of the D-flip-flop 24 (the value latched by the cycle immediately preceding the cycle counting "7") and the "high" of the AND gate 22. In response to the output signal, an ASM_enable signal of "high" is output to the state machine 28. Accordingly, state machine 28 transitions from first state 40 to second state 52 by the ASM_enable signal to enable the first, second, and third reset signals to " high " And other registers are reset to initial values to block the inflow of dummy data.

In the next cycle of the external clock signal, the D-flip-flop 24 outputs a "high" signal (a value latched in the cycle counting "7") to the AND gate 26 to output a "low" ASM_enable signal. Outputs State machine 28 thus transitions from second state 42 to third state 44 to disable the first reset signal " low " to receive data 0000h into the PC. In this case, since the remaining reset signal is continuously enabled as "high", the IR and other registers are reset to initial values so that the inflow of dummy data is blocked.

In the next cycle of the external clock signal, it continues to output a "low" ASM_enable signal. State machine 28 thus transitions from third state 44 to fourth state 46, disabling the second reset signal " low " to accept data (0001h, 0000h) from PC and IR. Here, since only the third reset signal is continuously enabled as "high", the other register is reset to an initial value and the inflow of dummy data is blocked.

In the next cycle, in response to an external clock signal, state machine 28 transitions from fourth state 46 to first state 40 to disable the third reset signal to " low " Allows the register to accept data (0002h, 0001h, 0000h). Here, all reset signals are disabled to start full pipeline operation.

As described above, it can be seen that the present invention accurately blocks dummy data from flowing into the PC, the IR, and other registers.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above has the effect that can be employed in the pipeline control microprocessor to ensure the accuracy of the operation of the microprocessor by blocking the dummy data when starting the pipeline operation at reset or power-on.

Claims (11)

In a processor operating in a pipelined manner, Counting means for performing a counting operation in response to an external clock and maintaining a counted value in any cycle; Enable means for outputting a state machine enable signal in response to a counting signal output from said external clock and said counting means; A state machine outputting a first reset signal, a second reset signal, and a third reset signal in response to the external clock and the state machine enable; And Internal clock generation means for transmitting the external clock to the internal clock of the processor in response to a counting signal output from the counting means; Boot circuit consisting of. The method of claim 1, Synchronization means for outputting the first, second, and third reset signals to the processor in synchronization with the internal clock; Boot circuit made further comprising. The method according to claim 1 or 2, The enable means And outputting said state machine enable signal with an arbitrary level enabling said state machine only in said any cycle in response to a value counted in said any cycle. The method of claim 3, wherein The enable means Latching means for latching a counting signal output from said counting means in response to said external clock; And Logic means for receiving the output of the latching means and the counting signal inverted and logically multiplied to output as the state machine enable signal Boot circuit consisting of. The method according to claim 1 or 2, The first, second and third reset signals are And a signal for resetting a program counter, an instruction register, and other registers of the processor, respectively. The method according to claim 1 or 2, The internal clock generating means Triple buffer enabled by the counted value in the arbitrary cycle to transfer the external clock to the internal clock of the microprocessor Boot circuit comprising a. The method according to claim 1 or 2, The state machine And a first state, a second state, a third state, and a fourth state, wherein each state is controlled by the state machine enable signal and the external clock signal. The method of claim 7, wherein The state machine Outputting the first, second and third reset signals in an enabled state and transitioning to the second state when the state machine enable signal having the arbitrary level is input in the first state; Boot circuit. The method of claim 7, wherein The state machine Outputting the first reset signal in a disabled state when the second state is synchronized with the external clock signal, continuing to output the second and third reset signals in the enabled state, and transitioning to the third state Boot circuit, characterized in that. The method of claim 7, wherein The state machine Outputting the first and second reset signals in a disabled state when the third state is synchronized with the external clock signal, continuing to output the third reset signal in a disabled state, and transitioning to the fourth state Boot circuit, characterized in that. The method of claim 7, wherein The state machine When the fourth state is synchronized with the external clock signal, all of the first, second and third reset signals are output in a disabled state to transition to the first state to perform a normal pipeline operation. Boot circuit.