KR20000000940A - Test system for integrated circuit package use and timing error measuring method thereof - Google Patents

Abstract

PURPOSE: A test system for an integrated circuit package use is provided to measure a timing error generated from the system itself. CONSTITUTION: The test system for an integrated circuit package use and the timing error measuring method comprise: a test system for an integrated circuit package use(201) having a driver(211), buffers(221, 223), a test signal output unit(231), a response signal input unit(233), a switching device(241), and a receiver(251); a load board(205) having an input terminal(261) and an output terminal(263) and made into a dual transmission line; and an integrated circuit package installing unit(271) for installing the integrated circuit package, placed between the input terminal and the output terminal.

Description

Test system for integrated circuit package and its timing error measuring method

The present invention relates to a test system for testing electrical characteristics of an integrated circuit package, and more particularly to a test system for an integrated circuit package capable of measuring timing errors of the system itself.

In general, testing the electrical characteristics and functionality of integrated circuit packages with integrated circuits requires test specifications based on the test data of the integrated circuit package, and the test specifications provide extensive assurance of the operation of the integrated circuit package. In order to determine the electrical characteristics margin (margin). The advent of high-speed memory integrated circuits, however, allows the measurement of the guard band (measurement of electrical characteristics of the memory integrated circuit) of the test system for its own set-up time and hold time measurements. Timing margins), such as timing errors of the test system itself and load-board wires, pattern traces, and sockets on which the integrated circuit package is mounted during the test. The signal loss caused by the effect is narrowed. As a result, it is difficult to accurately determine the electrical characteristics of a high-speed memory integrated circuit. Therefore, it is necessary to set a test specification considering an error of a test system. A conventional method for measuring error values of a test system including several test environment components in testing a high speed memory integrated circuit is shown in FIG. 1.

Referring to FIG. 1, the test system 101 for an integrated circuit package includes a driver 111, buffers 121 and 123, a test signal output unit 131, a response signal input unit 133, and a receiver 141. The load board 105 includes an input terminal 151, an output terminal 153, and an integrated circuit package mounting unit 161 for mounting an integrated circuit package. In order to measure the timing error of the test system 101 illustrated in FIG. 1, the input terminal 151 and the output terminal 153 of the load board 105 are connected to each other. Accordingly, the test signal S1 generated to test the integrated circuit package in the test system 101 is not inputted into the integrated circuit package, but is transmitted through the input terminal 151 and the output terminal 153 of the load board 105. 101). That is, the test signal S1 generated by the driver 111 is transmitted to the load board 105 through the buffer 121 and the test signal output unit 131, and the input terminal 151 and the output terminal of the load board 105 are transmitted. The input is again input to the test system 101 through 153, and is input to the receiver 141 through the response signal input unit 133 and the buffer 123 of the test system 101. The receiver 141 compares the test signal S1 generated by the driver 111 with the signal received by the receiver 141 to extract timing errors caused by the test environment including the test system 101 and the load board 105. Serve

As described above, according to the conventional test system 101 and the load board 105, all signal loss caused by various kinds of test environments is included, and the timing error of the test system 101 itself cannot be measured. Failure to accurately measure the timing error of the test system 101 may not accurately test the electrical characteristics of the integrated circuit package.

An object of the present invention is to provide a test system for an integrated circuit package for measuring the timing error of the system itself.

Another object of the present invention is to provide a timing error measuring method of a test system for an integrated circuit package for measuring timing errors of a test system.

1 schematically illustrates a test system and load board for a conventional integrated circuit package for measuring timing error by a test environment.

2 schematically illustrates a test system and a load board for an integrated circuit package according to a preferred embodiment of the present invention for measuring timing errors of a test system.

3 shows a smooth plot of timing errors of the test system shown in FIG.

4 is a flowchart illustrating a timing error measuring method of the test system illustrated in FIG. 3.

The present invention to achieve the above technical problem,

A test system connected to a load board on which an integrated circuit package having an integrated circuit is mounted and testing electrical characteristics of the integrated circuit package mounted on the load board, wherein the driver generates a test signal for testing the integrated circuit package. A test signal output unit connected to the load board to transfer the test signal to the load board, a response signal input unit coupled to the load board to receive a response signal output from the integrated circuit package, and the response signal input A receiver which receives a signal input through the unit and compares it with the test signal, and is connected between the test signal output unit and the response signal input unit and electrically connects the test signal output unit and the response signal input unit in response to a control signal. Letting switching number It provides an integrated circuit package for testing a system comprising a.

Preferably, further comprising a control signal generator for generating the control signal, the control signal generator is driven by a program.

The present invention to achieve the above other technical problem,

A method of measuring a timing error of a test signal generated in a test system for testing the integrated circuit package in connection with a load board on which an integrated circuit package is mounted, the method comprising: generating a test signal for testing the integrated circuit package; Receiving the test signal just before a signal is output from the test system to the outside, and comparing the timing of the generated test signal with the received test signal; Provide a measurement method.

According to the present invention, the electrical characteristics of the integrated circuit package are accurately tested.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of a test system and load board for an integrated circuit package according to a preferred embodiment of the present invention for measuring timing errors of a test system. 2, a test system 201 for an integrated circuit package according to an exemplary embodiment of the present invention includes a driver 211, buffers 221 and 223, a test signal output unit 231, a response signal input unit 233, A switching means 241 and a receiver 251. The test system 201 is an input / output split channel method. The load board 205 includes an input terminal 261 and an output terminal 263, and includes an integrated circuit package mounting unit 271 for mounting an integrated circuit package between the input terminal 261 and the output terminal 263. The load board 205 is configured of a dual transmission line (DTL).

The driver 211 generates and outputs a test signal P1 for testing an integrated circuit package. The test signal P1 output from the driver 211 arrives at the test signal output unit 231 through the buffer 221. To test the integrated circuit package, a load board 205 on which the integrated circuit package is mounted is electrically connected to the test system 201. That is, the input terminal 261 of the load board 205 and the test signal output unit 231 of the test system 201 are electrically and mechanically coupled, and the output terminal 263 and the test system 201 of the load board 205 are coupled. The response signal input unit 233 is electrically and mechanically coupled.

The test signal P1 arriving at the test signal output unit 231 is transmitted to the integrated circuit package through the input terminal 261 of the load board 205. The integrated circuit package outputs a response signal in response to the test signal P1. The response signal is transmitted to the response signal input unit 233 through the output terminal 263 of the load board 205. When the timing error of the test environment including the load board 205 is measured without testing the integrated circuit package, the input terminal 261 and the output terminal 263 of the load board 205 are directly connected. Therefore, the test signal P1 transmitted to the input terminal 261 of the load board 205 is transmitted directly to the output terminal 263 of the load board 205 without passing through the integrated circuit package.

The switching means 241 is connected between the test signal output unit 231 and the response signal input unit 233. The switching means 241 electrically connects the test signal output unit 231 and the response signal input unit 233 in response to the control signal C1 input from the outside. That is, when the control signal C1 is enabled as logic high, the switching means 241 is turned on to electrically connect the test signal output unit 231 and the response signal input unit 233. When the control signal C1 is disabled as a logic low, the switching means 241 is turned off to the test signal output unit 231 and the response signal input unit 233. ) Is electrically isolated. In order to test the electrical characteristics of the integrated circuit package mounted on the load board 205 substantially, the control signal C1 is disabled. Then, the switching means 241 is turned off so that the test signal output unit 231 is electrically connected to the input terminal 261 of the load board 205, and the response signal input unit 233 is the output terminal 263 of the load board 205. ) Is electrically connected. When the timing error of the test system 201 is to be measured, the control signal C1 is enabled and the switching means 241 is turned on. When the switching means 241 is turned on, since the test signal output unit 231 and the response signal input unit 233 are electrically connected, the test signal P1 output from the driver 211 is not transmitted to the load board 205 and the receiver is not connected. Forwarded to 251.

The receiver 251 is a signal input through the response signal input unit 233, that is, a signal from which the test signal P1 generated from the driver 211 is input through the test signal output unit 231 and the switching means 241, or The signal output from the integrated circuit package is input to the response signal input unit 233 through the output terminal 263 of the load board 205. The receiver 251 compares the signal input through the response signal input unit 233 with the test signal P1 generated by the driver 211.

The control signal C1 is enabled to measure the timing error of the test system 201. Then, the switching means 241 is turned on and the test signal P1 output from the driver 211 is buffered 221, the test signal output 231, the switching means 241, the response signal input 233 and the buffer ( It is input to the receiver 251 through 223. As the test signal P1, a pulse having a certain period is used, and the smooth plot 311 shown in FIG. 3 can be obtained by repeatedly generating the pulse. T3 shown in FIG. 3 becomes a timing error at the leading edge of the test system 201.

In order to measure the timing error due to the test environment including the load board 205, the control signal C1 is disabled. Then, the switching means 241 is turned off and the test signal P1 output from the driver 211 is buffer 221, the test signal output unit 231, the input terminal 261 of the load board 205, the load board ( It is input to the receiver 251 through the output terminal 263 of the 205, the response signal input unit 233 and the buffer 223. By using a pulse having a constant period as the test signal P1 and generating the pulse repeatedly, the seam plot 321 shown in FIG. 4 can be obtained. T2 shown in FIG. 3 is a value including timing error at the leading edge of the test system 201 and timing error at the leading edge due to the test environment such as the load board 205. Here, (T2-T3) becomes a timing error by a pure test environment, such as the load board 205 etc. which excluded the timing error of the test system 201. FIG.

4 is a flowchart illustrating a timing error measuring method of a test system for an integrated circuit package according to an exemplary embodiment of the present invention. A timing error measuring method of the test system shown in FIG. 4 will be described with reference to FIG. 2. A timing error measuring method of a test system for an integrated circuit package according to an exemplary embodiment of the present invention includes a test signal generation step 411, a test signal transmission step 421, and a test signal analysis step 431.

In the test signal generation step 411, a test signal P1 for testing an integrated circuit package is generated from the driver 211. As the test signal P1, a pulse having a constant period is used.

In the test signal transmission step 421, the test signal P1 generated in the test signal generation step 411 is transmitted to the portion where the test system 201 and the load board 205 are coupled, and the test signal P1 is It is transmitted to the receiver 251 without being output to the outside of the test system 201.

In the test signal analysis step 431, the signal received by the receiver 251 is compared with and analyzed by the test signal P1 generated by the driver 211, thereby measuring the pure timing error of the test system 201.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, it is possible to accurately test the electrical characteristics of the integrated circuit package by measuring the correct timing error of the test system 201 for the integrated circuit package.

Claims (4)

A test system connected to a load board on which an integrated circuit package having an integrated circuit is mounted and testing electrical characteristics of the integrated circuit package mounted on the load board. A driver for generating a test signal for testing the integrated circuit package; A test signal output unit connected to the load board to transfer the test signal to the load board; A response signal input unit coupled to the load board to receive a response signal output from the integrated circuit package; A receiver which receives a signal input through the response signal input unit and compares the signal with the test signal; And And switching means connected between the test signal output unit and the response signal input unit and electrically connecting the test signal output unit and the response signal input unit in response to a control signal. The test system according to claim 1, further comprising a control signal generator for generating the control signal. The test system of claim 2, wherein the control signal generator is driven by a program. A method of measuring timing error of a test signal generated in a test system for testing an integrated circuit package by connecting to a load board on which an integrated circuit package is mounted, Generating a test signal for testing the integrated circuit package; Receiving the test signal immediately before the test signal is output from the test system to the outside; And And comparing the timing of the generated test signal with the received test signal.