KR19990086847A - Synchronous memory device - Google Patents

Abstract

The synchronous memory device disclosed herein includes a memory cell array including memory cells, a sense amplifier configured to sense data of the cells in response to a first pulse signal, and a data sensed by the sense amplifier in response to a second pulse signal. A latch circuit for latching and a data output buffer for receiving the latched data and outputting the latched data, a first pulse generating circuit for generating the first pulse signal in synchronization with the second pulse signal, and a second in synchronization with the external clock signal And a second pulse generation circuit for generating a pulse signal.

Description

A SYNCHRONOUS MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device, and more particularly, to a synchronous memory device capable of preventing read errors by adjusting activation and deactivation timings of pulse signals.

Recently, semiconductor memory devices have been required to operate with large bandwidths. With the same bandwidth, the semiconductor memory device is desired to be operated at a high operating frequency. BACKGROUND OF THE INVENTION A synchronous memory device that operates in synchronization with an external clock signal has been proposed among semiconductor memory devices for satisfying such a demand.

The synchronous DRAM device has a function of CAS latency (hereinafter referred to as CL) indicating the number of clock cycles until a data is fetched after a read command is provided. For example, a value corresponding to a cascade latency of 2 means that data can be taken in a second cycle after a clock cycle provided with a read command. If the value corresponding to the cache latency is 3, it means that the read command may take data in the third clock cycle after the provided clock cycle.

1 illustrates a schematic configuration of a synchronous memory device, and illustrates a path of a data path.

The synchronous memory device includes a memory cell array 100, a column decoder circuit, a first pulse generator circuit 150, a second pulse generator circuit 160, a bit line sense amplifier 110, an input / output gate circuit, an input / output sense amplifier ( 120 and data output buffer 140. Since the memory cell array 100 and the column decoder circuits are well known to those skilled in the art, detailed description thereof will be omitted below.

When the cascade latency is 3, the data developed through the bit line sense amplifier 110 are passed through the input / output gate circuit controlled by the column select signal CSL. Is passed to. The data are sequentially stored in the input and output sense amplifier 120, the first register, the latch circuit 130, the second register, and the data output buffer 140, the third register. And the data are controlled by the same clock. Therefore, it is important to adjust the pulse signals to control the three data so as not to damage each other.

Referring to FIG. 1, the first register is controlled by the first pulse signal FRP generated by the delay of the internal clock signal PCLK synchronized with the external clock signal CLK. The second and third registers are controlled by the second pulse signal CLKDQ, which is synchronized with the external clock signal CLK. The first pulse signal FRP is a signal synchronized with the first clock cycle after a read command is input, and is a signal for latching data provided from the bit line sense amplifier 110 through the data line. The second pulse signal CLKDQ is a signal for latching data provided from the input / output sense amplifier 120 as a signal synchronized with a next cycle after a read command is input.

Pulse signals that control the registers are generated independently of each other. Therefore, the registers have difficulty in responding to process changes and variables such as VDD, which causes the pulse signals to be interrelated with each other, resulting in a read fail. In other words, the first pulse signal FRP and the second pulse signal CLKDQ are output from different pulse generation circuits 150 and 160, and the clock signal having a predetermined width with respect to a high frequency must be simultaneously applied. It becomes difficult to respond to variables.

3 is an operation timing diagram of pulse signals according to a clock signal.

In the first pulse generation circuit, the activation time of the first pulse signal FRP synchronized with the internal clock signal PCLK synchronized with the external clock signal CLK is changed from the original according to the component change of the resistor and capacitor of FIG. 2. It may be accelerated or slowed down. Referring to FIG. 3, when the activation time of the first pulse signal FRP is advanced and overlaps with the second pulse signal CLKDQ, a problem occurs in which data which is already being output is changed to data corresponding to the next clock cycle instead of the current. Done. And despite the change in VDD, the pulse signals do not change, so it is difficult to respond to the variables.

Accordingly, an object of the present invention is to provide a synchronous memory device capable of sequentially taking data according to a cascade latency value.

1 is a block diagram of a synchronous memory device;

2 is a circuit diagram of a pulse generating circuit according to the prior art;

3 is an operation timing diagram of pulse signals according to the prior art;

4 is a circuit diagram of a pulse generating circuit according to the present invention;

5 is an operation timing diagram of pulse signals according to the present invention.

* Explanation of symbols on main parts of the drawings

100: memory cell array 110: bit line sense amplifier

120: input and output sense amplifier 130: latch circuit

150: data output buffer

(Configuration)

According to one aspect of the present invention, a synchronous memory device includes a memory cell array including memory cells arranged in a matrix form of a plurality of columns and rows, the memory cell array in response to a first pulse signal. A sense amplifier for sensing data, a latch circuit for latching data sensed by the sense amplifier in response to a second pulse signal, a data output buffer for accepting and outputting the latched data, and in synchronization with the second pulse signal A first pulse generating circuit for generating the first pulse signal and a second pulse generating circuit for generating a second pulse signal in synchronization with the external clock signal, wherein the first pulse generating circuit includes: When deactivated, it generates a first pulse signal that is activated.

In this embodiment, the synchronous memory device is a synchronous dynamic random access memory (DRAM).

In this embodiment, the first pulse generation circuit receives an external clock signal and an internal clock signal synchronized with the external clock signal to generate a fourth pulse signal, and a delay for delaying the fourth pulse signal. A circuit for transmitting the delayed fourth pulse signal, a control circuit for receiving the second pulse signal and an external clock signal to control the transfer of the fourth pulse signal, and an output circuit for outputting the fourth pulse signal; do.

In this embodiment, the delay circuit increases the pulse width of the fourth pulse signal.

(Action)

With such a device, a read error can be prevented by controlling the activation time of the pulse signal and sequentially outputting data according to the cascade latency value.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIGS. 4 and 5.

Referring to FIG. 4, the novel synchronous memory device of the present invention provides a pulse generating circuit that allows data to be sequentially output. The pulse generation circuit outputs a pulse signal for controlling the next register only after the pulse signal for controlling the register for storing the last data is deactivated.

Referring again to FIG. 1, a synchronous memory device having a cascade latency value of 3 during a read operation may include a register (input / output sense amplifier) 120 for first data and a register (latch circuit) for second data during a read operation. 130 and a register (data output buffer circuit) 140 for the third data. Each of the registers receives data by a first pulse signal FRP and a second pulse signal CLKDQ. For this purpose, the width between the pulse signals must be guaranteed.

4 is a circuit diagram showing the configuration of a first pulse generating circuit according to the present invention.

The internal clock signal PCLK and the pulse signal PWR are generated in synchronization with the external clock signal CLK, and the first pulse signal FRP is generated through the delay of the internal clock signal PCLK. The first pulse generating circuit 150 is generated from an input circuit 150a and an input circuit 150a which receive an external clock signal CLK, an internal clock signal PCLK, and a read pulse signal PWR and combine them. A delay circuit 150b for delaying the pulse signal by a predetermined interval, a control circuit 150d for controlling the output of the pulse signal, a transfer circuit 150c for transmitting the pulse signal in accordance with the control circuit 150d, and the pulse And an output circuit 150e for outputting a signal.

The input circuit 150a includes a NAND gate ND21 to which the external clock signal CLK, the internal clock signal PCLK, and the read pulse signal PWR are input. The delay circuit 150b is connected to the output terminals of the inverters IV22 to IV26 and the last one of the inverters IV22 to IV26 connected in series from the output terminal of the NAND gate ND21. The input stages include a NOR gate NR1 to which each of the input terminals is connected. The control circuit 150d includes an inverter IV28 for inverting the second pulse signal CLKDQ, a NAND gate having one input terminal connected to an output terminal of the inverter IV28, and a type force terminal receiving an external clock signal CLK. ND22). The transfer circuit 150C includes an inverter IV27 and a gate connected to an output terminal of the NAND gate ND22 and a PMOS transistor and an NMOS transistor having gates connected to input and output terminals of the inverter IV27 and the same source and drain connected to each other. It includes a transfer gate (TG21) consisting of. Subsequently, the output circuit 150e includes inverters IV29 and IV30 connected in series with the output terminal of the transfer circuit 150c.

5 is an operation timing diagram of pulse signals according to the present invention.

First, the first pulse signal FRP is generated by the delay of the internal clock signal PCLK synchronized with the external clock signal CLK. The first pulse signal FRP controls the input / output sense amplifier 120 that is the first register of FIG. 1.

Referring to FIG. 4, when an external clock signal CLK, an internal clock signal PCLK, and a read pulse signal PWR are applied to the NAND gate ND21, a pulse signal is output. This is output as a pulse signal having a predetermined width via the inverters IV22 to IV26 of the delay circuit 150b. However, when the second pulse signal CLKDQ of the control circuit 150d transitions from 'H' to 'L', the pulse signal passes through the transfer circuit 150c and the output circuit 150e and the first pulse signal FRP. ) Is output. Accordingly, data is transferred to the first register 120 only after valid data is transmitted to the latch circuit 130 and the data output buffer 140 by the second pulse signal CLKDQ. As a result, the conventional first pulse signal FRP is not adapted to the process change, and the activation time overlaps with the second pulse signal CLKDQ, so that the data to be transmitted to the data output buffer 140 is output as the next data. do.

The second pulse signal CLKDQ prevents the generation of the first pulse signal FRP even when the process change and the VDD change occur and the delay period of the internal clock signal is shortened. Therefore, the overlap of conventional pulse signals prevents the next data from damaging the data currently being output. In this case, the resistance and capacitor components of the delay circuit 150b may be increased so that the first pulse signal FRP has an increased width by the delay period of the internal clock signal PCLK compared to the second pulse signal CLKDQ. do.

As described above, according to the present invention, the widths of the pulse signals do not overlap, and the data are sequentially output.

Claims (4)

A memory cell array having memory cells arranged in a matrix form of a plurality of columns and rows; A sense amplifier for sensing data of the cells in response to a first pulse signal; A latch circuit for latching data sensed by the sense amplifier in response to a second pulse signal; A data output buffer which receives the latched data and outputs the latched data; A first pulse generating circuit generating the first pulse signal in synchronization with the second pulse signal; And A second pulse generation circuit configured to generate a second pulse signal in synchronization with an external clock signal, And the first pulse generation circuit generates a first pulse signal that is activated when the second pulse signal is inactivated. The method of claim 1, The synchronous memory device is a synchronous dynamic random access memory (DRAM). The method of claim 1, The first pulse generating circuit includes an input circuit for receiving the external clock signal and an internal clock signal synchronized with the external clock signal to generate a fourth pulse signal; A delay circuit for delaying the fourth pulse signal; A transfer circuit for delivering the delayed fourth pulse signal; A control circuit for receiving the second pulse signal and an external clock signal to control transmission of a fourth pulse signal; And And an output circuit for outputting the fourth pulse signal. The method of claim 3, wherein And the delay circuit increases the pulse width of the fourth pulse signal.