KR19990086508A - Semiconductor memory device capable of verifying multiple memory bank operations - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of verifying a plurality of memory bank operations. The present invention relates to a control signal generator for generating a control signal by a combination of a plurality of memory banks, a pad, and an address signal input from an external device. And a plurality of bank enable circuits connected to the pad and the control signal generator and configured to select the plurality of memory banks by combining the control signal and the signal input from the pad. Several banks can be selected even in the packaged state.

Description

Semiconductor memory device capable of verifying multiple memory bank operations

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of verifying even when a semiconductor memory device including a plurality of memory banks is packaged.

A conventional semiconductor memory device includes two memory banks or four memory banks, and includes power pins, a plurality of pads, and a plurality of bank enable circuits for controlling the memory banks. A plurality of pad signals are generated from the recovery bank enable circuit. The plurality of pads are not connected to the power pin for the operation of four memory banks. The plurality of pad signals are then disabled to operate the four memory banks. The plurality of pads are connected to the power pins to operate two memory banks. The plurality of pad signals are then enabled to operate the two memory banks. In the wafer state, two memory banks were verified by applying power to the plurality of pads to generate an internal signal to test the wafer. Then, the plurality of pads were packaged by connecting them to a power source. In the conventional case, four memory banks are implicit, and only four memory banks can be analyzed in a packaged state. In order to analyze the two memory banks, the two memory bank packages were separately manufactured and analyzed.

As described above, according to the related art, a package has to be manufactured and verified separately in order to verify a mode that has not yet been verified.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device capable of simultaneously verifying various banks in a package manufactured for one mode.

1 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the plurality of bank enable units shown in FIG. 1. FIG.

3 is a circuit diagram of the mode register set circuit shown in FIG.

4 is a circuit diagram of the mode input / output circuit shown in FIG. 1;

5 is a schematic block diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a DualBC mode input / output circuit shown in FIG. 5.

The present invention to achieve the above technical problem,

A control signal generator for generating a control signal by a combination of a plurality of memory banks, a pad, and an address signal input from the outside, and a signal connected to the pad and the control signal generator and input from the control signal and the pad. And a plurality of bank enable circuits for selecting the plurality of memory banks in combination with each other.

According to the present invention, various banks can be selected even when the semiconductor memory device is packaged.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention. Referring to FIG. 1, a semiconductor memory device according to an exemplary embodiment of the present invention may include a memory bank 151, a power pin 121, a pad 111, a control signal generator 141, and a plurality of bank enable units ( 131.

The memory bank 151 has a plurality of, for example, four memory banks. The memory bank 151 may include four or more memory banks.

The power supply voltage VCC is supplied through the power supply pin 121. The pad 111 generates a plurality of pad signals PDUAL_PAD as a plurality of pads.

The plurality of pads 111 and the power pins 121 are selectively connected through a wire, for example, a gold wire.

The control signal generator 141 inputs the address signal MRAsB from the outside to generate the first control signal PDUAL_MRS. The control signal generator 141 includes a mode register set circuit 161 and a mode input / output circuit 171. The mode register set circuit 161 and the mode input / output circuit 171 will be described in detail with reference to FIGS. 3 and 4, respectively.

The plurality of bank enable units 131 may be connected to the pad 111 and the control signal generator 141. The plurality of bank enable units 131 may be configured by combining the first control signal PDUAL_MRS and the plurality of pad signals PDUAL_PAD or two in the memory bank 151. Select four memory banks.

Table 1 shows selecting the memory bank 151 by a combination of the plurality of pad signals PDUAL_PAD and the first control signal PDUAL_MRS.

Multi-Pad Signal (PDUAL_PAD) First control signal PDUAL_MRS Multi-bank enable signal (PDUAL) 0 One One 0 0 0 One One One One 0 0

In Table 1, when the plurality of pad signals PDUAL_PAD is '0', the plurality of pads 111 and the power pin 121 are disconnected, and when the plurality of pad signals PDUAL_PAD is '1', the plurality of pads 111 and the power pin are '1'. 121 is connected. When the first control signal PDUAL_MRS is '0', it indicates a disable state. When the first control signal PDUAL_MRS is '1', it indicates an enable state. Four memory banks are selected when the multi-bank enable signal PDUAL is '0', and two memory banks are selected when the multi-bank enable signal PDUAL is '1'.

As described above, two memory banks or four memory banks may be selected and verified by the address signal MRAsB regardless of the connection state of the plurality of pads 111 and the power pin 121. That is, even if the semiconductor memory device is set to 2 bank mode and packaged, the 4 bank mode can be verified, and even if the semiconductor memory device is set to 4 bank mode and packaged, the 2 bank mode can be verified.

FIG. 2 is a circuit diagram of the plurality of bank enable units 131 shown in FIG. Referring to FIG. 2, the plurality of bank enable units 131 may include NMOS transistors 211 and 212, PMOS transistors 221 to 228, buffers 231 and 232, and an exclusive OR gate 241.

The NMOS transistor 211 serves as a diode in which a gate and a source are commonly connected to the ground terminal GND, and a plurality of pad signals PDUAL_PAD are applied to a drain. Since the power supply voltage VCC is applied to the gate, the NMOS transistor 212 is always turned on and a plurality of pad signals PDUAL_PAD are applied to the drain to transmit the plurality of pad signals PDUAL_PAD to the buffer 231. It is a transfer transistor. The PMOS transistors 221 to 228 are connected in series between the power supply voltage VCC and the node C, and the gates of the PMOS transistors 221 to 228 are all grounded to the ground terminal GND and are always turned on. maintain. The node C is maintained at the ground terminal GND level when the plurality of pad signals PDUAL_PAD are not input. The plural pad signal PDUAL_PAD is input so that the plural pad signal PDUAL_PAD is at a low level when the plural pad signal PDUAL_PAD is at a logic low level, and is maintained at a high level when the plural pad signal PDUAL_PAD is at a logic high level.

The buffers 231 and 232 respectively buffer the signal applied to the node C and the output of the exclusive OR gate 241. A plurality of bank enable signals PDUAL are generated from the buffer 232.

The exclusive OR gate 241 performs an exclusive OR on the signal applied to the node C and the first control signal PDUAL_MRS. The exclusive OR gate 241 includes NAND gates 251 to 254 and an inverter 257.

3 is a circuit diagram of the mode register set circuit 161 shown in FIG. Referring to FIG. 3, the mode register set circuit 161 includes negative AND gates 311 to 314, negative AND gates 321 to 326, and inverters 331 to 333. The mode register set circuit 161 inputs the address signals MRAiB, MRAjB, MRAkB, MRAmB, and MRAnB, the second control signal PWMC, and the power detection signal PVCCH to receive the third to sixth control signals MRSET. Occurs.

When the second control signal PWCBR is logic low, the negative AND gates 322 to 325 are reset, thereby causing the third to fifth control signals TMSET, MRSTEST, and DUALTEST to be logic low. The power detection signal PVCCH goes to a logic low when the power supply voltage VCC is lower than a predetermined level, and goes to a logic high when the power supply voltage VCC is higher than a predetermined level. Therefore, when the power supply voltage VCC is lower than the predetermined level, the power supply detection signal PVCCH is at a logic low, and thus the sixth control signal MRSET is at a logic low at this time. When the second control signal PWMC is logic low while the power detection signal PVCCH is logic high, the sixth control signal MRSET is logic low.

When the second control signal PWCBR is logic high, the third to sixth control signals TMSET, MRSTEST, DUALTEST, and MRSET are controlled by a combination of the address signals MRAiB, MRAjB, MRAkB, MRAmB, and MRAnB.

The address signals MRAiB and MRAjB are applied to the negative OR gate 311 and the output of the negative OR gate 311 is the negative AND gate 322 together with the output of the inverter 333 and the second control signal PWMB. Is applied to. The output of the negative AND gate 322 is generated as a third control signal TMSET through the inverter 334. The output of the address signal MRAiB and the inverter 332 is applied to the negative AND gate 312, and the output of the negative OR gate 312 is negative and logical together with the output of the inverter 333 and the second control signal PWCBR. Is applied to the gate 323. The output of the negative AND gate 323 is generated as the fourth control signal MRSTEST through the inverter 335. The output of the address signal MRAjB and the inverter 331 are applied to the negative AND gate 313, and the output of the negative AND gate 313 is negative AND together with the output of the inverter 333 and the second control signal PWCBR. Is applied to the gate 324. The output of the negative AND gate 324 is generated as the fifth control signal DUALTEST through the inverter 336. The outputs of the inverters 331 and 332 are applied to the negative AND gate 314 and the output of the negative AND gate 314 is together with the output of the negative AND gate 321 and the second control signal PWCBR. 325 is applied. The output of the negative AND gate 325 is applied to the negative AND gate 326 together with the power detection signal PVCCH and the negative AND gate 326 generates a sixth control signal MRSET. The address signals MRAkB, MRAm, and BMRAnB are applied to the negative AND gate 321.

4 is a circuit diagram of the mode input / output circuit 171 shown in FIG. Referring to FIG. 3, the mode input / output circuit 171 includes transmission gates 311 to 314, latches 321 to 324, buffers 331, 332 and 333, power supplies 341 and 342, and inverters 351 and 352. ). The mode input / output circuit 171 inputs an address signal MRAsB, a mode enable signal PMRSPD, a power detection signal PVCCH, and third to sixth control signals TMSET, MRSTEST, DUALTEST, and MRSET. The first control signal PDUAL_MRS, the seventh control signal P4K, and the eighth control signal PBTX8 are generated.

The mode input / output circuit 171 latches the address signal MRAsB to the latch 321 through the transmission gate 311 when the mode enable signal PMRSPD is enabled as logic high. In this state, when the fourth control signal MRSTEST becomes logic high, the address signal MRAsB is applied to the buffer 332 through the inverter 352, the transfer gate 313, and the latch 323, and the buffer 332. From the eighth control signal PBTX8. When the fifth control signal DUALTEST is logic high, the address signal MRAsB is applied to the buffer 333 through the inverter 352, the transfer gate 314, and the latch 324, and from the buffer 333. The first control signal PDUAL_MRS is generated. In addition, when the third control signal TMSET becomes logic high, the address signal MRAsB is applied to the buffer 331 through the inverter 352, the transfer gate 312, and the latch 322, and from the buffer 331. The seventh control signal P4K is generated.

The sixth control signal MRSET is applied to the power supply unit 341 through the inverter 351. If the sixth control signal MRSET is logic high, the power supply 341 is activated to supply the power supply voltage VCC to the latches 322 and 323, and is deactivated if the sixth control signal MRSET is logic low. The power supply unit 342 is activated when the power detection signal PVCCH is at a low level to apply a power supply voltage to the latch 321, and is deactivated when the power detection signal PVCCH is at a high level.

5 is a schematic block diagram of a semiconductor memory device according to a second embodiment of the present invention. Referring to FIG. 5, a semiconductor memory device according to a second embodiment of the present invention may include a memory bank 515, a power pin 521, a dual BC pad 511, a dual BC mode input / output circuit 541, and a semiconductor memory device. The dual BC bank enable unit 531 is provided.

The memory bank 515 and the power supply pin 521 are the same as those shown in FIG. 1 and will be omitted.

The dual BC pad 511 generates the dual BC pad signal PDUALBC_PAD.

The dual BC mode input / output circuit 541 receives the address signal MRAtB to generate the first control signal PDUALBC_MRS. The dual BC mode input / output circuit 541 will be described in detail with reference to FIG. 6.

The dual BC bank enable unit 531 includes an input unit 551, a logic unit 561, and an output unit 571.

The input unit 551 includes inverters 533 and 534, a negative logic gate 535, NMOS transistors 581 to 586, and PMOS transistors 591 to 597. The dual BC pad signal PDUALBC_PAD is applied to the PMOS transistor 591, and the NMOS transistors 581 to 584 and the PMOS transistors 592 to 597 are connected in series to the PMOS transistor 591. NMOS transistors 585 and 586 are connected in parallel to the PMOS transistors 592 to 597. The gates of the PMOS transistors 591 and the gates of the PMOS transistors 592 to 597 are grounded and always turned on, and the gates of the NMOS transistors 581 to 584 are also connected to the power supply voltage VCC and are always turned on. . Gates of the NMOS transistors 585 and 586 are commonly connected to the output terminal of the inverter 533. The inverter 533 is connected to the inverter 534 and the output of the inverter 534 is applied to the logic unit 561 along with the second control signal P4K.

The logic unit 561 is composed of an exclusive OR gate. The logic unit 561 inputs the output of the negative AND gate 535 and the first control signal PDUALBC_MRS. An output of the logic unit 561 is applied to the buffer 571 and the buffer 571 generates a dual BC bank enable signal PDUALBC.

The dual BC bank enable unit 531 inputs the dual BC pad signal PDUALBC_PAD and the first control signal PDUALBC_MRS and generates the dual BC bank signal PDUALBC to generate two memory banks, for example, two memory banks in the memory bank 515. Select a memory bank or four memory banks.

Table 2 shows selecting the memory bank 515 by the combination of the dual BC pad signal PDUALBC_PAD and the first control signal PDUALBC_MRS.

Dual BC Pad Signal (PDUALBC_PAD) First control signal PDUALBC_MRS Dual BC Bank Enable Signal (PDUALBC) 0 0 0 0 One One One 0 0 One One One

In Table 2, when the dual BC pad signal PDUAL_PAD is '0', the dual BC pad 511 and the power pin 521 are disconnected, and when the dual BC pad signal PDUAL_PAD is '1', the dual BC pad 511 is used. ) And the power pin 521 are connected. When the first control signal PDUAL_MRS is '0', it indicates a disable state. When the first control signal PDUAL_MRS is '1', it indicates an enable state. If the dual BC bank enable signal PDUAL is '0', two memory banks are selected. If the dual BC bank enable signal PDUAL is '1', four memory banks are selected.

As described above, regardless of the connection state between the dual BC pad 511 and the power supply pin 521, two memory banks or four memory banks may be selected and verified by the address signal MRAtB. That is, even if the semiconductor memory device is set to 2 bank mode and packaged, the 4 bank mode can be verified, and even if the semiconductor memory device is set to 4 bank mode and packaged, the 2 bank mode can be verified.

FIG. 6 is a circuit diagram of the dual BC mode input / output circuit 541 shown in FIG. 4. Referring to FIG. 6, the dual BC mode input / output circuit 541 may include transmission gates 611 to 613, latches 621 to 623, buffers 631 and 632, power supplies 641 and 642, and inverters 651 and 652. It is provided. The dual BC mode input / output circuit 541 inputs an address signal MRAtB, a mode enable signal PMRSPD, a power detection signal PVCCH, and third to fifth control signals MRSET, MRSTEST, and DUALTEST. The first control signal PDUALBC_MRS and the sixth control signal PSECON are generated.

The dual BC mode input / output circuit 541 latches the address signal MRAtB to the latch 621 through the transmission gate 611 when the mode enable signal PMRSPD is enabled as logic high. In this state, when the fourth control signal MRSTEST becomes logic high, the address signal MRAtB is applied to the buffer 632 through the inverter 652, the transfer gate 613, and the latch 623, and the buffer 632. The sixth control signal PSECON is generated. When the fifth control signal DUALTEST is logic high, the address signal MRAtB is applied to the buffer 631 through the inverter 652, the transfer gate 612, and the latch 622, and from the buffer 631. The first control signal PDUALBC_MRS is generated. The third control signal MRSET is applied to the power supply 642 through the inverter 651. That is, when the output of the inverter 651 is logic low, the power supply 642 is activated to supply the power supply voltage VCC to the input terminals of the latches 622 and 623. If the output of the inverter 651 is logic high, then the power supply 642 is deactivated. The power detection signal PVCCH is applied to the power supply unit 641. If the power detection signal PVCCH is logic low, the power supply unit 641 is activated to apply the power supply voltage VCC to the input terminal of the latch 621. If the power detection signal PVCCH is logic high, the power supply unit 641 is deactivated.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, various banks, for example, two memory banks or four memory banks, may be selected even when the semiconductor memory device is packaged.

Claims (1)

A plurality of memory banks; pad; A control signal generator which generates a control signal by a combination of address signals input from the outside; And And a plurality of bank enable circuits connected to the pad and the control signal generator and configured to select the plurality of memory banks by combining the control signal and the signal input from the pad.