KR19990084738A - Triac element - Google Patents

Abstract

The triac element of the present invention is configured so that the gate region and the cathode of one side thyristor do not overlap with each other as much as possible within the cathode area to obtain the on-state current characteristics. When the negative bias is applied to the second electrode under the state, the on-state voltage characteristic can be improved by removing the transverse voltage drop component.

Description

Triac element

FIELD OF THE INVENTION The present invention relates to bidirectional switching devices, and more particularly to triac devices.

The triac device is a bidirectional device in which PNPN thyristors are connected in parallel with each other, and the operation mode is different depending on the applied voltage, and the triac device should be designed and manufactured to have uniform characteristics in each operation mode.

In particular, the on-state voltage (V _TM ) characteristic determines the power efficiency of the system in which the triac device is used, and thus reduces the on-state voltage characteristic as much as possible, and similar in both directions depending on the bias state of both electrodes. It should be designed to have on-state voltage characteristics, and for this purpose, the cathode and anode of anti-parallel parallel thyristor should be designed to be equally symmetric in plane.

However, in the case of a conventional corner gate type triac device, as illustrated in FIGS. 1A and 1B, the upper and lower sides of the first semiconductor layer 1, which is, for example, an n-type substrate as the first conductivity type, are illustrated. P-type second and third semiconductor layers 3 and 4 of the second conductivity type formed on both surfaces, a device isolation region 2 of the second conductivity type, and a predetermined distance from each other in the second semiconductor layer 3 The fourth and fifth semiconductor layers 5 and 6 of the first conductivity type formed to be spaced apart, the sixth semiconductor layer 7 formed in the third semiconductor layer, the second semiconductor layer 3 and the fifth Each of the first electrodes 10 formed in one-to-one contact with the semiconductor layer 6, the gate electrodes 9 formed in contact with both the third semiconductor layer 5 and the second semiconductor layer 3, and The second electrode 11 is formed to be in contact with the third semiconductor layer 4 including the sixth semiconductor layer 7, and is positive to the second electrode 11 in an on state operation. Bye When the current is applied, the current flow is efficient because the cathode sixth semiconductor layer 7 and the anode second semiconductor layer 3 are formed symmetrically in plan view, while negative (−) is applied to the second electrode 11. When a bias is applied, the fifth semiconductor layer 6, which is a cathode, and the third semiconductor layer 4, which is an anode are formed asymmetrically, and as shown in FIG. There is a problem that the power consumption is increased by the increase in the voltage drop value.

Accordingly, an object of the present invention is to provide a triac device capable of minimizing a voltage drop by planarly symmetrical both the cathode and the anode of both thyristors in order to solve the problems of the prior art as described above.

In order to achieve the above object, a triac device of the present invention includes a first semiconductor layer of a first conductivity type and a second and third semiconductor layer of a second conductivity type formed on both upper and lower surfaces of the first semiconductor layer. And fourth and fifth semiconductor layers of a first conductivity type formed in the second semiconductor layer to be spaced apart from each other by a predetermined distance, a sixth semiconductor layer of a first conductivity type formed in the third semiconductor layer, and the fifth semiconductor layer. A gate electrode formed to contact the partial region of the layer and the second semiconductor layer, a first electrode formed to contact the second semiconductor layer and the fifth semiconductor layer, and a third semiconductor layer including the sixth semiconductor layer; In a triac device having a second electrode formed to be in contact with each other, the sixth semiconductor layer is opposite to the fourth and fifth semiconductor layers facing the partial region of the second semiconductor layer and centered on the same vertical line. Configured to be located at It is characterized by.

Figure 1a shows a planar structure of a triac device according to the prior art,

FIG. 1B illustrates a vertical cross-sectional structure of the triac device of FIG. 1A;

FIG. 1C illustrates the flow of current within the triac device of FIG. 1A, and FIG.

Figure 2a shows a planar structure of a triac device according to the present invention,

FIG. 2B illustrates a vertical cross-sectional structure of the triac device of FIG. 2A.

* Description of the symbols for the main parts of the drawings *

21: first semiconductor layer 22: device isolation region

23: second semiconductor layer 24: third semiconductor layer

25: fourth semiconductor layer 26: fifth semiconductor layer

27: sixth semiconductor layer 28: seventh semiconductor layer

29 gate electrode 30 first electrode

31: second electrode

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The triac device of the present invention is a corner gate type, and is formed in the gate region and on the left side of the drawing as much as possible in the cathode area range to obtain the on-state current characteristics as shown in FIGS. 2A and 2B. The sixth semiconductor layer 27, which is a cathode of the first thyristor, is not overlapped with each other. The structure thereof is as follows.

The triac device of the present invention is a device isolation region formed by locally diffusing a p-type impurity of a second conductivity type on both the upper and lower surfaces of an n-type first semiconductor layer 21 of a first conductivity type for a long time. 22), a second semiconductor layer 23 formed by diffusing a second conductivity type impurity in the upper portion of the first semiconductor layer 21, and a second conductivity type impurity in the lower portion of the first semiconductor layer 21. Third and fourth semiconductor layers 25 and 26 formed by diffusion and locally diffused impurities of the first conductivity type in the second semiconductor layer 23 so as to be spaced apart from each other by a predetermined interval. And a first conductivity in the third semiconductor layer 24 so as not to overlap on the same vertical line as the fourth and fifth semiconductor layers 25 and 26 and to be located on the left side opposite to the fourth semiconductor layer 25 in the drawing. The sixth semiconductor layer 27 formed by diffusing the impurities of the type, the second semiconductor layer 23 and the phosphorus A gate electrode 29 formed in contact with a portion of the fifth semiconductor layer 26 in contact with each other, and a first electrode 30 formed in one-to-one contact with the second semiconductor layer 23 and the fifth semiconductor layer 26, respectively. ), And a second electrode 31 formed to contact the third semiconductor layer 24 including the sixth semiconductor layer 27, and reference numeral 28 not to contact the gate electrode 29. A seventh semiconductor layer for dividing a part of the second semiconductor layer 23 as a p-type gate region.

In the structure of the present invention, since the anode and the cathode of the first thyristor positioned on the left side and the second thyristor positioned on the right side are symmetrically planarized, a negative bias is applied to the second electrode when operating in the on state. Also, the lateral voltage drop due to the conventional carrier injection can be reduced.

As described above, according to the present invention, even when a negative bias is applied to the second electrode under the on-state without decreasing other characteristics, the on-state voltage characteristic can be improved by removing the voltage drop component in the lateral direction.

Claims (2)

A first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type formed on both upper and lower surfaces of the first semiconductor layer, and a first conductivity formed to be spaced apart from each other within the second semiconductor layer The fourth and fifth semiconductor layers of the mold type, the sixth semiconductor layer of the first conductivity type formed in the third semiconductor layer, the gate electrode formed to be in contact with a partial region of the fifth semiconductor layer and the second semiconductor layer, In a triac device comprising a first electrode formed to contact the second semiconductor layer and the fifth semiconductor layer, respectively, and a second electrode formed to contact the third semiconductor layer including the sixth semiconductor layer. , And the sixth semiconductor layer is disposed to face the partial region of the second semiconductor layer and to be opposite to the fourth and fifth semiconductor layers about the same vertical line. The triac device according to claim 1, wherein the gate electrode is a corner type.