KR19990083536A - Atm communications control apparatus using an atm controller - Google Patents

Abstract

Provided is an ATM controller and an ATM communication controller that can achieve high quality data communication.

This controller includes transmission means for transmitting packet data between the terminal and the buffer memory, transmission control means for dividing the packet at the terminal into data cells and transmitting the packet data to the ATM network side, and received at the ATM network side. Reception control means for generating a packet from the data cell and storing it in a buffer memory or a memory in the terminal, means for selecting either a buffer memory or a memory in the terminal as a storage location of packet data according to the nature of the traffic; Only a cell other than the received data cell has a microprocessor which performs the analysis of the cell and the processing according to the analysis result.

Description

ATM communication controller using ATM controller {ATM COMMUNICATIONS CONTROL APPARATUS USING AN ATM CONTROLLER}

The present invention relates to an ATM communication control apparatus that executes processing of a lower part of an ATM protocol between a terminal and an Asynchronous Transfer Mode (ATM) network. The present invention also relates to an ATM controller that shares the processing of the type processing apparatus communication control apparatus even within the ATM communication control apparatus.

In an ATM network, communication according to an ATM controller is performed between an ATM communication controller and a plurality of terminals connected via a line. The ATM communication controller shares the processing of the lower part of the ATM controller. The ATM communication controller divides a variable length packet generated at a terminal into cells of fixed length. Thereafter, the ATM communication control apparatus transmits the divided cell on the line. On the other hand, the ATM communication controller generates a packet in the cell received on the circuit, and then passes the generated packet to the terminal.

Conventional ATM controllers include an ATM controller of the type which performs divisional assembly of cells on a buffer memory in a communication control device, and an ATM controller of the type that performs divisional assembly of cells on a main memory of a calculator main body.

The former ATM controller has a problem that the transmission delay time until the data is transmitted from the calculator to the network is long. Since the latter ATM controller does not have a buffer memory in the communication control device, there is a problem that the reception cell is likely to be discarded due to the load on the system bus of the calculator.

The invention which solves the problem of the said conventional ATM controller is described in Unexamined-Japanese-Patent No. 9-205439.

In the invention described in the above publication, packet data is stored in the main memory in the terminal with respect to low-delay request traffic. In addition, the packet data is stored in the buffer memory for traffic having a small influence of the transmission delay.

In the above conventional technique, delay variation due to load variation of the system bus in the terminal is not considered. Therefore, we want to avoid the effects of delay fluctuations as much as possible. In other words, there is room for improvement in how to transmit a cell with a small delay variation for traffic pursuing real time.

This invention is made | formed in view of the said subject. An object of the present invention is to provide an ATM controller, an ATM communication control device, and an ATM communication control device and a terminal capable of achieving higher quality data communication.

In order to achieve the above object, the present invention makes it possible to select a storage location of packet data in accordance with the presence or absence of a low delay variation request defined by an ATM service category, an ATM adaptation layer (AAL) type, or the like.

1 is a block diagram showing the configuration of an ATM communication control apparatus and a terminal, showing a first embodiment of the present invention.

2 is a diagram showing the configuration of a network system to which the ATM communication control apparatus of the present invention is applied.

3 is a diagram illustrating a layer of a communication protocol layer.

4 is a diagram illustrating a format of a frame AAL1 flowing through a network.

4 is a diagram illustrating a format of a frame AAL3 / 4 flowing through a network.

6 is a diagram illustrating the format of a frame AAL5 flowing through a network.

7 is a diagram illustrating a configuration of an ATM cell.

8 is a diagram illustrating a communication sequence of an ATM protocol.

9 is a diagram illustrating a relationship between service category contents and an AAL type.

10 is a diagram summarizing the features of the ATM service category of the ATM Forum Rules.

Fig. 11 is a diagram showing the presence or absence of a low delay change request in each ATM service category and AAL type in the first embodiment of the present invention.

12 is a configuration diagram of a table defined in the buffer memory in the first embodiment of the present invention.

13 is a block diagram showing the structure of a cell transmission / reception control unit in the first embodiment of the present invention.

Fig. 14 is a block diagram showing the structure of a SAR / DMAC in the first embodiment of the present invention.

Fig. 15 is a flow chart showing the transmission processing flow of the ATM communication control apparatus in the first embodiment of the present invention.

Fig. 16 is a flow chart showing a transmission processing flow of the ATM communication control apparatus in the first embodiment of the present invention.

Fig. 17 is a flow chart showing the buffer selection processing flow of the MPU in the first embodiment of the present invention.

Fig. 18 is a flow chart showing the reception processing flow of the ATM communication control apparatus in the first embodiment of the present invention.

Fig. 19 is a flow chart showing the reception processing flow of the ATM communication control apparatus in the first embodiment of the present invention.

20 is a time chart showing the operation of the ATM communication control device in the second embodiment of the present invention.

Fig. 21 is a flow chart showing another transmission flow of the ATM communication control device in the second embodiment of the present invention.

Fig. 22 is a flow chart showing another transmission flow of the ATM communication control apparatus in the second embodiment of the present invention.

Fig. 23 is a flow chart showing another reception flow of the ATM communication control apparatus in the second embodiment of the present invention.

Fig. 24 is a flow chart showing another reception flow of the ATM communication control device in the second embodiment of the present invention.

Fig. 25 is a flow chart showing another transmission flow of the ATM communication control apparatus in the third embodiment of the present invention.

Fig. 26 is a flow chart showing another transmission flow of the ATM communication control apparatus in the third embodiment of the present invention.

Fig. 27 is a flow chart showing another reception flow of the ATM communication control apparatus in the third embodiment of the present invention.

Fig. 28 is a flow chart showing another reception flow of the ATM communication control apparatus in the third embodiment of the present invention.

Fig. 29 is a block diagram showing another configuration of the ATM communication control apparatus in the fourth embodiment of the present invention.

Specifically, the present invention has the following configuration.

An ATM controller according to one aspect of the present invention performs processing of an ATM layer and an AAL layer of an ATM controller between a transmission path and a terminal. This ATM controller is connected to (1) an external buffer memory to transfer packet data between the terminal and the buffer memory, and (2) divides the packet data stored in the buffer memory or memory into data cells. Cell transmission control means for transmitting the divided data cells to the ATM network side, and (3) a cell type for judging whether or not the corresponding cell is a data cell by examining a header portion of the cell received at the ATM network side. Determination means, (4) cell reception control means for assembling data cells to generate packet data, and storing the generated packet data in the buffer memory or memory; and (5) the nature of traffic in the ATM connection to be established. Accordingly, the cell transmission control means stores the packet data divided into cells and the packet data generated by the cell reception control means. Selecting means for selecting any one of the Mori is provided.

Preferably, the ATM controller is connected to a program memory that stores and maintains a control program, and performs analysis of cells other than data cells identified by the cell type determination and processing according to the result of the analysis in accordance with the control program. It is connected to a running microprocessor.

An ATM communication control apparatus according to one aspect of the present invention executes processing of an ATM layer, an AAL layer, and a PHY layer of an ATM protocol between a transmission path and a terminal. The ATM communication control apparatus drives an ATM controller, a buffer memory connected to the ATM controller, a PHY controller that executes processing of the PHY layer between the ATM controller and the transmission path, and drives the PHY controller. Has a crystal oscillator.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

(Example 1)

2 shows a configuration of a communication network system to which the ATM communication control apparatus according to the present embodiment is applied. In Fig. 2, terminals 1 (1A to 1D) such as a calculator are connected to an ATM switch 3 via an ATM communication control device 2 (2A to 2D) and a transmission path 7. Fig. 3 shows the layer structure of the ATM communication protocol and the sharing of functions between the terminal 1 and the ATM communication control device 2. As shown in Figs. As shown in Fig. 3, the lower layers below the AAL layer for dividing and assembling cells are shared by the ATM communication control apparatus 2. As shown in Figs. The upper layer or more of the LLC layer including the signal processing for establishing the ATM connection is shared by the terminal 1.

1 schematically shows an example of the configuration of the ATM communication control apparatus 2.

See FIG. 1. As a configuration related to communication, the terminal 1 includes a main processor 4, a main memory 5, and a system bus 6 for connecting them. The ATM communication control device 2 is connected to the system bus 6. This ATM communication control device 2 includes an ATM controller 8 which performs cell division and assembly processing, and a PHY controller 9 which performs transmission control to the transmission path 7. In addition, the ATM communication control apparatus 2 includes a microprocessor (hereinafter referred to as MPU) 100, a ROM 20 that stores a control program of the MPU 100, a RAM 30 that is a work memory of the MPU 100, A buffer memory 40 for storing a cell to be transmitted / received and a partition assembly management table for maintaining information necessary for partitioning and assembling the cell, a crystal oscillator 10 for driving the PHY controller 9, and the ATM controller 8, A local bus 230 is connected to the MPU, the ROM, and the RAM.

The ATM controller 8 transfers packets between the bus interface circuit 90 for connecting to the system bus 6 of the terminal 1 and the memory 5 and the buffer memory 40. A SAR / DMAC 60 that performs division and assembly of cells on a HOST / DMAC 50, a main memory 5, or a buffer memory 40 to execute, and a cell transmission / reception control unit 70 that performs generation and analysis of cells. ). The ATM controller 8 further includes an arbiter 110 for adjusting access to the HOST / DMAC 50, the SAR-DMAC 60, and the MPU 100 to the buffer memory 40, and the main processor ( 4) and the main memory 5 through the shared memory 80 for exchanging control information between the MPU 100, the internal bus 200 for connecting the respective parts in the controller, and the bus interface circuit 90. Data transmission buses 210 and 220 are provided for directly exchanging transmission / reception cells. In addition, the ATM controller 8 incorporates a crystal oscillator (not show). Each part in the controller operates according to the block of this oscillator.

When the MPU 100 receives a transmission request from the terminal 1 and the received transmission request requires a low delay variation, the divisional assembly management in the buffer memory 40 as a storage location of the transmission data is performed. The buffer memory 40 is registered in the table, and the main memory 5 is registered when the transmission request does not require low delay variation. In addition, the MPU 100 activates the SAR / DMAC 60. The SAR / DMAC 60 transmits a cell from the main memory 5 or the buffer memory 40 to the transfer path 7 in accordance with the information of the divided assembly management table in the buffer memory 40.

In addition, when the connection is required for the delayed delay at the time of reception cell transmission at the time of connection establishment at the start of communication, the MPU 100 serves as a transfer place of the reception data in the divided assembly management table in the buffer memory 40. The buffer memory 40 is registered, and in the case of a connection that does not require low delay variation, the main memory 5 is registered. When the cell is received by the PHY controller 9, the SAR / DMAC 60 transfers the receiving cell to the main memory or the buffer memory 40 in accordance with the contents of the divided assembly management table.

4, 4, and 6 are diagrams showing the format prescribed by ITU-T Recommendation (THE-ECOMMUNICATION STANDARDIZATION SECTOR OF INTERNATIONAL TELRCOMMUNICATION UNION) I.363 of the ATM cell transmitted in the transmission path 7. In addition, the meanings of the terms in the drawings are explained in detail in Recommendation ITU-T I.363. 4 to 6, the terminal 1 generates the LLC frame 52 by adding the higher protocol header 52-1 obtained by the layer processing of the LLC layer or more to the variable-length data 51 to be transmitted. .

In the case of the AAL type 1 (FIG. 4), the ATM communication controller 2 pays the LLC frame 52 for 47 bytes of data (hereinafter referred to as SAR (AAL1) payload). ) Into 53). The ATM communication control apparatus 2 further adds a SAR (AAL1) header 53-1 to each of the divided SAR (AAL1) payloads 53-2, and the SAR-PDU (AAL1) 53 is added. Create

In addition, in the case of the AAL type (3/4) (FIG. 4), the CPCS (AAL 3/4) header 54-1 and the CPCS (AAL 3/4) trailer 54-2 in the LLC frame 52 described above. ) Adds a CPCS-PDU (AAL 3/4) 55. The CPCS-PDU (AAL 3/4) 54 described above is divided into data every 44 bytes (hereinafter referred to as SAR (AAL3 / 4) payload) 55-3. By adding a SAR (AAL3 / 4) header 55-1 and a (55-2) SAR (AAL3 / 4) trailer to each of the divided SAR (AAL3 / 4) payloads 55-3. A SAR-PDU (AAL3 / 4) 55 is generated.

In addition, in the case of the AAL type 5 (FIG. 6), the CPCS-PDU (AAL5) 56 is generated by adding the CPCS (AAL5) trailer 56-1 to the LLC frame 52 described above. .

In the ATM layer processing, the SAR-PDU (AAL1) 53 or the SAR-PDU (AAL3 / 4) 55 or the CPCS-PDU (AAL5) 56 records data every 48 bytes (hereinafter referred to as payload). 57-2). The cell 57 is generated by adding the cell header 57-1 to each of the divided payloads 57-2. The generated cell is sent out on the transmission path 7 after the PHY layer is processed. On the other hand, the received cell is assembled to the LLC frame in the reverse order. Here, the cell header 57-1 includes a GFC field 57-1A used for flow control, a VPI field 57-1B, an identifier of an ATM connection, a VCI field 57-1C, and a cell. Error detection information for the PT field 57-1D indicating the type (including the specification of the last cell of the packet), the CLP field 57-1E indicating the cell discard priority, and the cell header 57-1. HEC field 57-1F.

FIG. 7 is a diagram showing a payload format of a cell defined in an ATM forum for each cell type.

In Fig. 7, the cell is a data cell 57 carrying user data, an OAM cell 58 used for maintenance / operation of the network, and an RM cell 59 used for transmission rate control of the data cell. Are classified. These types are identified by the PT field 57-1D in the cell header 57-1. In addition, the meaning of the symbol in the figure is described in detail in the ATM Forum Traffic Management Specification.

8 shows an example of a cell transmission and reception sequence in the ATM communication control apparatus. The terminal 1A first establishes a connection of ATM (hereinafter referred to as VC) between the terminal 1B as the communication partner. VC setting and release are performed by the signaling process of the terminal 1A. The packet transmitted from the terminal 1A is divided into cells in the ATM communication control device 2A and sent to the transmission path 7. ATM communication control device on the receiving side For example, in 2B, the receiving cell is assembled into a packet and transmitted to the terminal 1B. In addition to the data cell transmission, the ATM communication control device 2A exchanges a management cell such as an OAM cell or an RM cell with another ATM communication control device or an ATM switch. After the transmission of the cell is finished, the VC is released to terminate the communication.

Fig. 9 shows the relationship between the service category contents A, B, C and D of the ITU-T rule and each AAL type.

In FIG. 9, the AAL type 1 is a protocol for transmitting constant bit rate (CBR) data such as conventional 64 kbps voice or a conventional leased line service. For this reason, the AAL type 1 has a function of continuously sending accurate data while suppressing a change in speed, that is, a "delay change" as much as possible.

In addition, the AAL type 2 is a protocol for providing a service with real-time at a variable speed.

The AAL type (3/4) applies to data traffic that is not sensitive to delay.

The AAL type 5 is for providing connection type data or signal messages more efficiently than the AAL 3.

10 is a collection of features of the ATM traffic service category of the ATM Forum Rules.

In FIG. 10, CBR is a service for transmitting fixed bit rate traffic having a fixed timing relationship between data and samples, and is strict with respect to delays and delay variations, such as voice, video, and circuit emulation. It is a service that supports applications that require real time.

The rt-VBR is a service for transmitting a variable bit rate traffic having a fixed timing relationship between samples. The rt-VBR is a service for supporting an application that requires strict and real-time for delay and delay variation, such as CBR.

nrt-VBR, like rt-VBR, is a service for applications that have variable bit rate traffic but do not have real-time capability. Both rt-VBR and nrt-VBR specify Sustainable Cell Rate (SCR) and Maximum Burst Size (MBR), and use ATM's unique statistical multiple effects.

UBR is a best effort type service for applications that do not have real-time capability, and there is no guarantee about cell loss, delay, or delay variation.

ABR has no real time and also does not require a fixed band. However, the ABR's target is traffic that tries to avoid data loss as much as possible. ABR is a service applied to applications that require more reliability than UBR. Moreover, it is a service which has a function of notifying a user about available transmission band (speed) using EFCI (Explicit Forward Congestion Indication) or RM cell.

Fig. 11 shows each ATM service category, and whether there is a low delay change request during data transmission in the AAL type.

ATM traffic services requiring low latency are CBR and rt-VBR that require real-time. In the AAL type frame, AAL (1) and AAL (2).

Services that do not specifically require low latency variation are nrt-VBR, UBR, and ABR, which do not require real time in the ATM service category. In the AAL type, AAL (3/4) and AAL (5) which do not require real time.

FIG. 12 shows the configuration of tables and buffers defined in the buffer memory 40 in the communication control device 2 and the main memory 5 in the terminal 1, and their correspondences.

In Fig. 12, the buffer memory 40 includes a partition management table 45 which holds management information used by the SAR and DMAC 60 in the cell division (transmission) processing, and the SAR / DMAC 60 assembles the cell. An assembly management table 47 for holding management information used for (reception) processing, a transmission buffer 46 for storing packets to be transmitted, a reception buffer 48 for storing assembled packets, and reception for management cells A buffer 49A and a management cell transmission buffer 49B are set. Their tables and buffers are installed per VC.

The division management table 45 includes a transmission buffer pointer 45-1 for holding an address in the transmission buffer 46 or 46α of the payload 57-2 to be transmitted next, and a transmission data length 45-2. ), The transmission CRC calculation result 45-3 holding the CRC calculation result updated for each cell transmission, and the template of the cell header 57-1 added to the payload 57-2. The transmission cell header 45-4 to be held and the transmission buffer type field 45-5 indicating which of the transmission buffers 46 and 46 alpha are stored.

The assembly management table 47 updates the reception buffer pointer 47-1 holding the address of the reception buffer 48 or 48α of the cell to be transmitted next, the reception data length 47-2, and cell reception. A reception CRC calculation result 47-3 holding the result of the CRC calculation and a reception buffer type field 47-4 indicating which reception packet assembled in the reception buffer 48 or 48α is stored. do.

13 is a block diagram showing the internal structure of the cell transmission / reception control unit 70. As shown in FIG.

In Fig. 13, the cell transmission / reception control unit 70 converts a reception FIFO 74 that temporarily holds a received cell, a cell decomposition processing unit 75 that decomposes and transmits a cell in the reception FIFO, and converts path information of the cell. And a VC identification CAM 77 for executing the message, a cell header assembly processing unit 71 for generating a transmission cell, and a transmission FIFO 72 for temporarily holding the generated transmission cell. The cell decomposition processing unit 75 selects the payload 57-2 of the cell and the PT field 57-1D (cell type) in the header, respectively, the payload receiving bus 78-3 and the cell type bus 78 -2) is transmitted to the SAR-DMAC 60, and the VPI field 48-1 and the VCI field 48-1C are transmitted to the VC identification CAM 77. A plurality of pairs of VPI, VCI, and VC identifier are registered in advance by the MPU 100. The VC identification CAM 77 searches for a pair matching the VPI 57-1B and the VCI 57-1C input from the cell decomposition processing unit 75. The VC identification CAM 77 then outputs the matched pair of VC identifiers to the SAR-DMAC 60 via the VC identifier bus 78-1.

14 is a block diagram showing the internal structure of the SAR-DMAC 60. As shown in FIG.

In the figure, the SAR-DMAC 60 uses a assembly management table 47 to transmit a receiving DMA controller (hereinafter referred to as RxDMAC) 62 which sequentially stores the receiving cells in the receiving buffer 48 or 48α. A transmission DMA controller (hereinafter referred to as TxDMAC) 61 which sequentially divides packet data stored in the buffer 46 or 46α into cells using the division management table 45, and sequentially transmits them, and a plurality of defined in the buffer memory 40; A host that holds an address of an empty area in a receive buffer pool 65 that holds an empty buffer address in a receive buffer 48 of the receive buffer 48 and a receive buffer 48α defined in the main memory 5. It consists of a receiving buffer pool 66. In addition, the RxDMAC 62 and the TxDMAC 61 have built-in CRC calculation circuits 63 and 64 for performing error detection CRC calculation for the payload to be transmitted.

15 and 16 are flute charts showing the operation of the ATM communication control device 2 during data transmission.

When the MPU 100 receives the packet transmission request from the terminal 1 through the shared memory 80 (step 300), when the received packet transmission request requires a low delay variation, the division management table 45 of FIG. Set the "buffer memory" in the transmission buffer type field 45-5 (302), start the HOST / DMAC 50, and transmit the transmission packet stored in the main memory 5 to the corresponding transmission buffer of the VC ( 46) (303). The AAL type CPCS header, CPCS trailer, SAR header, and SAR trailer corresponding to the transmission packet transmitted to the transmission buffer 46 (other than the CRC field 56-1E of FIG. 6 in the case of the AAL 5). (304), and the template of the cell header (57-1 in Figs. 4, 5 and 6) to be added to the head address of the transmission buffer 46, the transmission data length and the cell to be transmitted, It sets to 45 (305). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (306). The TxDMAC 61 sets the transmission buffer pointer 45-1, the transmission data length 45-2, and the transmission CRC calculation result 45-3 (the initial value is 0) in the division management table 45 corresponding to the designated VC identifier. ), The transmission cell header 45-4 is read (307). Next, the transmission data is read in units of 48 bytes, combined with the previously read cell header 45-4 to form a cell, and transmitted (308). At this time, CRC calculation is performed on the payload portion.

After completion of the cell transmission, the CRC calculation result is saved to the division management table, and the transmission buffer pointer 45-1 and the transmission data length 45-2 are updated in preparation for the next cell transmission (309). Thereafter, steps 307 to 309 are repeated until the transmission data length 45-2 becomes " 0 " (310).

If the packet transmission request received in step 301 does not particularly require a low delay variation, " main memory " is set in the transmission buffer type field 45-5 of the division management table 45 (311). In addition, in the case of the AAL 5, a CPCS header, a CPCS trailer, a SAR header, and a SAR trailer of the corresponding AAL type are added (312) other than the CRC field 56-1E to the transmission packet in the main memory. The head address, the transmission data length, and the template of the cell header added to the cell to be transmitted are set in the division management table 45 (313). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (314).

The TxDMAC 61 performs a transmission buffer pointer 45-1, a transmission data length 45-2, and a transmission CRC calculation result 45-3 (initial value) in the division management table 45 corresponding to the designated VC identifier. 0) and transmit cell header 45-4 are read (315), respectively. Next, the transmission data is read in units of 48 bytes, combined with the previously read cell header 45-4 to form a cell, and transmitted (316). At this time, CRC calculation is performed on the payload portion. After completion of the cell transmission, the result of CRC calculation is saved to the division management table, and the transmission buffer pointer 45-1 and the transmission data length 45-2 are updated in preparation for the next cell transmission (317). Thereafter, steps 315 to 317 are repeated until the transmission data length 45-2 becomes " 0 " (318).

When transmission of the last cell is completed, (in the case of AAL (5), the CRC calculation result at that time is inserted into the CRC field of the CPCS trailer (56-1E in FIG. 6)) and transmitted to the PHY controller 9 (319). ). When all packet transmissions are completed, the TxDMAC 61 notifies the MPU 100 of the completion of packet transmission (320). Upon receipt of this notification, the MPU 100 notifies the terminal 1 of the completion of packet transmission (321).

17 is a flowchart showing an example of processing for selecting a reception buffer in the controller 8. FIG. At the start of communication, the MPU 100 first establishes an ATM connection (step 400). When the set ATM connection requires low delay variation, the MPU 100 sets " buffer memory " in the reception buffer type field 47-4 of the assembly management table 47 (402). The address of the reception buffer 48 defined at 40 is registered in the reception buffer pool 65 in the SAR / DMAC 60 (403).

If an ATM connection is set up to handle traffic that does not require low delay variations during transmission, " main memory " is set in the reception buffer type field 47-4 of the assembly management table 47 (404). The address of the receiving buffer 48α defined in the memory 5 is registered in the host receiving buffer pool 66 in the SAR / DMAC 60 (405).

18 and 19 are flowcharts showing the operation of the ATM communication control device 2 at the time of cell reception.

In the cell transmission control unit 70 of the ATM controller 8, when the cell is received by the PHY controller 9 (step 406), the cell decomposition processing unit 75 analyzes the selector of the receiving cell, and the cell type 78-2. At the same time, the VC identification CAM 77 is used to identify the VC (407). The cell transmission / reception control unit 70 then starts the RxDMAC 62 by designating the cell type 78-2 and the VC identifier 78-1. In the RxDMAC 62, the cell type 78-2 is determined (409). If it is not the data cell 57, the RxDMAC 62 transmits the cell to the reception buffer 49A for the management cell and at the same time (410), the MPU 100. The reception of the management cell is notified 411. Upon receipt of this notification, the MPU 100 executes processing according to the received management cell (412). In addition, the MPU 100 creates a response management cell on the management cell transmission buffer 49B as necessary. Thereafter, the MPU 100 activates the TxDMAC 61, and transmits the created management cell via the TxDMAC 61 (413 and 414).

In step 409, when the received cell is the data cell 57, a parameter is read from the assembly management table 47 corresponding to the identified VC (415). Then, the reception buffer type field 47-4 is checked (416).

When the "main memory" is set in this field and no reception buffer is registered in the reception buffer pointer 47-1, the address of the empty reception buffer in the host reception buffer pool 66 is set. Is obtained and registered in the reception buffer pointer 47-1 (417, 418), and the payload portion of the received cell is transferred to the reception buffer 48α of the main memory 5 while performing CRC calculation. (419). Here, the reception buffer 48α is indicated by the reception buffer pointer 47-1. When the transmission is completed, the RxDMAC 62 evacuates the CRC calculation result to the reception CRC calculation result 47-3 of the assembly management table 47, and the reception buffer pointer 47-1 in preparation for the next cell reception. And the received data length 47-2 are updated (420). Thereafter, steps 406 to 420 are repeated until the PT field 57-1D of the received selector 57-1 recognizes the reception of the final cell, and the receiving cells are assembled to place on the receiving buffer 48α. A receiving packet is formed (421). When the RxDMAC 62 recognizes the reception of the last cell, the RxDMAC 62 checks the normality from the CRC calculation result, and the MPU 100 receives the address of the reception buffer and the received data length as packet reception completion information. Inform 422. Thereafter, the reception buffer pointer 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared in preparation for the next reception (423). The MPU 100 that has received the packet reception completion notification notifies the terminal 1 of the completion of packet reception through the shared memory 80 (424).

In step 416, if " buffer memory " is set in the reception buffer type field 47-4, and no reception buffer 48 is registered in the reception buffer pointer 47-1, the reception buffer pool 65 ), The first address of the empty receiving buffer is taken out and registered in the receiving buffer pointer 47-1 of the assembly management table 47 (426, 427). Then, the payload portion of the received cell is transmitted while performing CRC calculation to the address indicated by the reception buffer pointer 47-1 (428). When the transmission is completed, the RxDMAC 62 evacuates the CRC calculation result to the reception CRC calculation result 47-3 of the assembly management table 47, and prepares for reception of the next cell with the reception buffer pointer 47-1. The received data length 47-2 is updated (429). Thereafter, steps 406 to 429 are repeated until the reception of the final cell is recognized by the PT field 57-1D of the received cell header 57-1, and the receiving cells are assembled to form the receiving buffer 48. A receiving packet is formed at 430. Upon reception of the final cell, the RxDMAC 62 checks the normality from the CRC calculation result, and notifies the MPU 100 of the address of the receiving buffer and the received data length as packet reception completion information (431). ). Thereafter, the reception buffer pointer 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared for the next reception (432). Upon receiving the packet reception completion notification, the MPU 100 starts up the HOST / DMAC 50 and transmits the received packet to the main memory 5 (433). After completion of the transmission, the MPU 100 notifies the terminal 1 of the completion of packet reception through the shared memory 80 (434). Finally, the MPU 100 reregisters the head address of the reception buffer 48, which has been made empty by transmission, with the reception buffer pool 65 (435).

FIG. 20 shows an example of a time chart showing the operation of the ATM communication control device 2 when the ATM protocol process is executed in accordance with the flue chart of FIGS. 15 to 19.

As shown in Fig. 20, when the transmission buffer type and the reception buffer type are the main memories, the processing load of the MPU 100 is reduced compared to the case where the transmission buffer type and the reception buffer memory type are the buffer memories, and the HOST It can be seen that the transfer time is shortened as the data transfer between the MDMA and the MPU is not necessary. In addition, although only one direction of communication is shown in the figure, actual communication is performed in both directions.

As described above, the ATM communication control apparatus 2 of the present embodiment has a large influence of the delay fluctuation during transmission, and the cell division / assembly processing is performed on the buffer memory for the VC that requires real-time performance. Traffic can be realized. In addition, although the influence of the delay fluctuation is small, the transmission / reception cell can be directly transmitted between the main memory 5 and the SAR / DMAC 60 for the VC requiring high speed, thereby reducing the data transmission time. In addition, a reduction in the processing load of the MPU 100 related to transmission is achieved.

(Example 2)

Next, another embodiment of the present invention will be described.

The ATM communication control apparatus of the first embodiment selects one of the main memory 5 and the buffer memory 40 as the transfer destination for each VC, depending on the nature of the traffic to be handled. However, the ATM communication control apparatus according to the second embodiment can select the transmission location according to the traffic amount regardless of the nature of the traffic and the unit of the VC. In this embodiment, when the load fluctuation of the system bus becomes large by using HOST · DMAC, which has a means for empirically detecting a congestion state of the system bus in the terminal, the transfer destination is a buffer memory. The effects of delay fluctuations due to load fluctuations can be avoided.

In addition, when the load variation of the system bus is small, high-speed traffic can be transmitted by direct transmission from the main memory or direct transmission to the main memory.

In the following, a part different from the apparatus of the first embodiment of the operation of the communication control apparatus 2 will be described.

21 and 22 are flowcharts showing operations at the time of data transmission by the ATM communication control apparatus 2.

When the MPU 100 receives a packet transmission request from the terminal 1 through the shared memory 80 (step 500), the MPU 100 has means for empirically detecting a congestion state of the system bus 6 in the terminal 2. When the DMAC 50 determines that the load fluctuation of the system bus is large (501), " buffer memory " is set in the transmission buffer type field 45-5 of the division management table 45 (502). The DMAC 50 is activated to transmit the transmission packet stored in the main memory 5 to the transmission buffer 46 of the corresponding VC (503). Then, a CPCS header, a CPCS trailer, a SAR header, and a SAR trailer of a corresponding AAL type other than the CRC field (56-1E in Fig. 6) of the AAL 5 are added to the transmission packet transmitted to the transmission buffer 46. (504), the head address of the transmission buffer 46, the transmission data length, and a template of the cell header added to the cell to be transmitted are set in the division management table 45 (505). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (506). The TxDMAC 61 receives the transmission buffer pointer 45-1, the transmission data length 45-2, and the transmission CRC calculation result 45-3 (the initial value is 0) from the division management table 45 corresponding to the designated VC identifier. ), And transmit cell header 45-4, respectively (507). Next, the transmission data is read in units of 48 bytes. The cells are formed by combining with the first read cell header 45-4 and transmitted (508). At this time, CRC calculation is performed on the payload portion. After completion of cell transmission, in the case of AAL 5, the result of CRC calculation is saved to the division management table, and the transmission buffer pointer 45-1 and the transmission data length 45-2 are prepared for the next cell transmission. It is updated (509). Thereafter, steps 507 to 509 are repeated until the transmission data length 45-2 becomes " 0 " (510).

In step 501, when it is determined that the load fluctuation of the system bus is small by the HOST-DMAC 50 having a means for empirically detecting a congestion state of the system bus 6 in the terminal 2, the division management table 45 &Quot; Main memory " is set in the transmission buffer type field 45-5 of step (511).

A CPCS header, a CPCS trailer, a SAR header, and a SAR trailer of corresponding AAL type other than the CRC field (56-1E in FIG. 6) are added to the transmission packet in the main memory (512), and the transmission buffer 46? The head address, the transmission data length, and the template of the cell header added to the cell to be transmitted are set in the division management table 45 (513). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (514). The TxDMAC 61 receives the transmission buffer pointer 45-1, the transmission data length 45-2, and the transmission CRC calculation result 45-3 from the division management table 45 corresponding to the designated VC identifier (the initial value is 0). ), And transmit cell header 45-4, respectively (515). Next, the transmission data is read in units of 48 bytes, and the cells are combined with the cell header 45-4 read out first, and then transmitted (516). At this time, CRC calculation is performed on the payload portion. After the end of cell transmission, in the case of AAL 5, the result of CRC calculation is saved to the division management table, and the transmission buffer pointer 45-1 and the transmission data length 45-2 are updated in preparation for the next cell transmission. (517) Thereafter, steps 515 to 517 are repeated until the transmission data length 45-2 becomes " 0 " (518).

When the transmission of the last cell is completed, the AAL 5 inserts the CRC calculation result at that time into the CRC field (47-5 in Fig. 6) of the CPCS trailer and transmits it to the PHY controller 9 (519). . When all packet transmissions are completed, the TxDMAC 61 notifies the MPU 100 of the completion of packet transmission (520). Upon receipt of this notification, the MPU 100 notifies the terminal 1 of the completion of packet transmission (521).

23 and 24 are flowcharts showing the operation of the ATM communication control device 2 at the time of cell reception.

When the cell transmit / receive controller 70 of the ATM controller 8 receives the cell from the PHY controller 9 (step 600), the cell decomposition processor 75 interprets the cell header of the received cell, and classifies the cell (78-2). ) Is identified and the VC identification CAM 77 is used to identify the VC (601). The cell transmit / receive controller 70 activates the RxDMAC 62 by specifying the cell type 78-2 and the VC identifier 78-1 (step 602). In the RxDMAC 62, the cell type 78-2 is determined (603). If it is not the data cell 48, the RxDMAC 62 transmits the cell to the receiving buffer 49A for the management cell and at the same time (604), the MPU 100 The reception of the management cell is notified 605. Upon receiving this notification, the MPU 100 executes the processing according to the received management cell (606). In addition, the MPU 100 creates a response management cell on the management cell transmission buffer 49B as needed. The MPU 100 then starts up the TxDMAC 61 and transmits the created management cell via the TxDMAC 61 (607, 608).

In step 603, when the received cell is the data cell 48, when the load on the system bus is large, the MPU adds " buffer memory " to the receive buffer type field 47-4 of the assembly management table 47. Set 610. If the reception buffer 48 is not registered in the reception buffer pointer 47-1, the first address of the empty reception buffer is taken out from the reception buffer pool 65, and the reception buffer pointer 47 of the assembly management table 47 is taken out. -1) (611, 612). Then, the payload portion of the received cell is transmitted to the address indicated by the reception buffer pointer 47-1 while performing CRC calculation (613). When the transmission is completed, the RxDMAC 62 saves the CRC calculation result to the reception CRC calculation result 47-3 of the assembly management table 47 in the case of AAL 5, and receives it in preparation for the next cell reception. The buffer pointer 47-1 and the received data length 47-2 are updated (614). Subsequently, steps 600 to 614 are repeated until the PT field 57-1D of the received cell header 57-1 recognizes the reception of the final cell, and the receiving cells are assembled to receive the reception buffer 48. A receiving packet is formed at 615. Upon reception of the last cell, the RxDMAC 62 checks the normality from the CRC calculation result and notifies the MPU 100 of the address of the receiving buffer and the received data length as packet reception completion information (616). ). Thereafter, the reception buffer pointer 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared in preparation for the next reception (617). Upon receiving the packet reception completion notification, the MPU 100 starts the HOST-DMAC 50 and transmits the received packet to the main memory 5 (618). After completion of the transmission, the MPU 100 notifies the terminal 1 of the completion of packet reception through the shared memory 80 (619). Finally, the MPU 100 re-registers (620) the head address of the reception buffer 48, which is made empty by transmission, with the reception buffer pool 65.

In step 609, when the load on the system bus is not large, that is, when it is not in a runaway state, " main memory " is set in the reception buffer type field 47-4 of the assembly management table 47 (621). When no reception buffer is registered in the reception buffer pointer 47-1, an address of an empty reception buffer is obtained from the host reception buffer pool 66, and registered in the reception buffer pointer 47-1. (622, 623). Then, the payload portion of the received cell is transferred to the reception buffer 48α of the main memory 5 while performing CRC calculation (624). Here, the reception buffer 48α is indicated by the reception buffer pointer 47-1. When the transmission is completed, the RxDMAC 62 evacuates the CRC calculation result to the reception CRC calculation result 47-3 of the assembly management table 47, and prepares for reception of the next cell with the reception buffer pointer 47-1. The received data length 47-2 is updated (625). Thereafter, steps 600 to 625 are repeated until the PT cell 57-1D of the received cell header 57-1 recognizes the reception of the final cell, and the receiving cells are assembled to receive the reception buffer 48α. A receiving packet is formed at 626. Upon reception of the final cell, the RxDMAC 62 checks the normality from the CRC calculation result, and notifies the MPU 100 of the address of the receiving buffer and the received data length as packet reception completion information (627). ). Thereafter, the reception buffer pointer 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared in preparation for the next reception (628). The MPU 100 that has received the packet reception completion notification notifies the terminal 1 of the completion of packet reception through the shared memory 80 (629).

As described above, in the ATM communication control apparatus 2 of the present embodiment, one of the main memory 5 and the buffer memory 40 is selected as the cell transfer destination by the congestion state (traffic amount) of the system bus irrespective of the VC. By doing so, when the additional variation of the system bus in the terminal becomes large, that is, the effect of the delay variation due to the congestion state can be avoided as much as possible, and the high speed traffic can be transmitted when the congestion state is not.

(Example 3)

Next, an ATM communication control apparatus according to a third embodiment of the present invention will be described.

In the second embodiment, the ATM communication control apparatus according to the present embodiment selects either the main memory 5 or the buffer memory 40 according to the amount of traffic as the transmission location. It is important to make it as small as possible, and to transfer it to the buffer memory as long as there is a space in the buffer memory, so that the main memory is selected as the transfer location when the space is lost.

In the following, a part different from the apparatus of the second embodiment of the operation of the communication control apparatus 2 will be described.

25 and 26 are flute charts showing the operation of the ATM communication control device 2 during data transmission.

When the MPU 100 receives a packet transmission request from the terminal 1 through the shared memory 80 (step 700), when there is a space in the buffer memory (701), the transmission buffer type field of the division management table 45 is received. "Buffer memory" is set in (45-5) (702), the HOST / DMAC 50 is started, and the transmission packet stored in the main memory 5 is transmitted to the corresponding transmission buffer 46 (703). ). For the transmission packet transmitted to the transmission buffer 46, a CPCS header, a CPCS trailer, a SAR header, and a SAR trailer of a corresponding AAL type other than the CRC field (56-1E in FIG. 6) are added (704). The head address of the transmission buffer 46, the transmission data length, and the template of the cell header added to the cell to be transmitted are set in the division management table 45 (705). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (706). The TxDMAC 61 sets the transmission buffer pointer 45-1, the transmission data length 45-2, and the transmission CRC calculation result 45-3 (initial value) in the division management table 45 corresponding to the designated VC identifier. 0) and the transmitting cell header 45-4 are respectively read (707). Next, the transmission data is read in units of 48 bytes, the cells are combined with the previously read cell header 45-4, and transmitted (708). At this time, CRC calculation is performed for the payload part.

After the cell transmission is completed, the CRC calculation result is saved to the division management table, and the transmission buffer point 45-1 and the transmission data length 45-2 are updated in preparation for the next cell transmission (709). Thereafter, steps 707 to 709 are repeated until the transmission data length 45-2 becomes "0" (710).

If there is no space in the buffer memory in step 701, "main memory" is set in the transmission buffer type field 45-5 of the division management table 45 (711). For the transmission packet in the main memory, a corresponding AAL type CPCS header, CPCS trailer, SAR header, and SAR trailer other than the CRC field are added (712), the head address of the transmission buffer 46α, and the transmission data length. And a template of a cell header added to the cell to be transmitted are set in the division management table 45 (713). Next, the MPU 100 starts the TxDMAC 61 by specifying a VC identifier indicating the VC to be transmitted, and requests transmission of the cell (714). The TxDMAC 61 converts the transmission buffer point 45-1, the transmission data length 45-2, and the transmission CRC calculation result 45-3 from the division management table 45 corresponding to the designated VC identifier. 0) and the transmission cell header 45-4 are read out respectively (715). Next, the transmission data is read in units of 48 bytes, combined with the previously read cell header 45-4 to form a cell, and transmitted (716). At this time, CRC calculation is performed on the payload portion. After transmission of the cell, the result of the CRC calculation is saved to the division management table, and the transmission buffer point 45-1 and the transmission data length 45-2 are updated in preparation for the next cell transmission (717). Thereafter, steps 715 to 717 are repeated until the transmission data length 45-2 becomes "0" (718).

When the transmission of the last cell is completed, the CRC calculation result at that time is inserted into the CRC field (56-1E in FIG. 6) of the CPCS trailer and transmitted to the PHY controller 9 (719). When all packet transmissions are completed, the TxDMAC 61 notifies the MPU 100 of the completion of packet transmission (720). Upon receipt of this notification, the MPU 100 notifies the terminal 1 of the completion of packet transmission (721).

27 and 28 are flute charts showing the operation of the ATM communication control device 2 at the time of cell reception.

In the cell transmission / reception control unit 70 of the ATM controller 8, when the cell is received from the PHY controller 9 (step 800), the cell decomposition processing unit 75 analyzes the cell header of the reception cell, and determines the cell type (78-). 2), the VC identification is performed using the VC identification CAM 77 (801). The cell transmission / reception control unit 70 activates the RxDMAC 62 by designating the cell type 78-2 and the VC identifier 78-1 (step 802). In the RxDMAC 62, the cell type 78-2 is determined (803). If it is not the data cell 48, the RxDMAC 62 transmits the cell to the reception buffer 49A for the management cell and at the same time (804) to the MPU 100. The reception of the management cell is notified (805). Upon receipt of this notification, the MPU 100 performs processing according to the received management cell (806), creates a management cell for a reply on the management cell transmission buffer 49B as needed, and starts the TxDMAC 61, The created management cell is transmitted (807, 808).

In step 803, when the received cell is a data cell 48, when there is an address of an empty receiving buffer in the receiving buffer pool 65 in the SAR / DMAC 60 (809), the SAR / DMAC 60 is stored. As a result, " buffer memory " is set in the reception buffer type field 47-4 of the assembly management table 45 (810). If the reception buffer 48 is not registered in the reception buffer point 47-1, the head address of the empty reception buffer is taken out of the reception buffer pool 65, and the reception buffer point (in the assembly management table 47) is obtained. 47-1) (811, 812). Then, the payload portion of the received cell is transmitted to the address indicated by the reception buffer point 47-1 by performing CRC calculation (813). When the transmission is completed, the RxDMAC 62 evacuates the CRC calculation result to the reception CRC calculation result 47-3 of the assembly management table 47, and prepares for reception of the next cell to receive the reception buffer point 47-1. ) And the received data length 47-2 are updated (814). Subsequently, steps 800 to 814 are repeated until the PT cell 57-1D of the received cell header 57-1 recognizes the reception of the final cell. Then, the receiving cells are assembled and placed on the reception buffer 48. A receiving packet is formed (815). Upon reception of the final cell, the RxDMAC 62 checks the normality in the CRC calculation result, and notifies the MPU 100 of the reception buffer address and the received data length as packet reception completion information (816). . Thereafter, the reception buffer point 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared in preparation for the next reception (817). Upon receipt of the packet reception completion notice, the MPU 100 starts up the HOST / DMAC 50 and transmits the reception packet to the main memory 5 (818). After completion of the transmission, the MPU 100 notifies the terminal 1 of the completion of packet reception through the shared memory 80 (819). Finally, the MPU 100 re-registers the head address of the reception buffer 48, which became an empty area by transmission, with the reception buffer pool 65 (820).

In step 809, if there is no address of the empty receiving buffer in the receiving buffer pool 65, the SAR / DMAC 60 displays the "main memory" in the receiving buffer type field 47-4 of the assembly management table 45; Is set (821). When no reception buffer is registered in the reception buffer point 47-1, the host reception buffer pool 66 obtains an address of the empty reception buffer, and the reception buffer point 47-1 is obtained. Register (822, 823). Then, the payload portion of the received cell is transferred to the receiving buffer 48α of the main memory 5 which teaches the receiving buffer point 47-1 while performing CRC calculation (824). When the transmission is completed, the RxDMAC 62 evacuates the assembly management table 47 to the received CRC calculation result 47-3 and returns the CRC calculation result to the reception buffer point 47-1 in preparation for the next cell reception. And the received data length 47-2 are updated (825). Thereafter, the steps 800 to 825 are repeated until the PT cell 57-1D of the received cell header 57-1 recognizes the reception of the final cell, and the receiving cell is assembled to receive the buffer 48α. A received packet is formed on the block (826). When the RxDMAC 62 recognizes the reception of the last cell, the RxDMAC 62 checks the normality in the CRC calculation result and notifies the MPU 100 of the reception buffer address and the reception data length as packet reception completion information ( 827). Then, in preparation for the next reception, the reception buffer point 47-1, the reception data length 47-2, and the reception CRC calculation result 47-3 field are cleared (828). Upon receipt of the packet reception completion notification, the MPU 100 notifies the terminal 1 of the completion of packet reception through the shared memory 80 (829).

The MPU may perform conversion recording of the reception buffer type.

As described above, in the ATM communication control apparatus 2 of the present embodiment, regardless of the VC, the traffic whose priority is made to minimize delay fluctuation as much as possible by transferring a cell having a free space in the buffer memory to the buffer memory at all times. This becomes possible.

(Example 4)

Next, an ATM communication control apparatus according to a fourth embodiment of the present invention will be described.

The ATM communication control apparatus according to the present embodiment is provided with a buffer memory for storing cells to be transmitted and received and information necessary for dividing and assembling cells so as to reduce the number of pins of the ATM controller between the MPU and the ATM controller. .

In the following, within the operation of the communication control apparatus 2, a part different from the apparatus of the first embodiment will be described.

29 is a block diagram showing an example of the configuration of the ATM communication control apparatus 2α.

The buffer memory 40α in the ATM communication control device 2α is a bridge 120 that coordinates the access from the MPU 100 to the buffer memory 40α and the access from the arbiter 110 to the buffer memory 40α. ), The internal bus 200 and the local bus 230 are connected to each other in the controller.

As described above, in the first embodiment, the ATM controller 8 requires a pin for connecting to the buffer memory 40 and for connecting to the MPU 100, whereas in the present embodiment, the buffer memory 40α is used. Is provided between the MPU 100 and the ATM controller 8α, the access to the buffer memory 40α and the ATM controller 8α from the MPU 100 is completed only by connection with the bridge 120, and the ATM controller. The number of pins of (8) can be greatly reduced.

According to the present invention, the delay variation can be reduced or the data transmission time can be shortened. Therefore, it is possible to provide an ATM controller and an ATM communication control apparatus capable of achieving higher quality data communication.

Claims (8)

In an ATM controller that performs processing of an ATM layer and an AAL layer of an ATM protocol between a transmission path and a terminal, Transmission means connected to an external buffer memory and transmitting packet data between the terminal and the buffer memory; Cell transmission control means for dividing the packet data stored in the buffer memory or memory into data cells and transmitting the divided data cells to an ATM network side; Cell type determining means for examining a part of a header of a cell received by the ATM network to determine whether the cell is a data cell; Cell reception control means for assembling a data cell to generate packet data and storing the generated packet data in the buffer memory or memory; According to the nature of the traffic in the established ATM connection, the cell transmission control means stores the packet data divided into cells and the packet data generated by the cell reception control means, respectively, in the buffer memory and the terminal. And selecting means for selecting any one of the memories, The microcontroller is connected to a program memory that stores and maintains a control program, and executes analysis of cells other than data cells identified by the cell type determination and processing according to the result of the analysis in accordance with the control program. ATM controller connected to the processor. The method of claim 1, A storage location for packet data divided into cells by said cell transmission control means and a storage location for packet data generated by said cell reception control means, And a means for selecting one of the buffer memory and the memory in the terminal according to the presence or absence of a low delay change request. The method of claim 1, HOST · DMAC having means for empirically detecting a congestion state of a system bus in a terminal is used, and a storage location of packet data divided by the cell transmission control means into cells according to the traffic amount and the cell reception control means are generated. And a means for selecting one of the buffer memory and the memory in the terminal as a storage location of one packet data. The method of claim 1, The cell transmission control means stores the packet data divided into cells and the packet data generated by the cell reception control means, and transfers the data to the buffer memory as long as there is a space in the buffer memory. ATM controller, characterized in that it has a means for transmitting to a memory in the terminal. In an ATM communication control apparatus that performs processing of an ATM layer, an AAL layer, and a PHY layer of an ATM protocol between a transmission path and a terminal, An ATM controller according to claim 1, 2, 3 or 4, A buffer memory connected to the ATM controller, A PHY controller that executes processing of the PHY layer between the ATM controller and the transmission path; And a crystal oscillator for driving the PHY controller. The method of claim 5, And the buffer memory is arranged between the microprocessor and the ATM controller. The method of claim 5, The ATM controller according to any one of claims 1, 2, 3 or 4, wherein the ATM controller is composed of one chip LSI. A communication system comprising an ATM communication control device according to claim 5, 6 or 7, a main processor in a terminal, a main memory, and a system bus for connecting them.