KR19990083380A - CMOS FET and manufacturing method thereof - Google Patents

Abstract

The CMOS FET according to the present invention includes an buried channel type nMOS region 121 and a surface channel type pMOS region 123. A p ⁺ diffusion layer 105, an n ⁻ diffusion layer 117, and an isolation layer (SiO ₂ ) 113, which is an isolation layer, are formed on the silicon (Si) substrate 100. The p ⁺ diffusion layer 105 and the n ⁻ diffusion layer 117 become the source and drain of the pMOS FET and the source and drain of the nMOS FET. A silicon dioxide film 115 is formed on the silicon substrate 100. The gate electrode 141 and the gate electrode 143 are formed on the silicon dioxide film 115. The gate electrode 141 includes a polysilicon layer 119, a titanium nitride (TiN) layer 109, and a tungsten (WSi ₂ ) layer 131. A dopant such as boron is injected into the polysilicon layer 119, and this layer changes to a P-type polarity. The gate electrode 143 includes a polysilicon layer 107, a titanium nitride (TiN) layer 109, and a tungsten (WSi ₂ ) layer 133. A dopant such as boron is injected into the polysilicon layer 107, and the layer changes to a P-type polarity.

Description

CMOS FET and its manufacturing method {CMOS FET and manufacturing method

The present invention relates to a CMOS Complementary Metal Oxide Semiconductor Field-Effect Transistor (FET) and a method of manufacturing the same. More specifically, it relates to a CMOS FET that operates at high speed and has low power consumption, and a method of manufacturing the same.

The demand for semiconductor integrated circuits has gradually increased. Therefore, it has been required to increase the operation speed of the semiconductor device constituting the semiconductor integrated circuit and to reduce the power consumption.

CMOS FETs composed of n-channel metal oxide semiconductors (nMOS) and p-channel metal oxide semiconductors (pMOS) are widely used in semiconductor devices. This can reduce power consumption.

Here, the configuration of the CMOS FET will be described with reference to FIG. 1 shows an example of an equivalent circuit of a CMOS FET.

As shown in FIG. 1, the CMOS FET is composed of a pMOS FET 1100 and an nMOS FET 1101. In general, the source Sp of the pMOS FET 1100 and the drain Dn of the nMOS FET 1101 are connected to each other.

Voltage is applied to the gates of the pMOS FET and nMOS FET. As shown in Fig. 1, this is described as an input voltage Vin. The voltage of the source Sp of the pMOS FET 1100 and the drain Dn of the nMOS FET 1101 is defined as an output voltage Vout.

Also, the current flowing between the drain Dp of the pMOS FET 1100 and the source Sn of the nMOS FET 1101 is defined as a through current I. The above definitions are used equally throughout the specification.

Next, a conventional CMOS FET is described in detail with reference to FIG. 2 is a sectional view of an example of a conventional CMOS FET.

As shown in FIG. 2, the conventional CMO SFET includes an nMOS region 221 in which an nMOS FET is formed on a silicon substrate 200, and a pMOS region 223 in which a pMOS FET is formed. A gate electrode 241 is formed in the nMOS region 221 by ion implantation of impurities having an n-type polarity, while a gate electrode 243 is ion implanted in an impurity having an n-type polarity in the pMOS region 223. Is formed.

The conventional CMOS FET shown in FIG. 2 is composed of a surface channel type nMOS region 221 and a buried channel type pMOS region 223. Two p ⁺ diffusion layers 205, two n ⁻ diffusion layers 217, and an isolation layer (SiO ₂ ) 213, which is an oxide layer for device isolation, are all formed on the silicon substrate 200. The P ⁺ diffusion layer 205 and the n ⁻ diffusion layer 217 become source and drain regions of the pMOS FET and source and drain regions of the nMOS FET, respectively.

A gate oxide film (SiO ₂ ) is formed on the silicon substrate 200, and gate electrodes 241 and 243 are formed thereon.

The gate electrode 241 is formed of a polysilicon (poly-Si) layer 219, a titanium nitride (TiN) layer 209, and a tungsten (WSi ₂ ) layer 231. Dopants, such as phosphorus (P), are injected into the polysilicon layer 219, and the layer becomes n-type polarity.

The gate electrode 243 is made of a polysilicon layer 207, a titanium nitride layer 209, and a tungsten layer 233. Dopants, such as phosphorus (P), are injected into the polysilicon layer 207, and the layer becomes n-type polarity.

As shown in FIG. 2, the diffusion layer of nMOS region 221 is n ⁻ diffusion layer 217, while the diffusion layer of pMOS region 223 is P ⁺ diffusion layer 205. Therefore, the channel of the nMOS region 221 is a surface channel type, while the pMOS region 223 is a buried channel type.

The state of the above-described channel will be described with reference to FIG. 3. 3 shows how the channels of the conventional CMOS FET of FIG. 2 are generated. As described above, the diffusion layer of the pMOS region 223 is P ⁺ diffusion layer 205, while the diffusion layer of the nMOS region 221 is n ⁻ diffusion layer 217.

Thus, as shown in FIG. 3, the channel (p channel) 203 of the pMOS region 223 is created as a buried channel type slightly below the surface of the gate silicon dioxide film 215, while the nMOS region 221 is formed. ) Channel (n channel) 201 is created as a surface channel type directly under the gate silicon dioxide film 215.

Meanwhile, the demand for semiconductor integrated circuits has been increased due to the miniaturized structure. Therefore, the design rule (minimum wiring width) has been improved to 1 µm, 0.35 µm, 0.25 µm, and 0.18 µm with the times.

The gate electrode structure of the CMOS FET designed according to a design rule larger than 25 μm is not a problem even if the polarities of the gate electrodes are formed in common for the purpose of shortening the manufacturing process as described in FIG. 2.

However, as described above, since the semiconductor integrated circuit having a miniaturized structure has been continuously developed, when the design rule is 0.25 mu m or less, the short channel effect clearly occurs in the CMOS FET as shown in FIG. There is this.

Here, this short channel effect means the influence from the short gate (distance between the source and the drain) of the MOS FET. Specifically, when the drain voltage VD is made constant and the channel length is shortened, the depletion layer from the drain and the source is extended to the substrate region under the gate, whereby the potential barrier of the channel is lowered and the drain voltage is slightly increased. As a result, the drain current ID rapidly increases, and as this progresses, it means that punchthrough occurs due to the connection of the depletion layer.

Therefore, in order to prevent this short channel effect from occurring, the conventional CMOS FET configuration shown in Fig. 3 has been proposed. 4 is a cross-sectional view showing a second example of a conventional CMOS FET. In Fig. 4, the same elements as those in Fig. 2 are designated by the same reference numerals.

As shown in FIG. 4, the second example of the conventional CMOS FET includes a surface channel type nMOS region 321 and a pMOS region 323. Two p ⁺ diffusion layers 205, two n ⁻ diffusion layers 217, and an isolation layer (SiO ₂ ) 213 are all formed on the silicon substrate 200. The P ⁺ diffusion layer 205 and the n ⁻ diffusion layer 217 become source and drain regions of the pMOS FET and source and drain regions of the nMOS FET, respectively.

In addition, a gate (SiO ₂ ) 215 which is a gate oxide film is formed on the silicon substrate 200. Gate electrodes 341 and 343 are formed on the gate 215.

The gate electrode 341 is formed of a polysilicon (Poly-Si) layer 319, a titanium nitride (TiN) layer 209, and tungsten (WSi ₂ ) 231. A dopant such as phosphorus (P) is implanted into the polysilicon layer 319 to be converted into an n-type polarity.

The gate electrode 343 is composed of a polysilicon layer 307, a titanium nitride layer 209, and a tungsten layer 233. For example, dopants such as boron are implanted into the polysilicon layer 307, and this layer becomes a p-type polarity.

The structure of the CMOS FET shown in FIG. 4 is generally called a surface channel type dual gate type CMOS FET. As apparent from Fig. 7, this CMOSFET has a configuration substantially the same as that of the conventional CMOS FET shown in Fig. 2, except that the polarity of impurities contained in the gate electrode is different from that of the first example of the conventional CMOS FET. Have

Specifically, in the conventional CMOS FET of FIG. 4, the p-type impurity (boron) is contained in the polysilicon layer 307 of the gate electrode 343 of the pMOS region 323, whereas the gate of the nMOS region 321 is formed. The polysilicon layer 319 of the electrode 341 contains p-type impurity (phosphorus).

The gate electrode 343 of the pMOS region 323 has a P-type polarity by injecting a dopant such as boron into it.

Accordingly, the channels created in the nMOS and pMOS regions of FIG. 4 are all surface type. 5 shows the shape of the channel of the CMOS FET of FIG. In FIG. 5, the channels correspond to the channel (p channel) 303 of the pMOS region 323 and the channel (n channel) 301 of the nMOS region 321, respectively.

As described above, the CMOS FET shown in FIG. 4 has been proposed to avoid the short channel effect in the CMOS FET shown in FIG. Specifically, as is apparent from the configuration of FIGS. 4 and 5, the channels 301 and 302 generated in the nMOS region 321 and the pMOS region 323 are both surface type.

This means that the respective channels in the nMOS and pMOS regions are generated near the surface of the silicon substrate and located close to the respective gate electrodes. This makes it easy to control the gate electrode and avoid the short channel effect. On the other hand, for example, in the buried channel type CMOS FET shown in Fig. 2, a channel is generated at a somewhat deep position from the surface of the silicon substrate. This makes it difficult to control the channel with the gate voltage, and also makes it difficult to suppress the occurrence of the short channel effect.

Therefore, according to the second example of the conventional CMOS FET of FIG. 4, the short channel effect in the first example of the conventional CMOS FET shown in FIG. 2 is prevented from occurring.

However, in the second example (dual gate type CMOS FET) of the conventional CMOS FET of Fig. 4, it is possible to prevent the occurrence of the short channel effect, but there is a problem.

The first problem is that the design rules are improved for the microstructure. As described above, semiconductor integrated circuits of smaller and smaller structures have been developed. In particular, a transistor designed based on a design rule of 0.25 mu m or less has a thin gate oxide film (6 nm or less). Therefore, when boron is implanted into the polysilicon layer 307 of the gate electrode 343 as shown in FIG. 4, this dopant penetrates between the P ⁺ diffusion layers in the silicon substrate 200.

In this case, since the impurity concentration of the silicon substrate 200 changes, the voltage required for generating the channel also changes. Therefore, in the CMOS FET of FIG. 4, only the threshold voltage on the pMOS region 323 of the pMOS FET changes.

The result according to the change of the threshold voltage will be described with reference to FIGS. 6A and 6B. 6A and 6B are graphs showing a relationship between an output voltage and a drain current, an input voltage, an output voltage, and a through current of the conventional CMOS FET of FIG. 4.

First, as shown in FIG. 6A, when boron injection is not penetrated (see solid line), the threshold voltage of the pMOS FET of FIG. 4 is approximately equal to VDD1. On the other hand, when boron implantation is penetrated (see dotted line), the voltage required to create the channel is changed so that only the threshold voltage of the pMOS FET changes to approximately VDD2.

As a result, as shown in Fig. 6B, in the case where boron injection is penetrated (shown by a dotted line), even when the input voltage exceeds VDD1, the pMOS FET does not exceed the predetermined value higher than the higher value. It is not turned off. This causes a problem that a large amount of through current flows and power consumption increases.

A second problem with the conventional CMOS FET of FIG. 4 is that it is difficult to sufficiently control the generation of depletion of the gate electrode. Here, the depletion of the gate electrode means that the impurity concentration in the gate electrode is high, but the impurities are not uniformly distributed.

As described above, in order to control the occurrence of the short channel effect of the transistor designed according to the 0.25 탆 design rule, a dual gate (pn-type gate) as shown in FIG. 4 is useful. However, since the impurities of the polysilicon layer of the gate are generally phosphorus and boron, the diffusion coefficients are different.

The uniform distribution of impurities in the gate electrode is a means of controlling the occurrence of depletion. However, it is difficult to uniformly distribute each impurity having different diffusion coefficients in the same aspect. Thus, it is difficult to control the occurrence of depletion at the gates of each independent polarity of the transistor.

A third problem is that it is difficult to control the generation of interdiffusion of impurities in the gate electrode of the second example of the conventional CMOS FET of FIG. Here, interdiffusion of impurities means that the respective impurities are mixed with each other by thermal diffusion. As illustrated in FIG. 4, the gate electrodes connected to each other include a polysilicon layer 319 including n-type impurities and a polysilicon layer 307 including n-type impurities. Therefore, when a dual gate (pn-type gate) is used to control the generation of a short channel effect of a transistor designed according to a design rule of 0.25 μm or less, impurities having n-type and p-type polarities at the gate electrode are subjected to heat treatment. Interdiffusion.

A fourth problem with the method of fabricating the second example of the conventional CMOS FET of FIG. 4 is that two photoresist using processes are required to complicate the fabrication.

This generally comes from the fact that dual gates (pn-type gates) are used to control the occurrence of short channel effects of transistors designed according to design rules of 0.25 μm or less or subsequently developed design rules. In addition, when a polyside gate is used, it is necessary to inject impurities into each gate electrode separately in addition to the injection operation into the source and drain. Therefore, two separate photoresist using processes are required.

Next, an example of a manufacturing method of the second example of the conventional CMOS FET of FIG. 4 will be described with reference to FIGS. 7A to 7F. 7A to 7B show a manufacturing method of a second example of the conventional CMOS FET of FIG.

First, as shown in FIG. 7A, a photoresist 353 is formed on the pMOS region 323. Next, as shown in FIG. 7B, a dopant such as phosphorus (P) 355 is implanted into the polysilicon layer 351 of the nMOS region 321.

Next, as shown in FIG. 7C, the photoresist 353 on the pMOS region 323 is removed, and a photoresist 357 is formed on the nMOS region 321. Next, as shown in FIG. 7D, a dopant such as boron is implanted into the polysilicon layer 351 of the pMOS region 323.

Next, as shown in FIG. 7E, the photoresist 357 of the nMOS region 321 is removed, and then a titanium nitride (TiN) layer 321 and a tungsten (WSi ₂ ) insect 361 are deposited. do.

Finally, as shown in FIG. 7F, the deposited layers are patterned to form gate electrode 341 and gate electrode 343 to fabricate a CMOS FET.

As described above, in the manufacturing process of the second example of the conventional CMOS FET, the impurities injected into the respective gates of the nMOS FET and the pMOS FET are different from each other. Therefore, two photoresist using processes are required.

On the other hand, in the second example of the buried channel type conventional CMOS FET as shown in Fig. 2, an nn type gate is used. This nn type gate is advantageous in simplifying the manufacturing process and is excellent in preventing the occurrence of interdiffusion and penetration of boron injection. However, it is difficult to control the occurrence of the short channel effect because of the fact that the pMOS FET is a buried channel type.

In summary, since it is difficult to prevent the occurrence of the short channel effect in the nMOS FET and the pMOS FET, in order to prevent the short channel effect in a transistor manufactured according to a design rule of 0.25 mu m or less, as shown in FIG. Dual gate (pn type gate) is required.

Accordingly, an object of the present invention is to improve the current driving capability of the nMOS FET to enhance the operation speed of the CMOS FET, reduce the through current to reduce the power consumption, and simplify the CMOS FET manufacturing process step. To provide.

1 shows a configuration of an equivalent circuit of a CMOS FET.

2 is a cross-sectional view of a first example of a conventional CMOS FET.

3 is a diagram illustrating a basic shape of a channel generated in the CMOS FET of FIG. 2.

4 is a cross-sectional view of a second example of a conventional CMOS FET.

FIG. 5 is a diagram illustrating a basic shape of a channel generated in the CMOS FET shown in FIG. 4.

6A and 6B are graphs illustrating operation characteristics of the CMOS FET of FIG. 4.

7A to 7E are diagrams showing the steps of a process procedure for manufacturing a conventional CMOS FET.

8 is a cross-sectional view of a CMOS FET according to a first embodiment of the present invention.

9A to 9C are diagrams illustrating a CMOS FET manufacturing method or a manufacturing process sequence of FIG. 8 according to the first embodiment of the present invention.

10A and 10B are graphs illustrating characteristics of the CMOS FET of FIG. 8.

FIG. 11 is a diagram illustrating a basic shape of a channel generated in the CMOS FET of FIG. 8.

12 is a diagram showing the configuration of a three-dimensional CMOS FET according to the second embodiment of the present invention.

※ Explanation of symbols for main parts of drawing

100: silicon substrate 105: P ⁺ diffusion layer

107,119,707,719 Polysilicon layer 109,709 Titanium nitride layer

113 device isolation film 115,715 silicon dioxide film

117: n ^- diffusion layer 121,771: nMOS region

123,770: pMOS region 131,133,731,733: tungsten layer

141, 143, 741, 743: gate electrode 500: p-type well

501 n-type well

According to one aspect of the invention, CMOS FETs comprise gate electrodes each having a polysilicon layer implanted with at least p-type impurities.

According to another aspect of the present invention, a method of manufacturing a CMOS FET includes a device isolation film / well forming step of forming a device isolation film and a well on a silicon substrate, and forming a polysilicon layer that becomes a part of gate electrodes on the device isolation film and the well. And a boron injection step of injecting a p-type impurity onto the substrate on which the polysilicon layer is formed. An embodiment of this method is shown in FIGS. 9A-9C.

According to another aspect of the present invention, a three-dimensional CMOS FET is formed on the first nMOS FET and the first pMOS FET each having a gate electrode containing a p-type impurity implanted in a polysilicon layer, and formed on the first nMOS FET A second pMOS FET and a second nMOS FET formed over the first pMOS FET, wherein an n ⁻ diffusion layer of the first nMOS FET is interconnected with a p ⁺ diffusion layer of the second pMOS FET and is connected to the first pMOS FET The p ⁺ diffusion layer of is interconnected with the n ⁻ diffusion layer of the second nMOS FET. An embodiment of this three-dimensional CMOS FET is shown in FIG.

According to another aspect of the present invention, a three-dimensional CMOS FET manufacturing method is a first forming step for forming a first nMOS FET and a first pMOS FET each gate electrode containing a p-type impurity implanted in a polysilicon layer And a deposition step of depositing an insulating film over the entire structure formed in the first forming step, and forming a second pMOS FET on the first nMOS FET formed in the first forming step and forming the first pMOS FET in the first forming step. Forming a second nMOS FET thereon, and interconnecting an n ⁻ diffusion layer of the first nMOS FET with a p ⁺ diffusion layer of the second pMOS FET and connecting a p ⁺ diffusion layer of the first pMOS FET; An interconnect step of interconnecting the n ⁻ diffusion layer of the 2 nMOS FET.

The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

First embodiment

A CMOS FET according to a first embodiment of the present invention will be described with reference to the accompanying drawings. 8 is a sectional view of a CMOS FET according to a first embodiment of the present invention. It is assumed that the CMOS FET shown in Fig. 8 is manufactured based on the design rule of 0.25 or less.

As shown in FIG. 8, the CMOS FET according to the embodiment of the present invention includes an buried channel type nMOS region 121 and a surface channel type pMOS region 123. Two p ⁺ diffusion layers 105, two n ⁻ diffusion layers 117, and an isolation layer (SiO ₂ ) 113, which is an isolation layer, are all formed on the silicon (Si) substrate 100. The P ⁺ diffusion layer 105 and the n ⁻ diffusion layer 117 become source and drain regions of the pMOS FET and source and drain regions of the nMOS FET, respectively.

In addition, silicon dioxide films 115 are formed on the silicon substrate 100 to be gate oxide films, respectively. Gate electrodes 141 and gate electrodes 143 are formed on the silicon dioxide films 115.

The gate electrode 141 includes a polysilicon layer 119, a titanium nitride (TiN) layer 109, and a tungsten (WSi ₂ ) layer 131. A dopant such as boron is injected into the polysilicon layer 119, for example, and the layer 119 is of p-type polarity.

The gate electrode 143 is composed of a polysilicon layer 107, a titanium nitride layer 109, and a tungsten (WSi ₂ ) layer 133. For example, a dopant such as boron is injected into the polysilicon layer 107, and the layer 107 becomes a p-type polarity.

The preferred concentration of the boron implant to be injected into the above-described gate electrode (141 143) is approximately more than 5 × 1019㎝ ^-3 or 1 × 1021㎝ ^-3 or less.

In summary, the CMOS FET according to the first embodiment of the present invention shown in FIG. 8 is formed based on a design rule of 0.25 μm or less, and includes an nMOS FET including the respective polysilicon layers 119 and 107 as the gate electrode portion. 121 and the pMOS FET 123 are combined, and boron injection is injected into the polysilicon layers of the gate electrodes.

Next, a method for manufacturing a CMOS FET according to the present invention will be described with reference to FIGS. 9A to 9C.

9A to 9C show the steps of the process sequence for manufacturing a CMOS FET according to the embodiment of the present invention shown in FIG.

9A to 9C, in the method of manufacturing a CMOS FET according to the present invention, it is designed based on a design rule of 0.25 탆 or less, and has a polysilicon layer as part of a gate electrode, and initially an element isolation film. (SiO ₂ ) 113 and wells 500 and 501 are formed. Here, the wells 500 and 501 are p-type and n-type, respectively. Next, a gate dioxide film (SiO ₂ ) 115 as a gate oxide film and a polysilicon film 151 as part of the gate electrode are formed, and then boron is implanted into the entire surface of the substrate 100 (see FIG. 9A).

A barrier layer 163, such as a titanium nitride (TiN) layer, and a silicide layer 161, such as a tungsten (WSi ₂ ) layer, are formed in this order (see FIG. 9B).

Next, the formed layers are patterned to form gate electrodes 141 and 143. Source and drain regions are formed in the n ⁻ diffusion layer 117 and the P ⁺ diffusion layer 105. Next, a transistor is formed by performing heat treatment for impurity activation (see Fig. 9C).

The manufacturing method mentioned above is demonstrated in more detail. As shown in FIG. 9A, in a CMOS FET having a polyside gate electrode, a well 500 is formed in a buried channel type nMOS FET, while a well 501 is formed in a surface channel type pMOS FET.

Next, the CMOS FET is manufactured by dispersing impurities having a large diffusion coefficient such as boron in the polysilicon layers of the gate electrodes of the nMOS FET and the pMOS FET, so that the gate electrode is made P-type. In the manufacturing method shown in FIGS. 9A to 9C, since only one type of impurities injected into the gate electrode is used, the resist process may be omitted.

Next, the operation of the CMOS FET of FIG. 8 will be described with reference to FIGS. 10A and 10B. FIG. 10A illustrates a relationship between an output voltage and a drain current of the CMOS FET of FIG. 8, and FIG. 10B illustrates a relationship between an input voltage, an output voltage, and a through current. The definition of output voltage, input voltage, and through current is the same as defined in FIG.

When the previous design rule is used, the gate oxide film is thick, and boron injection does not occur. Thus, the nMOS FET and pMOS FET operate as shown by the solid line in FIG. 10A. The through current is shown by the solid line in FIG. 10B.

On the other hand, according to the design rule based on 0.25 mu m or less, the gate oxide film is thin (6 nm or less). In this case, boron implantation occurs. Since the gate electrodes of the nMOS FET and the pMOS FET of the present invention both contain boron implantation, boron implantation occurs in these transistors. This changes the output voltage-drain current relationship as shown by the dotted line in Fig. 10A, and the through current is changed as shown by the dotted line in Fig. 10B.

In other words, according to the CMOS FET of the embodiment of the present invention of Fig. 8, even though the boron implantation occurs, the increase in the penetration current can be controlled. This is due to the fact that both thresholds of the nMOS FET and pMOS FET change at the same time (see the on-state characteristics of each pMOS FET and nMOS FET shown in Figure 10a).

In addition, according to the CMOS FET manufacturing method according to the present invention described above, only one type (boron) is used for the gate electrodes of the nMOS FET and the pMOS FET. Therefore, only boron is needed as an impurity injected into the gate electrode. This reduces the two-step resist use process in the process sequence used in the dual gate CMOS FET of FIG. 4, simplifying the manufacturing process.

The present invention is not limited to the structure of the above-described embodiment, and various changes and modifications are possible within the spirit and the gist of the present invention.

In particular, according to the present invention, the gate electrode includes respective polysilicon layers on the gate insulating film, and p-type impurities (boron) are distributed in the polysilicon layer. Thus, the structure formed on or on the polysilicon layer may be made of a tungsten (WSi ₂ ) layer, a titanium silicide layer, a titanium nitride (TiN) layer, or other related materials.

Second embodiment

In the above, the two-dimensional CMOS FET and the method of manufacturing the same according to the present invention have been described with reference to FIGS. 8, 9A to 9C, 10A and 10B, and FIG. 11. Here, a three-dimensional CMOS FET according to a second embodiment of the present invention using a two-dimensional CMOS FET will be described with reference to FIG. 12 is a process cross-sectional view showing the shape of the three-dimensional CMOS FET according to the second embodiment of the present invention.

In Fig. 12, the same elements as those in Fig. 8 are denoted by the same reference numerals.

In FIG. 12, the structure including the nMOS region 121 and the pMOS region 123 on the silicon substrate 100 is the same as that of FIG. 8, and the nMOS region 121 in FIG. 12 is a polysilicon layer 119. , A gate electrode 141 including a titanium nitride (TiN) layer 109, a tungsten (WSi ₂ ) layer 131, a gate dioxide film (SiO ₂ ) 115, a p-type well 500, and n ⁻ The pMOS region 123 is formed of a diffusion layer 117, and includes a polysilicon layer 107, a titanium nitride (TiN) layer 109, a tungsten (WSi ₂ ) layer 133, and a gate dioxide layer (SiO ₂ ) 115. And a gate electrode 143, an n-type well 501, and a p ⁻ diffusion layer 105. Dopants such as boron are injected into the polysilicon layers 119 and 107 to form a p-type. This structure is manufactured according to the process sequence shown in Figs. 9A to 9C.

After this structure is fabricated, a PSG (phosphor-silicate glass) layer 740 or other insulator is deposited on the front. On this layer, a pMOS region 770 and an nMOS region 771 are formed over the nMOS region 121 and the pMOS region 123, respectively. The pMOS region 770 is formed of a silicon nitride film 720 or other insulator, a P ⁺ diffusion layer 717 and an n ⁻ diffusion layer 791, and a gate electrode 741. The gate electrode 741 is formed of a polysilicon layer 719, a titanium nitride (TiN) layer 709, a tungsten (WSi ₂ ) layer 731, and a gate dioxide film (SiO ₂ ) 715. The nMOS region 771 is formed of a silicon nitride film 721 or other insulator, an n ⁻ diffusion layer 705 and a P ⁺ diffusion layer 780, and a gate electrode 743. Here, the gate electrode 743 is formed of a polysilicon layer 707, a titanium nitride (TiN) layer 709, a tungsten (WSi ₂ ) layer 733, and a gate dioxide film (SiO ₂ ) 715. Dopants such as boron are implanted into the polysilicon layers 719 and 707 to form a p-type.

As is apparent from the structure of Fig. 12, the structures of the gate electrodes 741 and 743 are the same as the gate electrodes 141 and 143. Therefore, in order to manufacture the gate electrodes 741 and 743, the same process steps as those shown in FIGS. 9A to 9C may be used.

The drain of the nMOS region 121 (one of the n ⁺ diffusion layers 117) and the source of the pMOS region 770 (one of the P ⁺ diffusion layers 717) are interconnected with each other with aluminum wiring or other metal wiring, The drain of the nMOS region 771 (one of the n ⁺ diffusion layers 705) and the source of the pMOS region 123 (one of the P ⁺ diffusion layers 105) are interconnected with each other by aluminum wiring or other metal wiring. The source of the nMOS region 121 (the other one of the n ⁺ diffusion layers 117), the drain of the pMOS region 770 (the other one of the P ⁺ diffusion layers 717), and the source (n ⁺ of the nMOS region 771). The other one of the diffusion layers 705), and the drain of the pMOS region 123 (one of the P ⁺ diffusion layers 105) are each made of other elements (not shown) manufactured on the same substrate 100, and each aluminum wiring. Or independently interconnected via other metallization. In the above-described manner, the nMOS region 121 and the pMOS region 770 form one CMOS element. The pMOS region 123 and nMOS region 771 also form another CMOS element.

In the manufacturing process of the three-dimensional CMOS device according to the second embodiment of the present invention, since the heat treatment performed to manufacture the upper transistor causes the occurrence of the above-described short channel effect through which boron injection penetrates more seriously, The three-dimensional CMOS FET and its manufacturing method solve this problem.

Although the present invention has been described with reference to preferred embodiments, it is clear that features included in the present invention are not limited to the specific embodiments. On the contrary, the invention includes all changes, modifications, and equivalents within the spirit and scope of the appended claims.

As described above, it is clear that according to the present invention, the following advantageous effects are provided.

The first effect is that a CMOS FET with reduced power consumption and a method of manufacturing the same are provided. This is because even though boron implantation is penetrated in the nM0S FET and the pMOS FET of the CMOS FET, the thresholds of the nMOS FET and the pMOS FET simultaneously change in almost the same manner.

In other words, controlling the through current of the CMOS FET can reduce power consumption. In particular, since the transistor manufactured according to the design rule of 0.25 mu m has a thin gate oxide film of 6 nm or less, penetration of boron injection easily occurs. Therefore, according to the present invention, the reduction in power consumption of the CMOS FET is significantly larger than that of conventional transistors.

For example, according to the conventional dual gate type CMOS FET (pn type gate) of Fig. 4, the penetration of boron injection changes the impurity concentration in the silicon substrate. This changes the threshold of the pMOS FET only (see Figure 6a) and allows a large through current to flow (see Figure 6b).

On the other hand, according to the CMOS FET according to the present invention, as shown in Fig. 8, since the p-type impurities such as boron are injected into the nMOS FET and the pMOS FET, boron injection easily occurs in both transistors. In addition, since the thresholds of the nMOS FET and the pMOS FET change in the same manner (see FIG. 10A), the through current of the CMOS FET can be controlled as well as the power consumption can be reduced (see FIG. 10B).

The second effect is that a CMOS FET having a large driving ability to drive another CMOS FET at high speed and a method of manufacturing the same are provided. This suggests that since boron has a high diffusion coefficient, the gate electrode of the nMOS FET can contain boron implantation uniformly, and the channel of the nMOS FET is embedded in the substrate (see FIG. 11), giving the CMOS FET high carrier mobility. It comes from the facts.

On the contrary, according to the conventional dual gate type (pn type gate) CMOS FET shown in FIG. 4 which controls the short channel effect of a transistor manufactured based on a design rule of 0.25 μm or less, impurities of the polysilicon layer of the gate electrode are used. Since the diffusion coefficients of phosphorus and boron used are different, it is difficult to control the occurrence of depletion of the gates of the transistor.

According to the present invention, since impurities having a high diffusion coefficient such as boron are used for the gate electrodes of the nMOS FET and the pMOS FET (see Fig. 8), it is easy to sufficiently suppress the depletion of the gate electrode.

With this shape, boron injection can allow penetration. According to the present invention, since the nMOS FET is a buried channel type, the current driving capability is high. This is advantageous when manufacturing a CMOS FET that operates at high speed.

A third effect is to provide a CMOS FET and a method of manufacturing the same, in which the impurity polarities of the gate electrodes of the nMOS FET and the pMOS FET are the same, so that interdiffusion of impurities in the gate electrodes of the nMOS FET and the pMOS FET does not occur. See Figure 8)

This is due to the fact that even if impurities of the same polarity are mixed, they are not neutralized with each other and no interdiffusion occurs.

The fourth effect is that a CMOS FET is provided that can be easily manufactured through a simple manufacturing process. This is because the impurity used for the gate electrodes of the nMOS FET and the pMOS FET is only one kind of impurity such as boron, so that at least, the two-step process using the resist can be reduced in the entire process for manufacturing the dual-gate CMOS FET. It comes from the fact that there is.

In general, the conventional CMOS FET uses a dual gate (pn-type gate) to control the occurrence of a short channel effect of a transistor manufactured based on a design rule of 0.25 mu m or less. (See FIG. 4) A polyside gate is used. In addition to the step of injecting impurities into the source and the drain, a separate step of injecting impurities into the gate electrode is required. As a result, two separate processes using a resist are required (see FIGS. 7A to 7F). On the other hand, according to the present invention, since a pp-type gate is used and boron injection is performed to the entire gate electrode, a resist is used. It is unnecessary to make a step. (See FIGS. 9A to 9C.)

The fifth effect relates to the control of the short channel effect. The CMOS FET according to the present invention includes a buried channel type nMOS FET. However, since acenic (As) or phosphorus (P) is used as an impurity to be injected into the diffusion regions of the source and the drain, the control of the profile can be easily performed, so that the occurrence of the short channel effect can be suppressed.

Here, the profile control indicates that the profile control is formed in a shape necessary for the distribution profile of the impurities injected into the source and the drain. In the case where a substance such as an Asic or Phosphorus is used, the profile is easy because the mass is heavy and difficult to diffuse.

Since the impurity used in the diffusion layer of the nMOS FET is either cyclic or phosphorous, an elaborate source and drain are formed.

On the other hand, the impurity used in the diffusion layer of the pMOS FET is boron, and its mass is light and diffuses in the horizontal direction and the depth direction by heat treatment, thereby forming a wide source and drain.

In order to suppress the occurrence of the short channel effect, a low junction depth between the source and the drain and a sufficiently long space between the source and the drain are necessary. Therefore, using boron implantation to control the occurrence of the short channel effect of the pMOS FET is more difficult than the same in the nMOS FET.

However, according to the present invention, since the pMOS FET is a surface channel type, it is easy to control the occurrence of the short channel effect. However, in the conventional CMOS FET having a transistor manufactured based on a design rule of 0.25 mu m or less, as shown in FIG. 4, a pn type gate is used to control the occurrence of a short channel effect. Penetration of p-type impurities changes the threshold voltage of the pMOS FET and increases the penetration current. This makes it impossible to reduce the power consumption.

According to the CMOS FET according to the present invention, the nMOS FET is of p-type polarity, buried channel type, and the pMOS FET is of p-type polarity and surface channel type (see Fig. 8).

In summary, according to the CMOS FET according to the present invention, since an impurity used in the source and drain regions of the nMOS FET is an acenic or phosphorous having a large mass, a small diffusion coefficient, and easy to control, a buried channel nMOS FET is used. Even the short channel effect can be sufficiently controlled. Moreover, since the pMOS FET of the CMOS FET according to the present invention is a surface channel type, the generation of the short channel effect is sufficiently controlled. In addition, since penetration occurs in both transistors, the change in the threshold voltage of each transistor is similar to each other, and the penetration current is sufficiently controlled. This reduces the power consumption.

Claims (19)

In a Complementary Metal Oxide Semiconductor Field-Effect Transistor (CMOS FET) with an nMOS FET and a pMOS FET: And a p-type impurity in both gate electrodes of the nMOS FET and the pMOS FET. 2. The CMOS FET according to claim 1, wherein each gate electrode has a polysilicon layer implanted with at least p-type impurities. The CMOS FET according to claim 1, wherein the p-type impurity is boron. According to claim 1, CMOS FET, characterized in that allowed the concentration of the p-type impurity is either more than or less 5 × 1019㎝ ^-3 1 × 1021㎝ ^-3. The CMOS FET according to claim 1, wherein the CMOS FET is designed according to a design rule of 0.25 mu m or less. The CMOS FET according to claim 1, wherein the gate electrodes of the nMOS FET and the pMOS FET include at least one of a tungsten layer, a titanium silicide layer, and a titanium nitride filling. 2. The CMOS FET according to claim 1, wherein an impurity having a heavy mass and a low diffusion coefficient is implanted into the source and drain regions of the nMOS FET. 8. The CMOS FET of claim 7, wherein the impurity is one of phosphorus or arsenic. In a method of manufacturing a CMOS FET consisting of an nMOS FET and a pMOS FET: An isolation layer / well forming step of forming an isolation layer and a well on the silicon substrate; Forming a polysilicon layer on the device isolation layer and the well, the polysilicon layer forming a portion of the gate electrodes; And And implanting a p-type impurity onto the substrate on which the polysilicon layer is formed. 10. The method of claim 9 wherein the p-type impurity is boron. 10. The method of claim 9, further comprising a barrier layer forming step of forming a barrier layer of titanium nitride (TiN) on the substrate implanted with the p-type impurity. 12. The method of claim 11, further comprising a silicide layer forming step of forming a silicide layer of tungsten on the barrier layer. The method of claim 12, further comprising a gate electrode patterning step of patterning the silicide layer, the barrier layer, and the polysilicon layer in which the p-type impurity is implanted into the gate electrodes. Way. 13. The method of claim 12, further comprising a source and a drain forming a source and a drain in the substrate by implanting impurities having a heavy mass and a low diffusion coefficient. 15. The method of claim 14 wherein the impurity having a high mass and low diffusion coefficient is one of phosphorus or arsenic. 15. The method of claim 14, further comprising a heat treatment step of performing a heat treatment for activating the impurity. In a three-dimensional CMOS FET consisting of an nMOS FET and a pMOS FET: A first nMOS FET and a first pMOS FET each having a gate electrode containing a p-type impurity implanted in a polysilicon layer; A second pMOS FET formed over said first nMOS FET; And And a second nMOS FET formed over the first pMOS FET, Wherein 1 n of the nMOS FET ^- diffusion layer and the second interconnection and a p ⁺ diffusion layer of the pMOS FET and the p ⁺ diffusion layer n of the second nMOS FET of the first 1 pMOS FET ^- 3, which are mutually connected to the diffusion layer D CMOS FET . In the method of manufacturing a three-dimensional CMOS FET consisting of an nMOS FET and a pMOS FET: A first forming step for forming a first nMOS FET and a first pMOS FET each gate electrode containing a p-type impurity implanted in a polysilicon layer; A deposition step of depositing an insulating film on the entire structure formed in the first forming step; Forming a second pMOS FET on the first nMOS FET formed in the first forming step and forming a second nMOS FET on the first pMOS FET formed in the first forming step; And A p ⁺ diffusion layers with each other in the first 2 pMOS FET diffusion connection, and n of the p ⁺ diffusion layer of the first 1 pMOS FET wherein the 2 nMOS FET ^{- -} wherein 1 n of the nMOS FET interconnection step of interconnecting diffusion layer and 3D CMOS FET manufacturing method provided. 19. The method of claim 18, wherein each of the second nMOS FETs and the second pMOS FETs comprises individual gate electrodes each including a polysilicon layer implanted with p-type impurities.