KR19990081582A - Double damascene technology - Google Patents

Abstract

The present invention relates to a dual damascene technique, in which photoresist layers are first formed in predetermined regions of the narrower and wider opening of the dual damascene, respectively. Two combination films consisting of an HSQ layer and an oxide film thereon are formed around the first and second photoresist layers, respectively. After the photoresist layers are removed, the remaining opening is filled by the barrier / glue layer and the metal. By the manufacturing method of such a semiconductor device, the etching damage according to the conventional dual damascene technology can be prevented, and the surface of the photoresist layer is flat, thereby reducing the critical dimension variation, and the deep sub-micron process and the multi-layer interconnection. Can be applied to the connection. In addition, the width of the contact window to the via can be kept constant with high reliability without any misalignment problem.

Description

DUAL DAMASCENE TECHNIQUE

The present invention relates to a dual damascene technique, and more particularly, to a dual damascene technique using ultraviolet-violate ray to bake a photoresist layer. This dual damascene technique can be successfully applied to sub-micron integrated circuits.

Increasing the degree of integration of integrated circuits causes a lack of surface of the chip to form interconnects. As the size of devices decreases, multilayer interconnect designs are required for IC processes in order to meet more wiring lines requirements. Multilayer interconnection is a three-dimensional wiring structure. In order to form a multi-layer interconnect structure, first to lower layers of metal wirings connected to the source / drain regions of a metal-oxide semiconductor transistor (MOS) on a semiconductor substrate are first formed, and then the first metal wirings. And a second layer of metal wiring is formed. The metal wires are formed of a conductive material such as metal to polysilicon. If necessary, two or more layers of metal wirings are formed.

However, for IC devices having a sub submicron size, the conventional dual damascene technique is not satisfactory. For example, copper, a filling material for forming contact plugs, is difficult to etch during the etch back process, and also difficult to select an appropriate etchant. In addition, poor step coverage during the metal deposition process in the plug or during the deposition of the insulating layer between the metal wires causes void formation and impurity trapping. Therefore, a conventional dual damascene technique has been proposed that avoids the defects caused by the shrinkage of the IC element and also forms a flat insulating layer surface.

The most commonly used dual damascene technique involves the use of chemical mechanical polishing (CMP) during patterning. The CMP provides a wide choice of wiring metals, such as aluminum, copper, and aluminum alloys, thus meeting low resistance and low electromigration requirements. As a result, the technique is generally used in processes for VLSIs of 0.25 μm or less.

1A-1D are process flow diagrams of a conventional dual damascene technique. First, referring to FIG. 1A, an oxide film, which is an interlayer insulating film 12, is deposited on a substrate 10. Next, the interlayer insulating layer 12 is patterned to form a wide opening 14 on the substrate 10.

In FIG. 1B, the lower portion of the wide opening 14 is further patterned and etched to form a narrower opening that exposes the semiconductor substrate 10.

Referring to FIG. 1C, metal 18 is filled in opening 16 and opening 14.

In FIG. 1D, an etch back or CMP technique for polishing the metal 18 is performed such that the surface of the interlayer insulating film 12 is exposed, such that the surface of the metal 18 is the same as one of the interlayer insulating films 12. It becomes a level.

However, the conventional dual damascene technique has at least the following problems.

First, both the opening 14 and the opening 16 are etched by dry etching, resulting in severe plasma damage.

Secondly, since rugged terrain occurs in the preceding dry etching step to form a wider opening, in the patterning step to form a narrower opening, critical dimension variation becomes large.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a dual damascene process that can overcome the drawbacks of the conventional dual damascene technique.

Another object of the present invention is to provide a dual damascene technique which is advantageous in metal interconnect processes.

It is another object of the present invention to provide a dual damascene technique suitable for sub-micron sub-micron processes.

Another object of the present invention is to reduce the misalignment problem, and to provide a dual damascene technique that does not have a problem due to the etching process.

1A-1D are cross-sectional views illustrating the process flow of a conventional dual damascene technique;

2A-2F are cross-sectional views illustrating the process flow of the dual damascene technique in accordance with a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 20: semiconductor substrate 12: interlayer insulating film

14, 16, 42: opening 18, 40: metal layer

21: field structure 22: MOSFET

24: source / drain 26, 32: photoresist film

28, 34: HSQ layer 30: silicon oxide film

31, 37: combination film 38: barrier / glue layer

(Configuration)

According to the present invention for achieving the above object, the dual damascene technique comprises the steps of preparing a semiconductor substrate having a region required to be in contact with a preformed wiring; Forming a first photoresist layer having a first pattern, ultimately contacting the region; Forming a first insulating layer that is flat and has a surface at approximately the same level as the first photoresist layer; Forming a second photoresist layer having a second pattern, wherein the second photoresist layer is ultimately in contact with the first photoresist layer and formed wider than the first pattern in cross section; Forming a second insulating layer that is flat and has a surface at approximately the same level as the second photoresist layer; Removing the first photoresist layer and the second photoresist layer to form an opening; Filling the opening with metal.

In a preferred embodiment of the method, after forming the first photoresist layer, a deep ultraviolet bake step may be further performed.

In a preferred embodiment of this method, after the second photoresist layer forming step, a deep ultraviolet bake step may be further performed.

In a preferred embodiment of the method, a barrier / glue layer may be further formed to cover the periphery and the bottom of the opening prior to the metal peeling step.

(Action)

Referring to FIG. 2E, in the novel dual damascene technique according to the embodiment of the present invention, photoresist layers are first formed in predetermined regions of narrower opening and wider opening of the dual damascene, respectively. Two combination films consisting of an HSQ film and an oxide film are formed around the first and second photoresist layers, respectively. After the photoresist layers are removed, the remaining opening is filled with the barrier / glue layer and the metal. By the manufacturing method of such a semiconductor device, the etching damage according to the conventional dual damascene technology can be prevented, and the surface of the photoresist layer is flat, thereby reducing the critical dimension variation, and the deep sub-micron process and the multi-layer interconnection. Can be applied to the connection. In addition, the width of the contact window to the via can be kept constant with high reliability without any misalignment problem.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A-2F are cross-sectional views illustrating the process flow of the dual damascene technique in accordance with a preferred embodiment of the present invention.

Referring to FIG. 2A, a semiconductor device is first formed on a semiconductor substrate 20. The semiconductor device may be a metal-oxide semiconductor field effect transistor (MOSFET) 22 formed in an active region isolated by a field structure 21, such as a shallow trench isolation structure. The MOSFET 22 includes source / drain regions 24.

In FIG. 2B, a photoresist film 26 having a desired narrower opening pattern is formed to ultimately connect with the source / drain regions 24. Preferably a deep ultraviolet bake process is performed. Next, a hydrogen silsesquioxane (HSQ) layer 28 is spin coated to cover at least the MOSFET 22.

Next, referring to FIG. 2C, a silicon oxide film 30 is preferably formed by chemical vapor deposition (CVD) so as to cover at least the HSQ layer 28 and the photoresist layer 26. Next, the silicon oxide film 30 is polished with CMP to remove part of the silicon oxide film 30 until at least the top surface of the photoresist layer 26 is exposed, so that the top surface of the silicon oxide film 30 The level is almost the same as the top surface of the resist layer 26. As a result, the combination film 31 including the silicon oxide film 30 and the HSQ film 28 is formed. The combination film 31, which is designed to withstand continuous processes, has the following excellent properties such as low RC time delay, water proof, and high density. . The good properties of the combination film 31 are, in part, the result of the fact that the HSQ layer 28 has a low insulation constant of about 2.6, which eliminates the relatively RC time delay problem. In addition, the silicon oxide film 30 makes the combination film 31 dense and waterproof, thereby overcoming the sparse and water-adsorbable problem of the HSQ layer 28.

In FIG. 2D, a photoresist layer 26 having a desired wider opening pattern is preferably formed in contact with the photoresist layer 26. Preferably a deeper ultraviolet bake process is performed. Subsequently, an HSQ layer 34 is spin coated on at least the silicon oxide film 30.

Next, referring to FIG. 2E, a silicon oxide film 36 is preferably formed by CVD to cover at least the HSQ layer 34 and the photoresist layer 32. The silicon oxide film 36 is polished with CMP to remove a portion of the silicon oxide film 36 until at least the top surface of the photoresist layer 32 is exposed. As a result, the upper surface of the silicon oxide film 36 is approximately at the same level as the upper surface of the photoresist layer 32. Thus, the combination film 37 including the silicon oxide film 36 and the HSQ layer 34 is formed. The combination film 37 designed to withstand continuous processes has the following excellent properties such as low RC time delay, water proof, and high density.

In FIG. 2F, the photoresist layer 32 and the photoresist layer 26 are preferably removed in turn in an ashing process to form a double damascene opening 42. In addition, a barrier / glue layer 38 is formed by the CVD method so as to cover at least the periphery and the bottom of the opening 42. The configuration of the barrier / glue layer 38 is, for example, Ti / TiN. A metal layer 40 is deposited to cover the barrier / glue layer 38 and the metal layer 40 and to fill the opening 42. The material of the metal layer 40 preferably comprises copper to tungsten. The metal layer 40 is etched back to be approximately equal to the top surface of the metal layer 40 and the level of the silicon oxide film 36.

The invention is not limited to two layer metalization, but may be applied to multi-level interconnections. For example, it can be applied to a three layer metal process by similar processes as described above.

Although the present invention has been described in accordance with the embodiments as described above, the present invention is not limited thereto, and includes various modifications and similar apparatus and steps, and additional claims. The present invention conforms to the broadest interpretation so as to encompass all modifications and similar arrangements and steps.

The present invention allows the photoresist layers to be first formed in certain areas of narrower openings and wider openings to prevent etch damage according to conventional dual damascene techniques.

Since the surface on which the photoresist layer is formed is flat, the critical dimension variation can be reduced. Thus, the present invention is suitable for deep submicron processes.

The dual damascene technique according to the present invention can be applied to multilayer interconnections.

The width of contact windows to vias can be kept constant with high reliability without misalignment problems.

Claims (14)

Preparing a semiconductor substrate having a region required to be in contact with a preformed wiring; Forming a first photoresist layer having a first pattern, ultimately contacting the region; Forming a first insulating layer that is flat and has a surface at approximately the same level as the first photoresist layer; Forming a second photoresist layer having a second pattern, wherein the second photoresist layer is ultimately in contact with the first photoresist layer and formed wider than the first pattern in cross section; Forming a second insulating layer that is flat and has a surface at approximately the same level as the second photoresist layer; Removing the first photoresist layer and the second photoresist layer to form an opening; A dual damascene technique comprising the step of filling the opening with a metal. The method of claim 1, After forming the first photoresist layer, a deep damascene technique is further performed a deep ultraviolet bake step. The method of claim 1, The dual damascene technique, further comprising a deep ultraviolet bake step, after the second photoresist layer forming step. The method of claim 1, Wherein the first insulating layer comprises an HSQ layer and a silicon oxide film formed on the HSQ layer. The method of claim 1, Wherein the second insulating layer comprises an HSQ layer and a silicon oxide film formed on the HSQ layer. The method of claim 1, A dual damascene technique in which a barrier / glue layer is further formed to cover the periphery and bottom of the opening prior to the metal peeling step. The method of claim 1, Wherein the region required to be connected to the wiring is any one of source / drain regions. The method of claim 4, wherein Wherein said HSQ layer is formed by spin coating. The method of claim 5, Wherein said HSQ layer is formed by spin coating. The method of claim 4, wherein Wherein said silicon oxide film is formed by CVD and CMP. The method of claim 5, Wherein said silicon oxide film is formed by CVD and CMP. The method of claim 6, Wherein said barrier / glue layer is a Ti / TiN layer. The method of claim 1, Wherein said metal comprises copper. The method of claim 1, Wherein said metal comprises tungsten.