KR19990081539A - Electrostatic Discharge Protection Semiconductor Devices - Google Patents
Electrostatic Discharge Protection Semiconductor Devices Download PDFInfo
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- KR19990081539A KR19990081539A KR1019980015554A KR19980015554A KR19990081539A KR 19990081539 A KR19990081539 A KR 19990081539A KR 1019980015554 A KR1019980015554 A KR 1019980015554A KR 19980015554 A KR19980015554 A KR 19980015554A KR 19990081539 A KR19990081539 A KR 19990081539A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- CFFOLZDPLGQDRA-UHFFFAOYSA-N S.I.I Chemical compound S.I.I CFFOLZDPLGQDRA-UHFFFAOYSA-N 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 9
- 230000003068 static effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 101100281521 Arabidopsis thaliana FOX4 gene Proteins 0.000 description 4
- 101100281522 Arabidopsis thaliana FOX5 gene Proteins 0.000 description 4
- 101100281515 Arabidopsis thaliana FOX1 gene Proteins 0.000 description 2
- 101100468517 Danio rerio rbfox1l gene Proteins 0.000 description 2
- 101150073947 RBFOX1 gene Proteins 0.000 description 2
- 102100038188 RNA binding protein fox-1 homolog 1 Human genes 0.000 description 2
- 101100161772 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) POX1 gene Proteins 0.000 description 2
- 210000003710 cerebral cortex Anatomy 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 정전방전보호용 반도체소자에 관한 것으로, 종래에는 접합항복을 통해 기생 트랜지스터를 턴온시키는 전압의 레벨이 높으므로, 방전패스의 형성이 늦어져 정전기 방전의 신뢰성이 저하되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 반도체기판 상에 형성된 절연산화막과; 상기 절연산화막 상에 소정거리 이격되어 형성된 제1,제2,제3필드산화막과; 상기 제1,제2필드산화막의 이격된 영역의 절연산화막 상에 수평방향의 피엔피엔 접합으로 형성되어 패드에 접속된 고농도의 제1피형 영역, 고농도의 제1엔형 영역, 고농도의 제2피형 영역 및 접지된 고농도의 제2엔형 영역과; 상기 제2,제3필드산화막과 소정거리씩 이격되어 절연산화막 상에 형성된 제3피형 영역과; 상기 제3피형 영역의 상부에 형성되어 접지된 게이트전극과; 상기 제3피형 영역과 제2,제3필드산화막의 이격된 영역의 절연산화막 상에 형성되어 액티브저항을 통해 패드에 접속됨과 아울러 폴리저항을 통해 입력버퍼에 접속된 고농도의 제3엔형 영역 및 접지된 고농도의 제4엔형 영역으로 구성되는 정전방전보호용 반도체소자를 통해 에스오아이 상에 턴온타임이 빠른 피엔피엔 접합 다이오드를 형성하여 정전기의 인가시 방전패스를 빠르게 형성할 수 있어 정전기 방전의 신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for electrostatic discharge protection. In the related art, since the level of the voltage for turning on the parasitic transistor through the junction breakdown is high, the formation of the discharge path is delayed and the reliability of the electrostatic discharge is lowered. In view of the above problems, the present invention provides an insulating oxide film formed on a semiconductor substrate; First, second and third field oxide films formed on the insulating oxide film and spaced apart from each other by a predetermined distance; A high density first skin region, a high concentration first N-type region, and a high concentration second skin formed on the insulating oxide film in the spaced apart region of the first and second field oxide films by a PPI connection in a horizontal direction and connected to the pad. A high concentration of the second yen type region and the ground; A third corrugated region spaced apart from the second and third field oxide films by a predetermined distance and formed on the insulating oxide film; A gate electrode formed on the third skinned region and grounded; A high concentration of the third Y-type region and the ground formed on the insulating oxide film in the spaced apart region of the third corrugated region and the second and third field oxide films and connected to the pad through an active resistor and connected to the input buffer through a poly resistor. Through the electrostatic discharge protection semiconductor device, which is composed of the high concentration of the fourth Yen-type region, a PNP-junction diode having a fast turn-on time is formed on the S.I.I. There is an effect that can be improved.
Description
본 발명은 정전방전보호용 반도체소자에 관한 것으로, 특히 에스오아이(silicon on insulator : SOI) 상에 턴온타임이 빠른 피엔피엔 접합 다이오드를 형성하여 정전기의 인가시 방전패스가 빠르게 형성되도록 한 정전방전보호용 반도체소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for electrostatic discharge protection, and in particular, for forming electrostatic discharge protection having a fast turn-on time on a piezoene junction diode on a silicon on insulator (SOI) so that a discharge path is formed upon application of static electricity. It relates to a semiconductor device.
종래 정전방전보호용 반도체소자를 도면을 참조하여 상세히 설명하면 다음과 같다.Referring to the conventional electrostatic discharge protection semiconductor device with reference to the drawings as follows.
도1은 종래 정전방전보호용 반도체소자의 구조를 보인 단면도로서, 이에 도시한 바와같이 피형 웰(1)상에 소정거리씩 이격되어 형성된 필드산화막(FOX1∼FOX5)과; 그 필드산화막(FOX1∼FOX4)의 이격된 영역의 피형 웰(1)상에 형성되어 접지된 고농도의 엔형 영역(N+1,N+3) 및 패드(10)에 접속된 고농도의 엔형 영역(N+2)과; 상기 필드산화막(FOX4,FOX5)의 이격된 영역의 피형 웰(1) 상부에 그 필드산화막(FOX4,FOX5)과 이격되도록 형성되어 접지된 게이트전극(2)과; 그 게이트전극(2)과 필드산화막(FOX4,FOX5)의 이격된 영역 사이의 피형 웰(1)상에 형성되어 액티브저항(R1)을 통해 패드(10)에 접속됨과 아울러 폴리저항(R2)을 통해 입력버퍼(20)에 접속된 고농도의 엔형 영역(N+4) 및 접지된 고농도의 엔형 영역(N+5)으로 이루어지며, 도2는 상기한 바와같은 종래 정전방전보호용 반도체소자의 레이아웃도이다. 미설명부호 'C'는 콘택이고, 'VC'는 비아(via)콘택이다.1 is a cross-sectional view showing the structure of a conventional electrostatic discharge protection semiconductor device, as shown in the field oxide films FOX1 to FOX5 spaced apart by a predetermined distance on the well 1; High concentration N-type regions N + 1, N + 3 formed on the wells 1 of the field oxide films FOX1 to FOX4 spaced apart from each other and grounded, and high concentration N-type regions connected to the pads 10 ( N + 2); A gate electrode (2) formed and spaced apart from the field oxide films (FOX4, FOX5) on the top of the well (1) in the spaced-apart area of the field oxide films (FOX4, FOX5); It is formed on the well 1 between the gate electrode 2 and the spaced areas of the field oxide films FOX4 and FOX5, and is connected to the pad 10 through the active resistor R1, and the poly resistor R2 is formed. It consists of a high concentration of the N-type region (N + 4) and grounded high concentration of the N-type region (N + 5) connected to the input buffer 20 through, Figure 2 is a layout of the conventional electrostatic discharge protection semiconductor device as described above to be. Unexplained symbol 'C' is a contact and 'VC' is a via contact.
그리고, 도3은 종래 정전방전보호용 반도체소자의 등가회로도로서, 이에 도시한 바와같이 패드(10)와 입력버퍼(20) 사이에 직렬접속된 액티브저항(R1) 및 폴리저항(R2)과; 일측이 패드(10)와 액티브저항(R1) 사이에 접속되고, 타측이 접지된 기생 트랜지스터(Q1)와; 드레인이 액티브저항(R1)과 폴리저항(R2) 사이에 접속되고, 게이트와 소스가 접지된 엔모스트랜지스터(Q2)로 구성된다.3 is an equivalent circuit diagram of a conventional electrostatic discharge protection semiconductor element, as shown in FIG. 3, wherein the active resistor R1 and the poly resistor R2 are connected in series between the pad 10 and the input buffer 20; A parasitic transistor Q1 having one side connected between the pad 10 and the active resistor R1 and the other side grounded; A drain is connected between the active resistor R1 and the poly resistor R2, and is composed of an enMOS transistor Q2 having a gate and a source grounded.
상기한 바와같이 구성되는 정전방전보호용 반도체소자의 패드(10)에 정전기가 인가되면, 그 정전기가 입력버퍼(20)에 인가되지 않도록 패드(10)로부터 접지로 방전패스가 형성되며, 이때 저항(R1,R2)은 내부 커패시터(미도시)와 더불어 입력버퍼(20)에 도달하는 정전기를 알씨(RC) 지연시켜 정전기가 방전패스를 통해 모두 방전되도록 한다. 그러나, 저항(R1,R2)의 저항값을 너무 크게하면 정상적인 동작에서 소자의 동작속도가 저하되므로, 적절한 고려가 필요하다.When static electricity is applied to the pad 10 of the electrostatic discharge protection semiconductor device configured as described above, a discharge path is formed from the pad 10 to the ground so that the static electricity is not applied to the input buffer 20, wherein the resistance ( R1 and R2, together with an internal capacitor (not shown), delay the static electricity (RC) from reaching the input buffer 20 so that the static electricity is discharged through the discharge path. However, if the resistance values of the resistors R1 and R2 are made too large, the operation speed of the device will be lowered in normal operation.
상술한 방전패스는 2개의 경로로 형성되는데, 첫 번째 경로는 기생 트랜지스터(Q1)가 턴온되어 전자가 패드(10)로부터 접지로 빠져나가는 것이고, 두 번째 경로는 엔모스트랜지스터(Q2)가 펀치쓰루(punch through)로 턴온되어 드레인으로부터 접지로 빠져나가는 것이다.The discharge path described above is formed of two paths, the first path of which the parasitic transistor Q1 is turned on to discharge electrons from the pad 10 to the ground, and the second path of the discharge path of the MOS transistor Q2 to punch-through. It is turned on by punch through and drains from drain to ground.
이와같은 방전패스는 첫 번째 경로인 기생 트랜지스터(Q1)가 접합항복(junction breakdown)을 통해 턴온되어 대부분의 정전기를 방전시키게 되지만, 그 기생 트랜지스터(Q1)의 접합항복이 발생하기 전에는 저항값이 매우 높은 상태이므로, 정전기의 일부가 액티브저항(R1)을 지나 주입될수 있으며, 이는 두 번째 경로인 엔모스트랜지스터(Q2)가 펀치쓰루로 턴온되어 방전시키게 된다.This discharge path causes parasitic transistor Q1, which is the first path, to be turned on through a junction breakdown to discharge most of the static electricity, but the resistance value is very high before the junction breakdown of the parasitic transistor Q1 occurs. Since the high state, a part of the static electricity can be injected through the active resistor (R1), which is the second path enMOS transistor (Q2) is turned on to punch through to discharge.
이때, 방전패스는 최대한 빠르게 형성되어 많은 양의 전류를 방전시킬 수 있어야 하며, 많은 양의 전류로 발생되는 열에너지에 파괴되지 않도록 설계되어야 한다.At this time, the discharge path should be formed as fast as possible to discharge a large amount of current, it should be designed so as not to be destroyed by the thermal energy generated by a large amount of current.
그러나, 상기한 바와같은 종래의 정전방전보호용 반도체소자는 접합항복을 통해 기생 트랜지스터를 턴온시키는 전압의 레벨이 높으므로, 방전패스의 형성이 늦어져 정전기 방전의 신뢰성이 저하되는 문제점이 있었다.However, the above-described conventional electrostatic discharge protection semiconductor device has a high level of voltage for turning on the parasitic transistor through the junction breakdown, and thus, the formation of the discharge path is delayed, thereby reducing the reliability of the electrostatic discharge.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 에스오아이(SOI) 상에 턴온타임이 빠른 피엔피엔 접합 다이오드를 형성하여 정전기의 인가시 방전패스를 빠르게 형성할 수 있는 정전방전보호용 반도체소자를 제공하는데 있다.The present invention was devised to solve the above problems, and an object of the present invention is to form a PNP junction diode having a fast turn-on time on an SOI to quickly form a discharge path upon application of static electricity. The present invention provides a semiconductor device for electrostatic discharge protection.
도1은 종래 정전방전보호용 반도체소자의 구조를 보인 단면도.1 is a cross-sectional view showing the structure of a conventional electrostatic discharge protection semiconductor device.
도2는 도1의 레이아웃도.2 is a layout diagram of FIG. 1;
도3은 도1의 등가회로도.3 is an equivalent circuit diagram of FIG.
도4는 본 발명의 일 실시예를 보인 단면도.Figure 4 is a cross-sectional view showing an embodiment of the present invention.
도5는 도4의 레이아웃도.5 is a layout diagram of FIG. 4;
도6은 도4의 등가회로도.6 is an equivalent circuit diagram of FIG.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
10:패드 20:입력버퍼10: pad 20: input buffer
11:반도체기판 12:절연산화막11: semiconductor substrate 12: insulating oxide film
13:게이트전극 FOX11∼FOX13:필드산화막13: gate electrode FOX11 to FOX13: field oxide film
P+11,P+12,P13:피형 영역 N+11∼N+14:엔형 영역P + 11, P + 12, P13: Cortical region N + 11 to N + 14: Yen region
R11,R12:액티브저항,폴리저항R11, R12: active resistance, poly resistance
상기한 바와같은 본 발명의 목적은 반도체기판 상에 형성된 절연산화막과; 상기 절연산화막 상에 소정거리 이격되어 형성된 제1,제2,제3필드산화막과; 상기 제1,제2필드산화막의 이격된 영역의 절연산화막 상에 수평방향의 피엔피엔 접합으로 형성되어 패드에 접속된 고농도의 제1피형 영역, 고농도의 제1엔형 영역, 고농도의 제2피형 영역 및 접지된 고농도의 제2엔형 영역과; 상기 제2,제3필드산화막과 소정거리씩 이격되어 절연산화막 상에 형성된 제3피형 영역과; 상기 제3피형 영역의 상부에 형성되어 접지된 게이트전극과; 상기 제3피형 영역과 제2,제3필드산화막의 이격된 영역의 절연산화막 상에 형성되어 액티브저항을 통해 패드에 접속됨과 아울러 폴리저항을 통해 입력버퍼에 접속된 고농도의 제3엔형 영역 및 접지된 고농도의 제4엔형 영역으로 구성함으로써 달성되는 것으로, 본 발명에 의한 정전방전보호용 반도체소자를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is an insulating oxide film formed on a semiconductor substrate; First, second and third field oxide films formed on the insulating oxide film and spaced apart from each other by a predetermined distance; A high density first skin region, a high concentration first N-type region, and a high concentration second skin formed on the insulating oxide film in the spaced apart region of the first and second field oxide films by a PPI connection in a horizontal direction and connected to the pad. A high concentration of the second yen type region and the ground; A third corrugated region spaced apart from the second and third field oxide films by a predetermined distance and formed on the insulating oxide film; A gate electrode formed on the third skinned region and grounded; A high concentration of the third Y-type region and the ground formed on the insulating oxide film in the spaced apart region of the third corrugated region and the second and third field oxide films and connected to the pad through an active resistor and connected to the input buffer through a poly resistor. This is achieved by configuring the high concentration fourth yen region, which will be described in detail with reference to the accompanying drawings for the electrostatic discharge protection semiconductor device according to the present invention.
도4는 본 발명의 일 실시예를 보인 단면도로서, 이에 도시한 바와같이 반도체기판(11) 상에 형성된 절연산화막(12)과; 그 절연산화막(12) 상에 소정거리 이격되어 형성된 필드산화막(FOX11∼FOX13)과; 그 필드산화막(FOX11,FOX12)의 이격된 영역의 절연산화막(12) 상에 수평방향의 피엔피엔 접합으로 형성되어 패드(10)에 접속된 고농도의 피형 영역(P+11), 고농도의 엔형 영역(N+11), 고농도의 피형 영역(P+12) 및 접지된 고농도의 엔형 영역(N+12)과; 상기 필드산화막(FOX12,FOX13)과 소정거리씩 이격되어 절연산화막(12) 상에 형성된 피형 영역(P13)과; 그 피형 영역(P13)의 상부에 형성되어 접지된 게이트전극(13)과; 상기 피형 영역(P13)과 필드산화막(FOX12,FOX13)의 이격된 영역의 절연산화막(12) 상에 형성되어 액티브저항(R11)을 통해 패드(10)에 접속됨과 아울러 폴리저항(R12)을 통해 입력버퍼(20)에 접속된 고농도의 엔형 영역(N+13) 및 접지된 고농도의 엔형 영역(N+14)으로 구성되며, 도5는 상기한 바와같은 본 발명에 의한 일 실시예의 레이아웃도이다.4 is a cross-sectional view showing an embodiment of the present invention, as shown therein, and an insulating oxide film 12 formed on the semiconductor substrate 11; Field oxide films FOX11 to FOX13 formed on the insulating oxide film 12 at a predetermined distance apart from each other; A high concentration of the p-type region (P + 11) connected to the pad 10 and formed of a high-density P-type 11 formed on the insulating oxide film 12 in the spaced-apart area of the field oxide films FOX11 and FOX12 connected to the pad 10 A region N + 11, a high concentration of the covered region P + 12 and a grounded high concentration of the N-type region N + 12; A shaped region P13 formed on the insulating oxide film 12 spaced apart from the field oxide films FOX12 and FOX13 by a predetermined distance; A gate electrode 13 formed on the top of the shaped region P13 and grounded; It is formed on the insulating oxide film 12 in the spaced apart region of the corrugated region P13 and the field oxide films FOX12 and FOX13, and is connected to the pad 10 through an active resistor R11 and through a poly resistor R12. Consists of a high concentration N-type region (N + 13) and a grounded high concentration N-type region (N + 14) connected to the input buffer 20, Figure 5 is a layout diagram of an embodiment according to the present invention as described above .
그리고, 도6은 본 발명에 의한 일 실시예의 등가회로도로서, 이에 도시한 바와같이 패드(10)와 입력버퍼(20) 사이에 직렬접속된 액티브저항(R11) 및 폴리저항(R12)과; 일측이 패드(10)와 액티브저항(R11) 사이에 접속되고, 타측이 접지된 피엔피엔 다이오드(PNPN-D11)와; 드레인이 액티브저항(R11)과 폴리저항(R12) 사이에 접속되고, 게이트와 소스가 접지된 엔모스트랜지스터(Q11)로 구성된다.6 is an equivalent circuit diagram of an embodiment according to the present invention, as shown therein; an active resistor R11 and a poly resistor R12 connected in series between the pad 10 and the input buffer 20; A PNP diode (PNPN-D11) having one side connected between the pad 10 and the active resistor R11 and the other side grounded; A drain is connected between the active resistor R11 and the poly resistor R12, and is constituted by an enMOS transistor Q11 having a gate and a source grounded.
상기한 바와같은 본 발명에 의한 정전방전보호용 반도체소자는 종래의 기생 트랜지스터(Q1) 대신에 피엔피엔 다이오드(PNPN-D11)를 접속하여, 기생 트랜지스터(Q1)보다 낮은 전압레벨에서 피엔피엔 다이오드(PNPN-D11)를 턴온시킬수 있으므로, 방전패스가 보다 빨리 형성될 수 있다.The electrostatic discharge protection semiconductor device according to the present invention as described above connects the PNP diode (PNPN-D11) instead of the parasitic transistor (Q1), the PNP diode at a lower voltage level than the parasitic transistor (Q1). Since the PNPN-D11 can be turned on, a discharge path can be formed faster.
한편, 패드(10)와 접지 사이에 피엔피엔 다이오드(PNPN-D11)를 역방향으로 추가하면, 패드(10)에 음(-)의 전압이 인가될 때에 접지로부터 패드(10)로 전자가 빠져나가는 경로가 형성된다.On the other hand, if the PNPN-D11 is added in the reverse direction between the pad 10 and the ground, electrons are drawn from the ground to the pad 10 when a negative voltage is applied to the pad 10. Outgoing paths are formed.
이와같은 경로는 상기 도4의 도면에 도시하지는 않았지만, 절연산화막(12) 상에 필드산화막(FOX11)과 소정거리 이격되는 제4필드산화막을 형성하고, 그 필드산화막(FOX11)과 제4필드산화막 사이의 절연산화막(12) 상에 수평방향의 엔피엔피 접합으로 형성되어 패드(10)에 접속된 고농도의 제5엔형 영역, 고농도의 제4피형 영역, 고농도의 제6엔형 영역 및 접지된 고농도의 제5피형 영역을 추가하여 형성한다.Although not shown in FIG. 4, such a path is formed on the insulating oxide film 12 to form a fourth field oxide film spaced apart from the field oxide film FOX11 by a predetermined distance, and the field oxide film FOX11 and the fourth field oxide film are formed. A high concentration of the fifth yen region, a high concentration of the fourth engraved region, the high concentration of the sixth yen region, and the grounding of the high concentration formed on the insulating oxide film 12 between the A fifth cortical region is added to form.
상기한 바와같은 본 발명에 의한 정전방전보호용 반도체소자는 에스오아이 상에 턴온타임이 빠른 피엔피엔 접합 다이오드를 형성하여 정전기의 인가시 방전패스를 빠르게 형성할 수 있어 정전기 방전의 신뢰성을 향상시킬 수 있는 효과가 있다.The semiconductor device for electrostatic discharge protection according to the present invention as described above can form a discharge path with fast turn-on time on the S.I.E. to quickly form a discharge path upon application of static electricity, thereby improving reliability of electrostatic discharge. It has an effect.
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| KR1019980015554A KR100289401B1 (en) | 1998-04-30 | 1998-04-30 | Semiconductor device for protecting electrostatic discharge |
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| KR100331540B1 (en) * | 2000-06-23 | 2002-04-06 | 김덕중 | MOS-type semiconductor device with electrostaticdischarge diode between gate and emitter |
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| KR100331540B1 (en) * | 2000-06-23 | 2002-04-06 | 김덕중 | MOS-type semiconductor device with electrostaticdischarge diode between gate and emitter |
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