KR19990081384A - Manufacturing method of electrostatic discharge input protection circuit of semiconductor device and layout of contact hole thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electrostatic discharge input protection circuit of a semiconductor device and a layout of a contact hole thereof, and more particularly to an impurity region for securing an input capacitance when manufacturing an ESD protection circuit used for a high speed DRAM of a semiconductor device. The present invention relates to a layout in which zigzag shapes are formed in such a way that the operation speed is improved by securing a low capacitance input capacitance, and the contact portion of the completed circuit is staggered with the contact hole of a neighboring active region.

According to the present invention, a first active region doped with a second conductivity type impurity ion and a second active region and a third active region are sequentially formed on the first conductive semiconductor substrate, and the first to third active regions are respectively positioned. Isolating by the separator, forming an insulating film on the surface of the first to third active regions, forming an ion implantation barrier on the surface of the second active region, and forming a first active region and a third active region. And forming a first conductivity type impurity diffusion layer in the lower adjacent portion of the region.

Description

Manufacturing method of electrostatic discharge input protection circuit of semiconductor device and layout of contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electrostatic discharge input protection circuit of a semiconductor device and a layout of a contact hole thereof, and more particularly to an impurity region for securing an input capacitance when manufacturing an ESD protection circuit used for a high speed DRAM of a semiconductor device. The present invention relates to a layout in which zigzag shapes are formed in such a way that the operation speed is improved by securing a low capacitance input capacitance, and the contact portion of the completed circuit is staggered with the contact hole of a neighboring active region.

As semiconductor devices are highly integrated, impurity regions and wiring widths used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that the resistance of the impurity region and the wiring increases, thereby lowering the operation speed.

Therefore, when wiring of elements in the semiconductor device is made of a low resistance material such as aluminum alloy and tungsten or made of polycrystalline silicon such as a gate electrode, a silicide layer may be formed to reduce the resistance. When the silicide layer is formed on the gate electrode formed of polycrystalline silicon, the silicide layer is formed on the surface of the impurity region to reduce the resistance.

However, the input / output terminals of the semiconductor device are susceptible to breakdown by electrostatic discharge (ESD) due to a drop in breakdown voltage due to a transient voltage or a thin gate oxide film. That is, if the drain region has a low resistance silicide layer, the applied voltage is not evenly distributed and is concentrated in the LDD (Lightly Doped Drain) region to destroy the semiconductor device. Therefore, an ESD protection transistor is formed to prevent electrostatic discharge destruction by evenly spreading the applied voltage by increasing the resistance of the impurity region used as the source and drain regions and the gate electrode formed of polycrystalline silicon in the input / output terminals.

The gate electrode of the MOS transistor has a thin oxide film as an insulator and forms one capacitor with the other part of the device. If the voltage across the capacitor exceeds a certain value, an excessively large electric field is formed in the insulating film, and irreversible breakage occurs. The maximum electric field that an oxide film can withstand in a MOS transistor is 6 MV / cm, which is about 30 V when converted into a structure having a thickness of about 50 nm. Voltages of this magnitude can be very easily formed by minute amounts of static electricity generated around the circuit.

Since the amount of charge that can destroy the transistor is very small as seen in the previous figures, the MOS circuit requires a protection circuit to maintain the voltage across the inlet terminal within a certain range and to prevent electrostatic breakdown. do.

The outage continues for a very short time, and if the voltage is very high, the peak of the current density flowing through the circuit will also be high. At this time, if a resistance is formed as a diffusion region in the wiring path connected from the ESD circuit to the internal circuit, and this resistance is connected to the pad through the contact between the metal and the diffusion region, excessive heat is generated at this contact, and the metal between aluminum and silicon An alloying phenomenon occurs at the pn junction, resulting in damage to the pn junction. In addition, when the current density is very high, electromigration occurs.

1 is a plan view of an YSD input protection circuit manufactured according to the prior art, and FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process of an ISD input protection circuit of a semiconductor device according to the prior art in which the portion B of FIG. 1 is enlarged.

Referring to FIG. 1, a first active region 31, a second active region 39, and a third active region 33 doped with n-type impurity ions are sequentially formed on a p-type semiconductor substrate. It is isolated by the oxide film 38, respectively.

In this case, a power supply voltage V _DD is applied to the first active region 31, and a ground voltage V _SS is applied to the third active region 33.

Referring to FIG. 2A, the first active region 31, the second active region 39, and the third active region 33 doped with n-type impurity ions are sequentially formed on the p-type silicon substrate 300. They are each isolated by the field oxide film 38.

In addition, a silicon oxide film 301 which is an insulating film is formed on the surfaces of each of the active regions 31, 39, and 33.

Referring to FIG. 2B, p-type impurity ion implantation is performed on the entire surface of the substrate. In this case, the impurity ions are buried under all the active regions 31, 39, 33 because no ion implantation barrier is formed on the substrate.

Referring to FIG. 2C, the buried impurities are sufficiently diffused to form a p-type impurity diffusion region 302 under the substrate surface, that is, under each of the active regions 31, 39, and 33.

The operation of the ESD protection circuit is as follows.

First, when a negative isdy charge is applied to the pad, the n + / p well diode connected to the pad is forward biased and biased to the p well. In this case, the voltage at the pad stage n + (emitter) is VESD (where VESD <0), the voltage at the p well (base) is the sum of VESD and 0.7 volts, and the VSS stage n + (collector) is 0 volts. Because the voltage difference between the base and emitter of the npn bipolar transistor is 0.7 volts and the voltage difference between the collector and emitter is equal to VESD, the bipolar transistor operates in active mode and discharges its charge to the VSS stage.

In addition, applying a positive YS charge to the pad causes the n + / p well diodes connected to the pad to be reverse biased, and this reverse bias increases, causing breakdown voltage at the n + / p well diodes. This breakdown voltage causes a bias to be applied to the p well. At this time, the bias condition is that the voltage at the pad end n + (collector) is VESD (where VESD> 0), the voltage at the p well (base) is greater than 0.7 volts, and the VSS end n + (emitter) is 0 volts (because Since the voltage difference between the base and emitter of the npn bipolar transistor is greater than 0.7 volts and the voltage difference between the collector and emitter is equal to VESD, the bipolar transistor discharges its charge to the VSS stage in either active or saturation mode.

As described above, in the ESD input protection circuit of the conventional semiconductor device, the RC delay time is longer due to the increase in the input capacitance as compared with the technique in which the ion implantation blocking layer is used only at the input section of the ESD input protection circuit when the p-type impurity ion is injected. Therefore, there is a problem in that the circuit operation speed is reduced.

Accordingly, an object of the present invention is to improve the operation speed by securing a low capacitance input capacitance by forming an impurity region only at an input cushion portion to secure an input capacitance when manufacturing an ESD protection circuit used in a high speed DRAM of a semiconductor device. In addition, the present invention provides a layout in which the contact portion is formed in a zigzag form so as to intersect with the contact hole of a neighboring active region.

In order to achieve the above objects, a method of manufacturing an ED input protection circuit of a semiconductor device according to the present invention includes a first active region, a second active region, and a third active region doped with a second conductive impurity ion on a first conductive semiconductor substrate. Forming the active regions in order and separating the first to third active regions by an isolation film, forming an insulating film on the surface of the first to third active regions, and Forming an ion implantation barrier on the surface; and forming a first conductivity type impurity diffusion layer in the lower adjacent portion of the first active region and the third active region.

In addition, the layout of the IC protection circuit according to the present invention includes a first conductive semiconductor substrate and a first formed on the surface of the semiconductor substrate and having a plurality of first contact portions having regular rows and columns and formed in a first direction and extending in a first direction. A first active region doped with a second conductive impurity in the form of a comb having a plurality of first branch portions in a second direction in the body portion and the body portion, and having a symmetrical form with the first active region, A plurality of third contact portions having a second body portion corresponding to the two portions, a space spaced from the first active region, forming a registration, formed on the surface of the semiconductor substrate, and aligned on the same line as the first contact portion; A third active region doped with a second conductivity type impurity having a first contact portion and a first contact portion formed on a surface of the semiconductor substrate in the spaced apart space between the first branch portion and the second branch portion; A second active region having a plurality of second contact regions staggered from the third contact region and doped with a second conductivity type impurity, and an isolation film formed on the surface of the semiconductor substrate other than the first to third active regions; .

1 is a plan view of an YSD input protection circuit manufactured according to the prior art.

2A to 2C are cross-sectional views illustrating a manufacturing process of an ISD input protection circuit of a semiconductor device according to the related art, in which a portion B of FIG. 1 is enlarged.

3A is a plan view of an electrostatic discharge input protection circuit of a semiconductor device manufactured according to the present invention.

3B is an enlarged plan view of a portion of an electrostatic discharge input protection circuit of a semiconductor device manufactured according to the prior art, in comparison with FIG. 3C.

FIG. 3C is a plan view of an electrostatic discharge input protection circuit of a semiconductor device manufactured according to the present invention in which portion A of FIG. 3A is enlarged.

4 is a plan view of an ESD input protection circuit manufactured according to the present invention;

5A to 5C are cross-sectional views illustrating a manufacturing process of an ISD input protection circuit of a semiconductor device according to the present invention, in which the portion C of FIG. 4 is enlarged.

Compared to the prior art, the present invention provides a p-type impurity ion implantation layer only at the input section of the ESD protection circuit, thereby reducing the concentration of bulk, thereby reducing the depletion region of the input section when voltage is applied. Increasing reduces the input capacitance, improving the circuit's operating speed. At this time, the input capacitance is as follows.

C _s = εA / d

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3A is a plan view of an electrostatic discharge input protection circuit of a semiconductor device manufactured in accordance with the present invention, and FIG. 3B shows a portion of an electrostatic discharge input protection circuit of a semiconductor device manufactured in accordance with the prior art. 3C is a plan view enlarged as compared with FIG. 3C, and FIG. 3C is a plan view of an electrostatic discharge input protection circuit of a semiconductor device manufactured according to the present invention in which portion A of FIG. 3A is enlarged.

Referring to FIG. 3A, the first active region 1 and the third active region 3 doped with n-type impurity ions on the p-type silicon substrate have a comb shape and are engaged with each other. Spaced apart.

The second active regions 2, 4 and 5 are located in a space where the respective comb-shaped active regions 1 and 3 are aligned, and all of these active regions 1, 2, 3, 4 and 5 are fields. It is isolated by the oxide film 8, respectively.

An insulating film (not shown) is formed on the active regions 1, 2, 3, 4, and 5, and a plurality of contact holes 6 and 7 are formed to open a predetermined portion of the insulating film.

As such, the contact portions 6 formed in the first active region 1 and the third active region 3 and the contact portions 9 of the second active regions 2, 4, and 5 are alternately formed in a zigzag form. have.

Referring to FIG. 3B, the second active regions 24 and 25 and the first active region 21 are separated by the field oxide film 28, and the contact portions 29 and 26 are formed in a line with each other. .

Referring to FIG. 3C, the second active regions 9 and 5 and the first active region 1 are separated by the field oxide film 8, and the contact portions 9 and 6 are horizontally staggered in a zigzag form. It is formed.

4 is a plan view of an YSD input protection circuit manufactured according to the present invention, and FIGS. 5A to 5C are cross-sectional views illustrating a manufacturing process of an ISD input protection circuit of the semiconductor device according to the present invention in which the portion C of FIG.

Referring to FIG. 4, a first active region 41, a second active region 49, and a third active region 43 doped with n-type impurity ions are sequentially formed on a p-type semiconductor substrate. It is isolated by the oxide film 48, respectively.

The first active region 41 and the third active region 43 doped with n-type impurity ions each have a comb shape and are engaged with each other, and are spaced at a predetermined interval.

The second active regions 49 are located in the space where the respective comb-shaped active regions 41 and 43 are engaged, and all of these active regions 41, 43, and 49 are isolated by the field oxide film 48, respectively. have.

In this case, a power supply voltage V _DD is applied to the first active region 41, and a ground voltage V _SS is applied to the third active region 43.

An ion implantation blocking film for p-type impurity ion implantation is formed on the second active region 49 to prevent the formation of an impurity ion layer under the ion implantation process.

The distance ① between the horizontal portion of the first active region 41 and the vertical end of the third active region 43 facing each other is formed to secure 4 μm or more, and the second active region 49 is formed. The separation distance (②) in the horizontal direction with the neighboring first and third active regions 41 and 43 of 2 mm or more is ensured, and the neighboring first and third active regions of the second active region 49 are also secured. The separation distance ③ in the vertical direction with respect to the regions 41 and 43 is also secured by 2 µm or more. In addition, the separation distance between the contact portion is formed to more than 3 ㎛.

Referring to FIG. 5A, the first active region 41, the second active region 49, and the third active region 43 doped with n-type impurity ions are sequentially positioned on the p-type silicon substrate 400. And they are each isolated by the field oxide film 48 for active region isolation.

Then, a silicon oxide film 401 is formed on the surfaces of the active regions 41, 49, and 43.

Referring to FIG. 5B, the photoresist pattern 50 is formed by performing a photolithography process on the surface of the second active region 49 with the ion implantation releasing film 50.

P-type impurity ion implantation is performed on the entire surface of the substrate. At this time, since the impurity ions are formed on the substrate, the impurity ion buried layer is formed only under the first and third active regions 41 and 43.

Referring to FIG. 5C, the buried impurities are sufficiently diffused to form a p-type impurity diffusion region 52 under the substrate surface, that is, under the first and third active regions 41 and 43.

Therefore, p-type impurity ion implantation reduces the bulk concentration by forming an ion implantation blocking layer only at the input section of the ESD protection circuit, thereby reducing the input capacitance by increasing the depletion region of the input section when voltage is applied. Improve the operation speed of the circuit.

Therefore, in the present invention, a high-intensity DRAM having a more limited input capacitance constraint than a conventional DRAM may form an inno-fusion injection barrier layer only at an input section of an ISD input protection circuit to reduce bulk concentration by implanting p-type impurity ions. This characteristic is similar to the conventional and has the advantage of improving the operation speed of the circuit as it secures a low capacitance input capacitance compared to the prior art.

Claims (6)

A first conductive semiconductor substrate, A first body portion formed on the surface of the semiconductor substrate and having a plurality of first contact portions having a regular row and column shape, the first body portion being elongated in a first direction, and the body portion having a plurality of first branch portions in a second direction A first active region doped with a second conductivity type impurity in the form of a comb, It has a symmetrical shape with the first active region, has a second body portion corresponding to the first body portion and the second branch portion, has a space spaced apart from the first active region, and is matched to the surface of the semiconductor substrate. A third active zero region formed of the second conductive type impurity having a plurality of third contact portions formed on the same line as the first contact portion and doped with the second conductivity type impurity; A plurality of second contact portions formed on the surface of the semiconductor substrate in the spaced apart space between the first branch portion and the second branch portion and staggered with the first contact portion and the third contact portion; A second active region having a doped with the second conductivity type impurity; A layout of an electrostatic discharge input protection circuit of a semiconductor device, comprising an isolation film formed on a surface of the semiconductor substrate other than the first to third active regions. The layout of an electrostatic discharge input protection circuit of a semiconductor device according to claim 1, wherein the first direction and the second direction are perpendicular to each other. 2. The layout of an electrostatic discharge input protection circuit as set forth in claim 1, wherein said first conductivity type is formed of p-type impurity and said second conductivity type is formed of n-type impurity. The method of claim 1, wherein the distance between the end of the first body portion and the second branch portion is formed to 4 ㎛ or more, and the separation distance between the first and second body portion and the second active region is formed to 2 ㎛ or more And the separation distance between the first and second branch portions and the second active region is 2 µm or more, and the separation distance between the contact portions is 3 µm or more. Layout. The first active region doped with the second conductivity type impurity ion and the second active region and the third active region are sequentially formed on the first conductive semiconductor substrate, and the first to third active regions are formed on the isolation layer, respectively. By means of isolation, Forming an insulating film on the surfaces of the first to third active regions; Forming an ion implantation barrier on the surface of the second active region; And forming a first conductivity type impurity diffusion layer in the lower adjacent portion of the first active region and the third active region. The method of claim 5, wherein the first conductivity type is formed of p-type impurity and the second conductivity type is formed of n-type impurity.