KR19990080283A - How to transfer data between FIFO and memory - Google Patents

Abstract

The present invention relates to any digital data processing apparatus comprising a FIFO and a memory, a DMA controller for controlling the data transfer between the FIFO and the memory, and a processor for controlling the DMA controller, the present invention relates to a method for transferring data between the FIFO and the memory. will be.

In the data transmission method from the memory to the FIFO according to the present invention, the processor unit writes the size of the data and the start address of the memory in which the data is stored, driving the DMA controller, and the DMA controller reads data from the memory. Memory-FIFO transfer step, the DMA controller checks whether all data has been transferred, and returns to the memory-FIFO transfer step depending on whether there is more data to be transferred, or the termination step notifies the processor unit of the end of data transfer. .

In addition, the data transfer method from the FIFO to the memory, each time the DMA controller writes data to the FIFO unit, setting the next bit (data end bit) of the current input data to an arbitrary logical value, the start address of the memory to transfer the data A FIFO-memory transfer step in which the DMA controller reads data from the FIFO unit in order and inputs the data into the memory, and the DMA controller examines the data end bits to transmit the FIFO-memory transfer step. It returns to or to generate an interrupt signal to inform the processor section is an interrupt step.

Description

Data transfer method between a FIFO and a memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method between digital data storage devices, and more particularly, to a method of transferring data between a FIFO and a memory using a direct memory access controller (DMA), that is, a data transfer method between a FIFO and a memory. It is about.

1 is a schematic diagram of transferring data using a DMA controller in a general computer system. Data transfer, usually using DMA, moves large amounts of data from memory 120 to a data storage location, such as hard disk drive 130, or from hard disk drive 130 to memory 120, or between two memories. When moving a large amount of data, it is used to realize efficient data movement by avoiding unnecessary steps.

At this time, the central processing unit 140 (CPU) instructs the DMA controller 110 to perform DMA processing when there is a DMA request, and the DMA controller 110 which received this instruction performs data movement between any two devices. Perform. When the data movement ends, the CPU 140 reports that the movement of data has ended.

However, such data transfer using DMA should be performed not only between the memory and the memory, or between the data storage device such as the hard disk drive 130 and the memory 120, but also between the FIFO and the memory as described above.

2 is a schematic diagram of data communication between two arbitrary points, wherein the first data transmission / reception device 210 and the second data transmission / reception device 220 exchange data via an arbitrary data processing device 300. In this case, there may be various reasons for exchanging data through the data processing unit 300. For example, the data processing speed of the first data transmitting and receiving device 210 and the data of the second data transmitting and receiving device 220 may be used. The processing speed is different. In another example, since the data structures used by the first data transmission / reception device 210 and the second data transmission / reception device 220 are different from each other, it is necessary to convert either transmission data into a data structure used by the other party and deliver them in order. If there is.

In the situation described above, the data processing unit 300 generally includes a FIFO and a memory. The memory is used to store data to be converted, and the FIFO receives data received from the memory or data to be sent to the memory. After that, it is used to output in order.

When the FIFO and the memory are used as described above, it is necessary to perform efficient data transmission and reception using the DMA controller as in the above-described memory and memory, or between the memory and the hard disk drive.

Accordingly, an object of the present invention is to provide a method for efficiently exchanging data between a FIFO and a memory using a DMA controller.

In order to achieve the above object, the data transfer method between the FIFO and the memory according to the present invention comprises a data transfer method from the memory to the FIFO and a data transfer method from the FIFO to the memory.

The data transfer method from the memory to the FIFO includes any digital data including a FIFO unit having an arbitrary digital data storage space, a memory, a DMA controller for controlling data transfer between the FIFO unit and a memory, and a processor unit for controlling the DMA controller. A processing apparatus comprising: a recording step of recording, by a processor unit, a size of data in a memory to be transmitted to a FIFO unit and a start address of a memory in which the data is stored in a predetermined storage location; A transfer command step of causing the processor to issue a data transfer start command to the DMA controller; A memory-FIFO transfer step in which the DMA controller receiving the data transfer start command reads data starting from the start address of the memory recorded in the predetermined storage location and writes the read data to the FIFO unit; An investigation step of the DMA controller checking whether all data has been transmitted; And if it is determined that there is still more data to be transmitted as a result of the investigation in the investigation step, the process returns to the memory-FIFO transmission step and, in the case where all data is transmitted, an end step of informing the processor unit that all data has been transmitted. Characterized in that comprises a.

At this time, in the above-mentioned writing step, the processor unit records the size of the data in the memory to be transmitted to the FIFO unit and the start address of the memory in which the data is stored. And writing the data into the first register and the second register, respectively, and the investigating step includes comparing the number of data read from the memory with the size of the data to be transmitted stored in the predetermined storage location. And the terminating step includes the step of generating a predetermined interrupt signal to the processor unit and informing the processor unit in order to inform the processor unit that all data has been transmitted.

On the other hand, the data transfer method from the FIFO to the memory, the DMA controller, each time the data is written to the FIFO unit, setting the next bit (data end bit) of the current input data to an arbitrary logic value; The processor unit writes a start address of a memory to which data inputted in the FIFO unit is to be transferred to a predetermined storage location; The processor unit giving an operation command to the DMA controller; A FIFO-memory transfer step of causing the DMA controller to read data in order from the FIFO unit and to input the read data into the memory starting from the start address recorded in the predetermined storage location; And the DMA controller checks whether all the data of the FIFO unit has been transferred, and returns to the FIFO-memory transfer step if all data is not transmitted, or generates an interrupt signal to notify the processor unit when all data has been transferred. Is characterized in that it comprises an interrupt step.

In this case, the interruption step may include determining whether all data have been terminated by examining a logic value of the data end bit in checking whether all data has been transmitted from the FIFO unit.

1 is a schematic diagram of transmitting data using a DMA controller in a general computer system;

2 is a schematic diagram of data communication between any two points;

3 is a block diagram of a data processing unit shown in FIG. 2;

4 is a flowchart relating to data transfer from a memory to a FIFO unit;

5 is a flowchart illustrating data transfer from a FIFO unit to a memory.

* Explanation of symbols for main parts of the drawings

110: DMA controller 120: memory

130: hard disk drive (HDD) 140: CPU

210: first data transceiver 220: second data transceiver

300: data processing unit 310: FIFO connection unit

320: FIFO unit 330: DMA controller

331: First register 332: Second register

340: memory 350: memory connection

360: processor unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of the data processing unit 300. An example of the configuration of the data processing unit 300 in charge of data processing between the first data transmission / reception unit 210 and the second data transmission / reception unit 220 shown in FIG. to be.

The data processing unit 300 includes a FIFO connection unit 310, a FIFO unit 320, a DMA controller 330, a memory 340, a memory connection unit 350, and a processor unit 360.

First, a process in which data transmitted from the first data transmission / reception device 210 is transferred to the second data transmission / reception device 220 will be described. In this case, it is assumed that the first data transmission and reception device 210 and the second data transmission and reception device 220 use different data structures. As an example, the first data transmitting and receiving device 210 is an apparatus for transmitting and receiving data of the frame relay network by being connected to the frame relay network, and the second data transmitting and receiving device 220 is connected to the ATM network to transmit data of the ATM network. It may be a device for transmitting and receiving. At this time, since the data structure used in the frame relay network and the data structure used in the ATM network are different from each other, in order to transmit data from one network to the other network, the data structure is converted from the data processing unit 300 to match the data structure of the other party. It must be given.

The FIFO connection unit 310 is directly connected to the first data transmission / reception unit 210 to receive data to be sent from the first data transmission / reception unit 210 to the second data transmission / reception unit 220, and in order of receiving 8-bit data. It is sent to the FIFO unit 320 through the input and output lines.

When data is input to the FIFO unit 320, the processor unit 360 instructs the DMA controller 330 to send data from the FIFO unit 320 to the memory 340, and receives the command. ) Transmits the data of the FIFO unit 320 to the memory 340.

The memory connection unit 350 converts the data stored in the memory to match the data structure used by the second data transmission / reception apparatus 220 and then outputs the data to the second data transmission / reception apparatus 220. At this time, the first data transmitting and receiving device 210 is a device for transmitting and receiving data of the frame relay network is connected to the frame relay network, the second data transmitting and receiving device 220 is connected to the ATM network for transmitting and receiving data of the ATM network In the case of a device, the frame data is converted into ATM cell data for use in an ATM network.

Meanwhile, a process of transmitting data transmitted from the second data transmission / reception apparatus 220 to the first data transmission / reception apparatus 210 is as follows.

The memory connection unit 350 receives data to be transmitted from the second data transmission / reception unit 220, converts the data to match the data structure used by the first data transmission / reception unit 210, and then inputs the data to the memory 340. .

When all the data to be transmitted to the memory 340 is input, the processor unit 360 instructs the DMA controller 330 to transmit the data of the memory 340 to the FIFO unit 320 and receives the command. 330 transmits the data of the memory 340 to the FIFO unit 320.

When the data of the memory 340 is transmitted to the FIFO unit 320, the FIFO connecting unit 310 sequentially transmits the data of the FIFO unit 320 to the first data transmitting and receiving device 210.

As such, the first data transmission and reception device 210 and the second data transmission and reception device 220 exchange data with each other through the data processing unit 300.

Now, a method of exchanging data between the FIFO unit 320 and the memory 340 using the DMA controller 330 will be described in detail.

4 is a flowchart illustrating data transfer from the memory 340 to the FIFO unit 320, in which the memory 340, the FIFO unit 320, the DMA controller 330, and the processor unit 360 relate to each other. A process in which data is transmitted from 340 to the FIFO unit 320 is shown.

In the first step, the processor unit 360 determines the size of data in the memory 340 to be transmitted to the FIFO unit 320 and the start address of the memory 340 in which the data is stored. Each of the first register 331 and the second register 332 included in 330 is written (step S410).

The processor 360 then gives a command to the DMA controller 330 to start a DMA operation, that is, a data transfer operation (step S420).

The DMA controller 330 receiving the DMA driving command reads data in units of 8 bits from the memory 340 by referring to the second register 332 (step S430), and reads the read data into the corresponding space of the FIFO unit 320. Record (step S440).

In addition, the DMA controller 330 writes data to the FIFO unit 320, and then compares the number of data transmitted so far with the contents of its first register 331, that is, the size of the data to be transmitted, It is checked whether data has been transmitted (step S450).

If it is determined in the above step S450 that there is still more data to be transmitted, the process returns to step S430. If all data is transmitted, the processor unit 360 generates an interrupt signal indicating that all data has been transmitted. Inform

5 is a flowchart illustrating data transfer from the FIFO unit 320 to the memory 340. The memory 340, the FIFO unit 320, the DMA controller 330, and the processor unit 360 are related to each other. A process in which data is transmitted from the memory 340 to the FIFO unit 320 is shown.

In the first step, the DMA controller 330 sets the next bit of the current input data to an arbitrary logic value each time data is written to the FIFO unit 320 (step S510). For example, if data to be transmitted is input to the FIFO unit 320 in units of 8-bit data, the 8-bit data is input to the FIFO unit 320 and then checked whether it is the last part of the data to be transmitted. The ninth bit (data end bit) is then set to logical value '0', and if it is the last part, the data end bit is set to logical value '1'.

This data end bit string is shown in the top row of the FIFO section 320. That is, as shown in FIG. 3, when the 8-bit data is input to the FIFO unit 320 from the FIFO connection unit 310 through the 8-bit data input / output line, the DMA controller 330 receives the corresponding data end bit of the top row of the corresponding data string. Set.

That is, if the first data transmitting and receiving device 210 is a device connected to the frame relay network, frame data continuously received from the frame relay network is input to the FIFO unit 320 in 8-bit units, and 8-bit data is input. Each time, the corresponding data end bit is set.

Then, the processor 360 records the start address of the memory 340 to transmit the data input to the FIFO unit 320 in the second register 332 of the DMA controller 330 (step S520), and then the DMA controller Give a driving command for (330) (S530).

Then, the DMA controller 330 reads data in units of 8 bits from the FIFO unit 320 in order (step S540), and inputs the read data into the memory 340 (step S550).

Next, the DMA controller 330 examines the value of the next bit of data currently read from the FIFO unit 320, that is, the data end bit output from the output terminal of the top row of the FIFO unit 320. As a result of this investigation, if the data end bit has a logic value of '0', there is still more data to be read from the FIFO section 320, and the flow returns to step S540, if the data end bit has a logic value of '1'. Since all data has been read from the FIFO unit 320, the flow advances to step S570.

In step S570, the DMA controller 330 generates an interrupt signal indicating that the transfer of all data has been completed and notifies the processor 360. FIG.

In this manner, data transfer from the FIFO unit 320 to the memory 340 is performed.

Using the data transmission method between the FIFO and the memory according to the present invention, there is an effect that can be efficiently implemented between the FIFO unit 320 and the memory 340.

Claims (6)

The FIFO unit 320 and the memory 340 having any digital data storage space, the DMA controller 330 for controlling data transfer between the FIFO unit 320 and the memory 340, and the DMA controller 330 In any digital data processing apparatus configured to include a processor unit 360 for controlling, the size of the data in the memory 340 to be transmitted to the FIFO unit 320 and the data is A recording step of recording the start address of the stored memory 340 in a predetermined storage location; A transfer command step of the processor unit 360 giving a data transfer start command to the DMA controller 330; A memory in which the DMA controller 330 receiving the data transfer start command reads data starting from the start address of the memory 340 recorded in the predetermined storage location and writes the read data to the FIFO unit 320; FIFO transmission step; An investigation step of examining, by the DMA controller 330, whether all data has been transmitted; And If it is determined that there is still more data to be transmitted as a result of the investigation, the processor returns to the memory-FIFO transmission step and, if all data is transmitted, indicates that all data has been transmitted. And a terminating step of notifying a data transfer method from the memory to the FIFO. The method of claim 1, wherein the writing step includes the size of the data in the memory 340 to be transmitted to the FIFO unit 320 by the processor unit 360 and the start address of the memory 340 in which the data is stored. And recording the corresponding data size and start address into the first register and the second register, respectively, provided in the DMA controller (330). The method according to claim 1, wherein the inspecting step comprises comparing the number of data read from the memory 340 with the size of the data to be transmitted stored in the predetermined storage location. Data transmission method. The method of claim 1, wherein the terminating step includes generating a predetermined interrupt signal from the DMA controller 330 and informing the processor 360 to inform the processor 360 that all data has been transmitted. And a data transfer method from the memory to the FIFO. The DMA controller (330), each time data is written to the FIFO unit (320), setting the next bit (data end bit) of the current input data to an arbitrary logic value; The processor 360 recording a start address of a memory 340 to transmit data input to the FIFO unit 320 in a predetermined storage location; The processor 360 giving an operation command to the DMA controller 330; The DMA controller 330 reads data from the FIFO unit 320 in order, and inputs the read data into the memory 340 starting from the start address recorded in the predetermined storage location; And The DMA controller 330 checks whether all data of the FIFO unit 320 has been transmitted. If all data is not transmitted, the DMA controller 330 returns to the FIFO-memory transfer step or terminates all data transfer. The data transfer method from the FIFO to the memory, characterized in that it comprises an interrupt step for generating an interrupt signal to inform the processor (360). 6. The method of claim 5, wherein the interrupting step includes determining whether all data has been terminated by examining a logic value of the data end bit in checking whether all data has been transmitted from the FIFO unit 320. A data transfer method from a FIFO to a memory, characterized in that.