KR19990079171A - Fast Fourier Transform (FFT) Device and Control Method - Google Patents

Abstract

The present invention relates to a fast Fourier transform (FFT) device and a control method of a digital signal processing to implement a structure for the Fast Fourier Transform (FFT) calculation process used in the digital signal processing.

In the present invention, in the FFT calculation structure made from the DIT algorithm, a multiplier, two add and subtractors, and four accumulators (X0, X1, X2, and X3) are included. MAC (multiply-and-accumulate) structure, to simplify the calculation structure of the butterfly in its calculation structure, to provide a structure that allows the entire calculation process to be simple and fast.

Description

Fast Fourier Transformation Device and Control Method

The present invention relates to a fast Fourier transform (FFT) device and a control method of a digital signal processing to implement a structure for the Fast Fourier Transform (FFT) calculation process used in the digital signal processing.

FFT calculation is frequently used for digital signal processing (DSP).

Fourier transform is a time function that can be expressed as overlap of sinusoids of different frequencies, and represents the magnitude of each frequency component included in the time function as a function of frequency, and is widely used for signal analysis and image processing. do.

Generally there are many FFT algorithms, but the most commonly used one is based on the DIT (Decimation-in-time) algorithm,

This algorithm consists of the butterfly (butterfly) as shown in Figure 2 having the most basic structure as a basic element.

Figure 1 shows an eight-point FFT calculation signal flow obtained from the DIT algorithm.

Looking at Figure 1, based on the butterfly structure, it can be seen that the butterfly is connected in multiple, in Figure 2 such a butterfly structure is shown in detail.

As shown in Fig. 2, when data X [a] + jY [a] and X [b] + jY [b] consisting of a real part and an imaginary part j are inputted to the input side of the butterfly, these values are multiplier ( 1), and through each summer (2, 3), obtain the output values X '[a] + jY' [a] and X '[b] + jY' [b] of the equations in the box. It becomes possible.

Looking at the FFT calculation flow process, it is divided into three types: butterfly, group, and stage. The FFT for the digital signal value inputted by repeating the butterfly calculation process of FIG. Will be converted,

This FFT transform is made with a cyclic algorithm as in FIG.

In this way, when the calculation of all the stages is completed, the order of the values obtained by the FFT calculation is rearranged.

As shown in the following Table 1, for 8-point FFT, for example,

Input data Binary address Conversion data Binary address X (0) 000 X (0) 000 X (1) 001 X (0) 100 X (2) 010 X (0) 010 X (3) 011 X (0) 110 X (4) 100 X (0) 001 X (5) 101 X (0) 101 X (6) 110 X (0) 011 X (7) 111 X (0) 111

Looking at each of the input address represented by the binary number and the binary address output through the FFT calculation, the binary address of the output value for the address of the input value has the opposite value, so that the bit reserve for the input values Reordering by bit-reserveed addressing ensures correct output.

In the present invention, in the FFT calculation structure made from the DIT algorithm, the present invention is to provide a structure that allows the entire FFT calculation process to be performed simply and quickly by efficiently calculating the butterfly.

1 illustrates an eight-point Fast Fourier Transform (FFT) calculation signal flow obtained from a deciation in time (DIT) algorithm.

FIG. 2 is a diagram illustrating a calculation structure of a butterfly in FIG. 1. FIG.

3 is a flow chart illustrating the FFT calculation algorithm of FIG.

4 is a block diagram of a Fast Fourier Transform (FFT) device of the present invention.

FIG. 5 is a control diagram conceptually illustrating a control process for each clock of FIG. 4.

FIG. 6 is a control diagram showing the control process for each clock of FIG.

FIG. 7 is a diagram illustrating a control process for each clock of FIG. 4, and illustrates a control diagram illustrating a case where a loop occurs.

FIG. 8 is a control diagram conceptually illustrating a control process for each clock when the phase angle q is 0 in FIG. 4; FIG.

FIG. 9 is a control diagram showing in detail the control process for each clock when the phase angle q is 0 in FIG.

FIG. 10 is a control diagram illustrating a control process for each clock when a phase angle q is 0 in FIG. 4 and a loop occurs.

FIG. 11 is a control diagram conceptually illustrating a control process for each clock when the phase angle q is π / 2 in FIG.

FIG. 12 is a control diagram illustrating in detail a control process for each clock when the phase angle q is π / 2 in FIG.

FIG. 13 is a control diagram illustrating a control process for each clock when a phase angle q is π / 2 in FIG. 4 and a loop occurs.

In the present invention, in order to achieve the above object it is proposed a device as shown in FIG.

FIG. 4 implements a calculation structure of a DIT (Decimation-In-Time) FFT as shown in FIG. 1.

Referring to the embodiment described below with reference to the accompanying drawings, the configuration and operation will be described.

Real number storage unit (10a) for storing the address for the real part of the tweed factor factors for the phase angle (q) and an imaginary storage unit for storing the address (sinptr) for the imaginary part ( Coefficient addressing registers 10 including 10b), a ROM 20 for outputting FFT coefficients stored according to an input address, input data to be converted and converted data Data addressing registers 30 which store addresses [a, a0 to a4], and data RAMs which output the read data in accordance with the input data address and store the converted data ( 40), the m register 50 for temporarily storing and outputting the FFT coefficients output from the ROM 20, and the t register for temporarily storing and outputting the data output from the data RAM 40 ( 60 and d register 70, The multiplier 80 multiplying the FFT coefficient output from the m register 50 and the data output from the t register 60, and the result calculated by the multiplier 80 is temporarily stored and output. P register 90,

Perform an additive operation of the multiplication result value output from the p register 90 and the input data output from the d register 70 to store the operation result in the corresponding XO register 110 and X2 register 120, An arithmetic operator 100 for performing an additive operation of the output data of the XO register 110 and the X2 register 120, that is, the previous operation result and the data output from the P register 90;

Perform an additive operation of the multiplication result value output from the p register 90 and the input data output from the d register 70 to store the operation result in the corresponding X1 register 140 and the X3 register 150, An arithmetic unit 130 for performing an operation on the output data of the X1 register 110 and the X3 register 12, that is, the previous calculation result and the data output from the P register 90;

And a numerical value limiting unit 160 for limiting and outputting numerical values of the values output from the XO register 110, the X1 register 120, the X2 register 140, and the X3 register 150.

The output values of the respective units and the logic operations of the calculators 100 and 130 are controlled by a control signal transmitted from a control unit for each clock that proceeds.

The apparatus proposed by the present invention characterized by such a configuration is characterized in that each clock (1 to 1) in the control means controls the output and action of each part so that a value such as the equation shown in FIG. 2 to calculate the butterfly can be obtained. 9) to be controlled as shown in FIG.

Referring to Figure 5, the basic operation thereof will be described.

The first clock 1 outputs the data of X [a] from the data RAM 40 so that the stored value of the d register 70 becomes X [a].

Then, when the next clock 2 is reached, the ROM 20 outputs cosq, and thus the stored value of the m register 50 becomes cosq.

In addition, X [b] is output from the data RAM 40 and X [b] is stored in the t register 60.

When the clock 3 reaches, the m register 50 and the t register 60 output these values, and the multiplier 80 multiplies these output values (m * t) and stores them in the p register 90. Done.

At this time, the count value sinq is output from the ROM 20, sinq is stored in the m register 50, and Y [b] is output from the data RAM 40.

Therefore, Y [b] is stored in the t register 60.

When the next clock 4 is reached, the operator 100 adds (d + p) the values output from the d register 70 and the p register 90 to store the value in the XO register 110. do.

In addition, the operator 130 subtracts the values output from the d register 70 and the p register 90 (d-p) and stores the values in the X1 register 140.

At this time, the multiplier 80 multiplies the values sinq and Y [b] stored in the t register 60 and the m register 50 in the previous clock 3 and stores them in the p register 90.

In the m register 50, cosq outputted from the ROM 20 at the current clock 4 is stored, and the d register 70 is outputted from the data RAM 40 at the current clock 4 in the d register 70. a] is stored.

In the clock 5, the calculation result of the calculation result of the operator 100 stored in the X0 register 110 is stored in the p register 90 from the previous clock 4 from the calculator 100 with the accumulated value X0. The existing value is subtracted (X0-P) and stored in the X0 register 110.

The calculator 130 adds (X1 + p) the value stored in the p register 90 and the value stored in the X1 register 140 to the previous clock 4 to store the value in the X1 register 140. do.

At the same time, the sinq and X [b] output from the ROM 20 and the data RAM 40 are stored in the m register 50 and the t register 60.

Then, when the clock 6 is reached, the value output from the register X0 110 is set to X '[a] among the values that are rounded and saturated through the numerical value limiting unit 160 and output.

At this time, the operator 100 subtracts (d-p) the value stored in the p register 90 from the value stored in the d register 70 and stores it in the X2 register 120.

The operator 130 adds (d + p) the value stored and output in the d register 70 and the value stored and output in the p register 90 to store it in the X3 register 150.

Here, the value obtained by multiplying the sinq and X [b] output from the m register 50 and the t register 60 is stored in the p register 90 again.

When the clock 7 is reached, the value output from the X1 register 140 is set as X '[b], and the value output from the p register 90 is calculated from the value output from the X2 register 120. 100 is subtracted (X2-p) and stored in the X2 register (12).

In addition, the operator 130 adds (X3 + p) the value output from the X3 register 150 and the value output from the p register 90 to store the result in the X3 register 150.

After that, when the clock 8 is reached, X2 is set to Y '[b] and X3 is set to Y' [a] in the clock 9.

Through this process, all of X '[a], X' [b], Y '[b], and Y' [a] can be obtained, and these values are shown as the execution equation at the top of FIG. Thus, the calculation for one butterfly can be completed.

FIG. 6 is a control diagram of each part actually performed in the apparatus of the present invention as shown in FIG. 4.

Here, a1 of the data addressing register 30 has an address of X [a], a2 of X [b], a3 of Y [a], and a4 of Y [b].

The data X0, X1, X2, and X3 obtained by the process described with reference to FIG. 5 in the data corresponding to each address are read, and the data of the data RAM 40 is stored in each of the clocks 6-9. When a] = X0, X1, X2, X3, the address a is set to a1, a2, a4, a3 from one previous clock, that is, the clock 5.

Therefore, the regions indicated by the addresses a1, a2, a4, a3 of the data RAM 40 have the values of X0, X1, X2, X3 obtained as described above.

At this time, the original addresses a1, a2, a3, a4 are increased by 1 in each of the clocks 5 to 8 (a1 = a1 + 1, a2 = a2 + 1, a3 = a3 + 1, a4 = a4 +). One)

In addition, the m register 50 stores and outputs values output from the ROM 20 by an address [cosptr] output from the real storage unit 10a and an address [sinptr] output from the imaginary storage unit 10b. The t register 60 and the d register 70 store and output the values output from the data RAM 40 by the addresses [a1] [a2] [a3] [a4] transmitted from the data addressing register 30. Done.

FIG. 7 is a diagram illustrating the FFT calculation by repeating the butterfly in the same process as described above with the entire butterfly unit as shown in FIG. 1, when a loop in which the butterfly is repeated exists. It is shown.

If clocks 5 to 9 are repeated cycles, and if more than one butterfly exists, assuming that the number of repetitions is N, the required cycle can be represented by 5N + 4, so one The cycle required for the butterfly is nine.

If there are two butterflies, that is, N = 2, then 14 cycles, as shown in the diagram.

When the repetition of the butterfly is present as shown in FIG. 1, when the value of q is the same in one group, but the value is different when the group is exceeded, the clock 11 and the clock ( As in 12), the values of cosptr and sinptr, which are address registers of the coefficient addressing register 10, are increased by one.

Also, when the next group starts from the end of one group, the values of a1, a2, a3, a4 of the data addressing register 30 are increased by a value larger than 1, so that the value of the address register a0 is increased. To be added.

At this time, when the phase angle q is 0 or π / 2, the sin value or the cos value is 0 or 1, and the equation is simplified.

That is, since the amount of calculation is reduced, if the phase angle as described above is controlled accordingly, fast calculation is possible.

FIG. 8 is a diagram illustrating a basic control concept of an execution equation when q is 0, and FIG. 9 is a diagram showing a control diagram performed in an actual device when q is 0. FIG. 10 is a control diagram illustrating a case where a loop exists when q is 0. FIG.

When q is 0, cosq = 1 and sinq = 0,

For example, X '[a] = X [a] + cosq * X [b] -sinq * Y [b], and the transplantation is X' [a] = X [a] + X [b].

As can be seen from the execution equation shown in Fig. 8, the equation is simplified.

Here, in the control diagram shown in FIG.

If there is no loop, it proceeds in clock order of 1, 2, 4, 10, 11, 12, 13, and only if the loop exists up to 5, 6, 7, 8, 9 clocks Suppose we run repeatedly, i.e., we run three butterflies in succession, 1, 2, 3, 5, 6, 7, 8, 5, 6, 7, 9, 10, 11, 12, 13 Control proceeds in order.

That is, when the loop is repeated, when the loop is exited, the last clock 8 is not executed, and control is performed on the clock 9.

11, 12, and 13 are diagrams illustrating a basic concept, a progress control diagram in an actual block, and a loop in a case where q has a value of π / 2.

Even in the case of FIG. 13, the procedure is the same as the clock progress control procedure.

As described above, in the execution procedure as shown in the attached control diagram, the apparatus as shown in FIG. 4 is controlled, and the entire FFT calculation is performed by executing the calculation of each butterfly.

As shown in FIG. 1, the FFT flow has a unit structure of a butterfly, and the q value is changed for each unit.

The FFT calculation is performed by controlling each part with a separate command for each mode corresponding to the general value, q value of 0, π / 2.

That is, as shown in FIG. 1, in the first stage, all q-values are zero and four butterflies have the same control procedure as in FIG. 10, and the loop may be executed three times.

In the second stage, each command is controlled by selecting each instruction in the mode where q is 0 in the upper group, the mode in which q is π / 2 in the lower group, and the mode in which q is a random value in the third stage. By doing so, each butterfly can be used to perform a complete FFT calculation.

As described above, a MAC (multiply-and-accumulate) structure consisting of one multiplier, two adder / subtracters, and four accumulators (X0, X1, X2, and X3) enables simple and fast FFT calculation. To provide a structure.

Claims (3)

Real number storage unit 10a for storing the address of the real part of the tree factor value (twsp) for the phase angle (q) and an imaginary storage unit for storing the address [sinptr] for the imaginary part ( Coefficient addressing registers 10 including 10b), a ROM 20 for outputting FFT coefficients stored according to an input address, input data to be converted and converted data Data addressing registers 30 which store addresses [a, a0 to a4], and data RAMs which output the read data in accordance with the input data address and store the converted data ( 40), the m register 50 for temporarily storing and outputting the FFT coefficients output from the ROM 20, and the t register for temporarily storing and outputting the data output from the data RAM 40 ( 60 and d register 70, The multiplier 80 multiplying the FFT coefficient output from the m register 50 and the data output from the t register 60, and the result calculated by the multiplier 80 is temporarily stored and output. P register 90, Perform an additive operation of the multiplication result value output from the p register 90 and the input data output from the d register 70 to store the operation result in the corresponding XO register 110 and X2 register 120, An arithmetic operator 100 for performing an additive operation of the output data of the XO register 110 and the X2 register 120, that is, the previous operation result and the data output from the P register 90; Perform an additive operation of the multiplication result value output from the p register 90 and the input data output from the d register 70 to store the operation result in the corresponding X1 register 140 and the X3 register 150, An arithmetic unit 130 for performing an operation on the output data of the X1 register 110 and the X3 register 12, that is, the previous calculation result and the data output from the P register 90; And a numerical value limiting unit 160 for limiting and outputting numerical values of the values output from the XO register 110, the X1 register 120, the X2 register 140, and the X3 register 150. Fast Fourier Transform (FFT) characterized in that the control of the output values of each part and the logic operation of the calculator (100, 130) is controlled by a control signal transmitted from the control means for each clock in progress. Device. According to claim 1, wherein the control means has a separate command for each mode according to the phase angle (q), accordingly, to output the control signal in accordance with each mode to perform the input and output control of each part Fast Fourier Transform (FFT) device. Determining a phase angle q, determining a control mode for outputting and calculating a value of each register configured for FFT conversion according to the determined phase angle q, and determining a control mode according to the determined control mode And a step of outputting a command signal to each register and arithmetic means to perform execution control of the FFT operation.