KR101842937B1 - Multifuntional proessing appratus - Google Patents

Abstract

According to an embodiment of the present invention, a multifunctional computation apparatus includes a MAC unit having a plurality of multiply-accumulate (MAC) circuits; Generating a read address group and transferring the read address group to a memory, wherein the read address group includes a plurality of read addresses; And a plurality of banks for storing a plurality of read data groups, the read data group transferring a read data group corresponding to the read address group among the plurality of read data groups to the MAC unit, And the memory.

Description

[0001] MULTIFUNCTIONAL PROCESSING APPRATUS [0002]

The technique described below relates to a multifunctional computing device.

A multiply-accumulate (MAC) circuit has a multiplier and an accumulator connected to the output of the multiplier. The MAC circuit is used for various purposes such as a finite impulse response filter (FIR filter), an infinite impulse response filter (IIR filter), a fast Fourier transform (FFT) and an inverse Fourier transform (IFFT). The MAC circuit was initially applied to a DSP (digital signal processor), but nowadays it is also applied to a general purpose processor (GPP).

There is a technique disclosed in Korean Patent No. 10-0835173 entitled " Device and method for digital signal processing for multiply accumulation operation " as a conventional technique of multiple MACs using a plurality of MACs in parallel. According to the related art, the control unit calls the instruction from the program memory every clock cycle and transfers it to the data address generation unit. This gives a lot of load to the control unit and lowers the efficiency of the whole system.

Korean Patent No. 10-0835173

SUMMARY OF THE INVENTION Accordingly, the present disclosure is directed to solving the problems of the prior art, and it is an object of the present invention to provide a multifunctional computation apparatus in which the control unit does not need to call an instruction from program memory every clock cycle.

The present disclosure also provides a multifunctional computation apparatus capable of minimizing the capacity of a memory to be used while simultaneously using a plurality of MAC circuits.

According to an embodiment of the present invention, a multifunctional computation apparatus includes a MAC unit having a plurality of multiply-accumulate (MAC) circuits; Generating a read address group and transferring the read address group to a memory, wherein the read address group includes a plurality of read addresses; And a plurality of banks for storing a plurality of read data groups, the read data group transferring a read data group corresponding to the read address group among the plurality of read data groups to the MAC unit, And the memory.

The multifunctional computation apparatus according to the present invention has an advantage that the address generation unit includes a lookup table or a state machine to generate an address without intervention of the control unit, thereby reducing the load of the control unit.

In addition, the multifunctional operation apparatus has an advantage that the capacity of a required memory can be reduced by storing data in a predetermined order so that collision does not occur between a plurality of banks.

1 is a diagram showing a multifunctional computation apparatus according to an embodiment.
FIGS. 2 to 10 are diagrams for explaining operations when the multifunctional computation apparatus shown in FIG. 1 has eight MACs and performs a 16-point fast Fourier transform (FFT) operation.
11 to 14 are diagrams for explaining the operation in the case where the multifunctional computation apparatus has eight MAC circuits and performs the FIR operation.

The following description is intended to illustrate and describe specific embodiments in the drawings, since various changes may be made and the embodiments may have various embodiments. However, it should be understood that the following description does not limit the specific embodiments, but includes all changes, equivalents, and alternatives falling within the spirit and scope of the following description.

The terms first, second, A, B, etc., may be used to describe various components, but the components are not limited by the terms, but may be used to distinguish one component from another . For example, without departing from the scope of the following description, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

As used herein, the singular " include "should be understood to include a plurality of representations unless the context clearly dictates otherwise, and the terms" comprises & , Parts or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, components, components, or combinations thereof.

Before describing the drawings in detail, it is to be clarified that the division of constituent parts in this specification is merely a division by main functions of each constituent part. That is, two or more constituent parts to be described below may be combined into one constituent part, or one constituent part may be divided into two or more functions according to functions that are more subdivided. In addition, each of the constituent units described below may additionally perform some or all of the functions of other constituent units in addition to the main functions of the constituent units themselves, and that some of the main functions, And may be carried out in a dedicated manner.

Also, in performing a method or an operation method, each of the processes constituting the method may take place differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

1 is a diagram showing a multifunctional computation apparatus according to an embodiment. 1, the multi-function processor includes a MAC unit 110, an address generator 120, a memory 130, a read mapper 140, a read mapper 150, (160).

The MAC unit 110 includes a plurality of MAC circuits 111 and an arithmetic unit 116. Each of the plurality of MAC circuits 111 has a multiplier 112 and an accumulator 115. The accumulator 115 accumulates the output of the multiplier 112. The accumulator 115 includes a summer 113 and a register 114 for this purpose. The accumulator 115 in the MAC circuit 111 may be omitted or the register 114 may be omitted. The circuit in which the register 114 is omitted in the MAC circuit 111 corresponds strictly to a multiply-add circuit, but the multiply-add circuit is considered to be included in the scope of the MAC circuit 111 in the present invention. The circuit in which the accumulator 115 is omitted from the MAC circuit 111 is strictly a multiplication circuit, but in the present invention, such a multiplication circuit is considered to be included in the category of the MAC circuit 111. That is, the MAC circuit 111 of the present invention is a MAC circuit in a broad sense including multiply-accumulate circuits as well as multiply-accumulate circuits in its nature. The arithmetic unit 116 performs at least one of sum, difference, accumulation, and shift operations on a plurality of outputs output from the plurality of MAC circuits 111. [ The arithmetic unit 116 outputs one or more MAC outputs (Mout1 to MoutC, where C is an integer) obtained as a result of at least one operation. The arithmetic unit 116 may additionally output a flag FL indicating the final operation result. The operation performed in the arithmetic unit 116 is changed according to an operation (e.g., FFT, FIR, or the like) to be performed by the multifunctional operation unit. Accordingly, the arithmetic operation unit 116 changes the operation performed in accordance with the arithmetic control signal ACS transmitted from the control unit 160. [

The address generator 120 generates a read address group (RAG), and transmits the read address group (RAG) to the memory 130. A read address group (RAG) has a plurality of read addresses. The address generator 120 generates a write address group (WAG) and transfers the write address group to the memory 130. A write address group (WAG) has a plurality of write addresses. The address generator generates a read mapping value (RMV) and a write mapping value (WMV) and transfers the read mapping value (RMV) and the write mapping value (WMV) to the read mapper 140 and the write mapper 150, respectively.

The address generator 120 includes a counter 122 and a lookup table 124 as an example. The counter 122 outputs a value changed in accordance with the clock signal CK. For example, the counter 122 outputs an integer value that increases in accordance with the clock signal CK. The lookup table 124 outputs a selected read address group (RAG) according to the value output from the counter 122 among the plurality of read address groups. To this end, the lookup table 124 stores a plurality of groups of read addresses. In addition, the lookup table 124 outputs a selected write address group (WAG) according to a value output from the counter 122 among a plurality of write address groups. To this end, the lookup table 124 stores a plurality of groups of write addresses. Instead of outputting the write address group WAG from the lookup table 124, the write address group WAG may be obtained by delaying the read address group RAG. The lookup table 124 outputs a selected read mapping value RMV according to a value output from the counter 122 among a plurality of read mapping values. To this end, the lookup table 124 stores a plurality of read mapping values. The lookup table 124 outputs a selected write mapping value (WMV) according to a value output from the counter 122 among a plurality of write mapping values. To this end, the lookup table 124 stores a plurality of write mapping values.

Unlike the drawing, the address generator 120 may include a state machine (not shown). The state machine generates a read address group (RAG), a write address group (WAG), a read mapping value (RMV) and a write mapping value (WMV) according to the clock signal. In a case where the address generating unit 120 includes a state machine, the lookup table 124 or the counter 122 may be omitted.

The memory 130 has a plurality of banks 132. Thus, the memory 130 can read or write multiple data simultaneously. For example, in the case where the memory 130 includes four banks 132, the memory 130 can simultaneously read or write four data. Of course, in this case, the four data must be located in different banks 132. Memory 130 may be, for example, a dual-port memory. In this case, the memory 130 can simultaneously perform a write operation and a read operation. For example, in the case where the memory 130 includes four banks 132, the memory 130 can simultaneously read four data and write four data. Of course, in this case, the four data to be read are located in different banks 112, and the four data to be written should be located in different banks 132. [

The plurality of banks 132 store a plurality of read data groups. The memory 130 transfers the read data group (RDG) corresponding to the read address group (RAG) among the plurality of read data groups to the MAC unit 110. The read data group RDG includes a plurality of read data. Each of the plurality of read data may be a complex number, a real number, or an integer number. The plurality of read data is output from the different banks 132. In the case where the memory 130 includes the first to fourth banks, the first to fourth read data among the plurality of read data may be output from the first to fourth banks, respectively. The plurality of read data may be located in the same row. For example, the first to fourth read data may be the first data of the first to fourth banks, respectively. The plurality of read data may be located in different rows. For example, the first and third read data may be the fifth data of the first and third banks, respectively, and the second and fourth read data may be the sixth data of the second and fourth banks, respectively.

The plurality of banks 132 store one or more write data groups. The memory 130 stores the write data group WDG in a position corresponding to the write address group WAG. The write data group WDG has one or more write data. Each of the one or more write data may be a complex number, a real number, or an integer number. The one or more write data is stored in different banks 132. In a case where the memory 130 includes the first to fourth banks, the first to fourth write data among the one or more write data may be stored in the first to fourth banks, respectively. One or more write data may be stored in the same row. For example, the first to fourth write data may be stored in the first positions of the first to fourth banks, respectively. The plurality of write data may be stored in different rows. In one example, the first and third write data may be stored in the fifth positions of the first and third banks, respectively, and the second and fourth write data may be stored in the sixth position of the second and fourth banks, respectively.

The read mapper 140 maps a plurality of read data to a plurality of MAC inputs (Min1 to MinB, where B is an integer) according to the read mapping value RMV. The write mapper 150 maps one or more MAC outputs Mout1 to MoutC to one or more write data according to a write mapping value WMV.

The controller 160 stores initial read data groups in the memory 130 and stores a plurality of read address groups in the lookup table 124 and then drives the address generator 120. The control unit 160 stores initial read data groups in the memory so that a plurality of read data are output from different banks among the plurality of banks 132 even though the plurality of MAC circuits 111 operate simultaneously . The controller 160 also transmits an arithmetic control signal ACS corresponding to the operation to be performed by the multi-function processor to the arithmetic unit 116. In this way, the control unit 160 mainly participates in the initial stage of the operation of the multifunctional computation apparatus, and does not participate at all or very often participates in the operation of the multifunctional computation apparatus (for example, FFT, FIR, etc.). That is, during the operation, the operation is mainly performed by the operation of the address generator 120. Accordingly, the burden on the control unit 160 is reduced. The controller 160 may be a CPU, for example.

The multifunctional computation apparatus shown in FIG. 1 can perform FFT operations. FIGS. 2 to 10 are diagrams for explaining operations when the multifunctional computation apparatus shown in FIG. 1 has eight MACs and performs a 16-point fast Fourier transform (FFT) operation. 2 is a diagram showing a "radix2, decimation in time" operation as an example of a calculation of a 16-point FFT. The 16-point FFT operation has four stages, and eight butterfly operations are performed in each stage. A 16-point FFT has 16 inputs (X (1) to X (16)) and 16 outputs (Y (1) to Y (16)). 3 is a diagram for explaining a butterfly operation briefly. 3, the butterfly receives the first and second butterfly inputs x1 and x2 and the twiddle factor w and outputs the first and second butterfly outputs y1 and y2.

4 is a diagram for explaining the operation of the MAC unit. Referring to FIG. 4, the MAC unit 110 includes a first butterfly circuit 410 and a second butterfly circuit 470. The first butterfly circuit 410 includes first through fourth MAC circuits 420, 430, 440, and 450 and a first arithmetic unit 460. Each of the MAC circuits of the first to fourth MAC circuits 420, 430, 440 and 450 includes a multiplier 112 and an accumulator 115. In the case of the FFT mode, each MAC circuit only has to perform multiplication, so that the accumulator 115 does not operate. Therefore, the register 114 included in the accumulator 115 operates in a reset state and outputs 0 (zero). The first MAC circuit 420 outputs a value obtained by multiplying the first and second MAC inputs Min1 and Min2. The second MAC circuit 430 outputs a value obtained by multiplying the third and fourth MAC inputs Min3 and Min4. The third MAC circuit 440 outputs the product of the fifth and sixth MAC inputs Min5 and Min6. The fourth MAC circuit 450 outputs the product of the seventh and eighth MAC inputs Min7 and Min8.

The first arithmetic unit 460 outputs the first to fourth outputs Mout1 to Mout4. The first output Mout1 corresponds to a value obtained by adding the output of the first MAC circuit 420 to the ninth input Min9 and subtracting the output of the second MAC circuit 430. [ The second output Mout2 corresponds to a value obtained by subtracting the output of the first MAC circuit 420 and the output of the second MAC circuit 430 to the ninth input Min9. The third output Mout3 corresponds to a value obtained by adding the output of the third MAC circuit 440 to the tenth input Min10 plus the output of the fourth MAC circuit 450. [ The fourth output Mout4 corresponds to subtracting the output of the third MAC circuit 440 and subtracting the output of the fourth MAC circuit 450 to the tenth input Min10. In order to perform such an operation, the first arithmetic unit 460 includes first to sixth summation units 461 to 466. The first summation unit 461 subtracts the output of the second MAC circuit 430 from the output of the first MAC circuit 420. The second summation unit 462 adds the output of the fourth MAC circuit 450 to the output of the third MAC circuit 440. The third summation unit 463 adds the output of the first summation unit 461 to the ninth MAC input Min9. The fourth summation unit 464 subtracts the output of the first summation unit 461 from the ninth MAC input Min9. The fifth summation unit 465 adds the output of the second summation unit 462 to the 10th MAC input Min10. The sixth summation unit 466 subtracts the output of the second summation unit 462 from the 10th MAC input Min10.

The second butterfly circuit 470 receives the 11th to 20th MAC inputs Min11 to Min20 and outputs the 5th to 8th MAC outputs Mout5 to Mout8. Since the configuration of the second butterfly circuit 470 is the same as that of the first butterfly circuit 420, detailed description thereof will be omitted.

In order to perform the butterfly operation, the butterfly circuit 410 of FIG. 4 requires that the real number x1 [R] and the imaginary number x1 [I] of the first butterfly input x1 be input to the ninth and tenth MAC inputs (Min9, Min10). (X2 [R]) of the second butterfly input (x2) to the first and fifth MAC inputs Min1 and Min5. (I2) of the second butterfly input (x2) to the third and seventh MAC inputs Min3 and Min7. And inputs the real number w [R] of the rotation factor w to the second and eighth MAC inputs Min2 and Min8. The imaginary number w [I] of the rotation factor w is input to the fourth and sixth MAC inputs Min4 and Min6. When input as described above, the first MAC output Mout1 corresponds to the real number of the first butterfly output y1. And the second MAC output Mout2 corresponds to the real number of the second butterfly output y2. The third MAC output Mout3 corresponds to the imaginary number of the first butterfly output y1. And the fourth MAC output Mout4 corresponds to the imaginary number of the second butterfly output y2.

Referring to FIG. 5, the memory 130 includes first to sixth banks 510 to 560. The first to fourth banks 510 to 540 are, for example, dual-port memories, capable of simultaneously performing four outputs and four inputs. The fifth and sixth banks 550 to 560 are, for example, single-port memories and can simultaneously perform two outputs.

The first to fourth banks 510 to 540 output the first to fourth butterfly inputs X1 to X4 corresponding to the first to fourth butterfly input addresses XA1 to XA4, respectively. The first to fourth banks 510 to 540 receive the first to fourth butterfly outputs Y1 to Y4 corresponding to the first to fourth butterfly output addresses YA1 to YA4, respectively. The fifth and sixth banks 550 and 560 output first and second rotation factors W1 and W2 respectively corresponding to the first and second rotation factor addresses WA1 and WA2.

The first to fourth butterfly input addresses XA1 to XA4 and the first and second rotation factor addresses WA1 and WA2 correspond to the read address group RAG in Fig. That is, the read address group RAG includes first to fourth butterfly input addresses XA1 to XA4 and first and second rotation factor addresses WA1 and WA2 as a plurality of read addresses. The first to fourth butterfly output addresses YA1 to YA4 correspond to the write address group WAG in Fig. That is, the write address group WAG includes the first to fourth butterfly output addresses YA1 to YA4 as a plurality of write addresses. The first to fourth butterfly inputs X1 to X4 and the first and second rotational factors W1 and W2 correspond to the read data group RDG in Fig. That is, the read data group RDG includes first to fourth butterfly inputs X1 to X4 and first and second rotational factors W1 and W2 as a plurality of read data. The first to fourth butterfly outputs Y1 to Y4 correspond to the write data group WDG in Fig. That is, the write data group WDG includes first through fourth butterfly outputs Y1 through Y4 as a plurality of write data.

The memory 130 stores the initial read data groups X (1) to X (16), W (1) to W (n) (8). The initial read data groups X (1) to X (16), W (1) to W (8)) are stored in the memory 130 before the FFT operation and are stored by the controller 160 as an example. In the figure, 1 / X (1) means that X (1) is stored at address 1 and 5 / W (1) means that W (1) is stored at address 5.

The 16 point FFT inputs X (1) through X (16) are generally sequentially (X (1), X (2), X (3), X (4), X (5) ), X (7), X (8), X (9), X (10), X (11), X (12) (4), X (7), X (8), X (5), X (6) (16), X (11), X (12), X (9), X (10), X (13), X (14), X (15) For example, the predetermined order is not sequential but sequential in row units. That is, X (1) to X (4) are located in the first row, X (5) to X (8) are located in the second row, X (9) ) To X (16) are located in the fourth row. The predetermined order is obtained through simulation before the collision between the banks 510 to 540 does not occur during the FFT operation. Here, a collision between the banks 510 to 540 means that two or more of the first to fourth butterfly inputs X1 to X4 are simultaneously read from one bank. Since one bank can output only one butterfly input at a time, if two or more butterfly inputs must be read from one bank, normal operation becomes impossible. The simulation can be performed during the program compilation process. For example, the compiler may check for conflicts between the banks and determine a predetermined order by repeating the process of changing the location of some of the initial FFT inputs X (1) to X (16) if a conflict occurs .

The eight rotation factors W (1) to W (8) are generally sequentially (W 1, W 2, W 3, W 4, W 5, W (2), W (4), W (3), W (6), W (8) (5), W (7), W (8)). For example, the predetermined order is not sequential but sequential in row units. W (3) and W (4) are located in the second row, W (5) and W (6) are located in the third row, W ) And W (8) are located in the fourth row. The predetermined order is obtained through simulation before the collision between the banks 550 to 560 does not occur during the FFT operation.

6, the lookup table 124 of the address generator 120 includes a butterfly lookup table 610, a rotation factor lookup table 620, a read mapping value lookup table 630, a write mapping value lookup table 640 And a register 650. In one example, after the controller 160 inputs the values required for the butterfly lookup table 610, the rotation factor lookup table 620, the read mapping value lookup table 630, and the write mapping value lookup table 640, And drives the counter 122.

The butterfly lookup table 610 outputs a plurality of butterfly input addresses XA1 to XA4 corresponding to the output value of the counter 122. [ The register 650 outputs a plurality of butterfly output addresses YA1 to YA4 that delay the plurality of butterfly input addresses XA1 to XA4 by one or more clock cycles. The delay by the register 650 is controlled until a plurality of butterfly inputs X1 to X4 are output from the memory 130 and then input to the memory 130 as a plurality of butterfly outputs Y1 to Y4 And corresponds to the required delay. Although not explicitly shown in FIG. 1, after a plurality of butterfly inputs X1 to X4 are output from the memory 130, a plurality of butterfly outputs Y1 to Y4 are stored in the memory 130 One or more clock cycles may be required until input. A plurality of butterfly outputs Y1 to Y4 are stored in the memory 130 by using values obtained by delaying a plurality of butterfly input addresses XA1 to XA4 as a plurality of butterfly output addresses YA1 to YA4 Are stored in the positions where the plurality of butterfly inputs (X1 to X4) were respectively stored.

The rotation factor lookup table 620 outputs one or more rotation factor addresses WA1, WA2 corresponding to the output value of the counter 122. [ The read mapping value lookup table 630 outputs a read mapping value (RMV) corresponding to the output value of the counter. The write mapping value lookup table 640 outputs a write mapping value (WMV) corresponding to the output value of the counter.

7 is a diagram showing the values stored in the butterfly look-up table 610. FIG. Referring to FIG. 7, in the first cycle, the butterfly lookup table 610 outputs 1, 2, 3, 4 as a plurality of butterfly input addresses XA1 to XA4. Therefore, the memory 130 outputs X (1), X (2), X (3), and X (4) located at 1, 2, 3 and 4 as a plurality of butterfly inputs X1 to X4 . Since a plurality of butterfly input addresses XA1 to XA4 are also used as a plurality of butterfly output addresses YA1 to YA4, a plurality of butterfly outputs Y1 to Y4 are stored in the same positions in the memory, 3, and 4, respectively. In the second cycle, the butterfly look-up table 610 outputs 7, 8, 9, 10 as a plurality of butterfly input addresses XA1 to XA4. Therefore, the memory 130 outputs X (7), X (8), X (5), and X (6) located at addresses 7, 8, 9 and 10 as a plurality of butterfly inputs X1 to X4 . The plurality of butterfly input addresses XA1 to XA4 are also used as the plurality of butterfly output addresses YA1 to YA4 so that the plurality of butterfly outputs Y1 to Y4 are stored in the same positions in the memory, 9, and 10, respectively. In the same manner, the butterfly lookup table 610 outputs 13, 14, 15 and 16 in the third cycle, and the memory 130 outputs X (11), X (12), X (9) . In the fourth cycle, the butterfly lookup table 610 outputs 19, 20, 21 and 22, and the memory 130 outputs X (13), X (14), X (15) and X (16) . The subsequent operation is the same as the previous one, and is omitted for the sake of explanation.

8 is a diagram showing the values stored in the rotation factor lookup table 620. FIG. Referring to FIG. 8, in the first to fourth cycles, the rotation factor lookup table 620 outputs 5, NA as one or more butterfly input addresses WA1, WA2. Here, NA means no output value. The memory 130 outputs W (1) located at address 5 as one or more rotation factors W1. In the fifth cycle, the rotation factor lookup table 620 outputs 5, 18 as one or more butterfly input addresses WA1, WA2. The memory 130 outputs W (1) and W (5) located at addresses 5 and 18 as one or more rotation factors W1 and W2. The subsequent operation is the same as the previous one, and is omitted for the sake of explanation.

FIG. 9 is a diagram for explaining the operation of the read mapper 140. FIG. 9, in a first cycle, the read mapper 140 maps the real number X2 [R] of the second butterfly input X2 to the first MAC input Min1, Maps the real number W1 [R] of the second butterfly input X2 to the second MAC input Min2 and maps the imaginary number X2 [I] of the second butterfly input X2 to the third MAC input Min3, And maps the imaginary number W1 [I] of the first rotational factor W1 to the fourth MAC input Min4. In the same way, X2 [R], W1 [I], X2 [I], W1 [R], X1 [R], X1 [I], X4 [R], W1 [ (I), X4 [R], W1 [I], X4 [I], W1 [R], X3 [R] and X3 [I] to the fifth through twentieth MAC inputs Min5 through Min20 . In the second cycle, the read mapper 140 reads X4 [R], W1 [R], X4 [I], W1 [I], X4 [R], W1 [I], X4 [I] I], X2 [I], W2 [R], X2 [I], W1 [I], X2 [R], W1 [I] , X1 [R], and X1 [I] to the first to twentieth MAC inputs (Min1 to Min20), respectively. The subsequent operation is the same as the previous one, and is omitted for the sake of explanation.

Also, it is possible to reduce the complexity of the mapper by changing the storage position between the data in the same row and making the change rule constant in the changed rows. Also, address changes to the location change between the data within the same row of the mapping information may be incorporated into the read or write address memory (butterfly lookup table 610, rotation factor lookup table 620). The performance and content of this process are determined and obtained by pre-simulation.

FIG. 10 is a diagram for explaining the operation of the write mapper 150. FIG. 10, the write mapper 150 in the first cycle maps the first MAC output Mout1 to the real value Y1 [R] of the first butterfly output Y1, and the second MAC output Mout2 to the real value Y2 [R] of the second butterfly output Y2 and the third MAC output Mout3 to the imaginary value Y1 [I] of the first butterfly output Y1 And maps the fourth MAC output Mout4 to the imaginary value Y2 [I] of the second butterfly output Y2. Further, the fifth to 8th MAC outputs Mout5 to Mout8 are mapped to Y3 [R], Y4 [R], Y3 [I], and Y4 [I], respectively. In the second cycle, the first to 8th MAC outputs Mout1 to Mout8 are set to Y3 [R], Y4 [R], Y3 [I], Y4 [I], Y1 [R], Y2 [ I] and Y2 [I], respectively. The subsequent operation is the same as the previous one, and is omitted for the sake of explanation.

The multifunctional computation apparatus shown in Fig. 1 can perform the FIR operation. 11 to 13 are diagrams for explaining the operation in the case where the multifunctional computation apparatus has eight MAC circuits and performs an FIR operation.

Referring to FIG. 11, the MAC unit 110 includes eight MAC circuits 111 and an arithmetic unit 116. Each of the eight MAC circuits 111 includes a multiplier 112 and an accumulator 115 to multiply the two MAC inputs and accumulate the multiplied values. The arithmetic unit 116 includes a plurality of adders to sum all the values output from the eight MAC circuits 111. [ Assuming that odd-numbered MAC inputs (Min1, Min3, ... Min15) are inputs to the FIR filter and even-numbered MAC inputs (Min2, Min4, ... Min16) are coefficients of the FIR filter, ) Can process eight inputs simultaneously. Accordingly, in the case of a 32-tap FIR filter, when the MAC unit 110 operates for 4 cycles, the result is obtained. As described above, the operation performed by the arithmetic unit 116 in accordance with the arithmetic control signal ACS transmitted from the controller 160 is changed as shown in the drawing. Since the configuration of the arithmetic unit 116 is changed to be suitable for the FFT operation according to the arithmetic control signal ACS or can be modified to be suitable for the FIR operation by a simple combination of an adder and a switch, For the sake of convenience.

Referring to FIG. 12, the memory 130 includes first to sixteen banks. The first to eighth banks store the FIR inputs In (1) to In (32), and the ninth to sixteenth banks store the FIR coefficients C (1) to C (8). The memory 130 outputs In (1) to In (8) and C (1) to C (8) in the first cycle. In (1) to In (8) are mapped to Min1, Min3, ... Min15 by the read mapper 140 and C (1) to C (8) are mapped to Min2, Min4, . In the second cycle, the memory 130 outputs In (9) to In (16) and C (1) to C (8). In (9) to In (16) are mapped to Min1, Min3, ... Min15 by the read mapper 140 and C (1) to C (8) are mapped to Min2, Min4, . The subsequent operation is the same as the previous one, and is omitted for the sake of explanation. Since the coefficients C (1) to C (8) are output continuously, they can be implemented using registers instead of banks. In this case, the number of banks used in the memory 130 can be reduced.

13 shows an example in which the address generator 120 is implemented as a state machine. Since the read mapping value RMV and the addresses transferred to the ninth through sixteenth banks correspond to constants, they are not shown in the drawings for convenience of description, and only the generation of addresses transferred to the first through eighth banks is shown in the drawing Respectively. The address generator 120 includes a counter 1301, a multiplier 1302, and first to eighth adders 1311, 1312, ..., 1318. The counter 1301 outputs an integer increasing from 0 to 1. The multiplier 1302 multiplies the output of the counter by 16. The adders 1311 to 1318 add 0 to 7 to the output of the multiplier 1302. The outputs of the adders 1311 to 1318 are transferred to the first to eighth banks.

FIG. 14 is a diagram showing a modification of the MAC unit 110 shown in FIG. Referring to FIG. 14, the MAC unit 110 includes eight MAC circuits 111 and an arithmetic unit 116. Unlike FIG. 11, each of the eight MAC circuits 111 includes only a multiplier 112. In addition, the arithmetic unit 116 includes a plurality of adders 117 as well as an accumulator 115. The accumulator 115 has an adder 113 and a register 114. In this way, when the accumulator 115 located in the MAC circuits 111 is moved to the arithmetic unit 116, the number of accumulators 115 can be reduced.

It should be noted that the present embodiment and the drawings attached hereto are only a part of the technical idea included in the above-described technology, and those skilled in the art will readily understand the technical ideas included in the above- It is to be understood that both variations and specific embodiments which can be deduced are included in the scope of the above-mentioned technical scope. For example, in the present embodiment, an FFT operation using 8 MAC is illustrated by way of example, but a person skilled in the art will be able to apply it to 16 MAC or more MAC.

Claims (19)

A MAC unit having a plurality of multiply-accumulate (MAC) circuits;
Generating a read address group and transferring the read address group to a memory, wherein the read address group includes a plurality of read addresses; And
And a read data group corresponding to the read address group among a plurality of read data groups to the MAC unit, wherein the read data group includes a plurality of read data groups Said memory comprising:
The address generating unit
A counter outputting a value changed according to a clock; And
And a lookup table for outputting the read address group selected according to the value among the plurality of read address groups, delete delete The method according to claim 1,
Further comprising a controller for storing initial read data groups in the memory and driving the address generator after storing the plurality of read address groups in the address generator. 5. The method of claim 4,
Wherein the controller stores the initial read data groups in the memory such that the plurality of read data is output from different banks among the plurality of banks while the plurality of MAC circuits operate simultaneously. The method according to claim 1,
Wherein each of the plurality of MAC circuits includes a multiplier and an accumulator. The method according to claim 1,
Each of the plurality of MAC circuits including a multiplier, or a multiplier and an adder. The method according to claim 1,
And a read mapper mapping the plurality of read data to a plurality of MAC inputs according to the read mapping value output from the address generation unit and transmitting the plurality of MAC inputs to the plurality of MAC circuits Multifunctional computing device. The method according to claim 1,
The MAC unit
An arithmetic unit that performs at least one of sum, difference, accumulation, and shift operations on a plurality of outputs from the plurality of MAC circuits and outputs one or more MAC outputs obtained as a result of the at least one operation A multifunctional arithmetic unit. 10. The method of claim 9,
And a write mapper for mapping the one or more MAC outputs to one or more write data in accordance with the write mapping value output from the address generator and transmitting the one or more write data to the memory, . 10. The method of claim 9,
When the multifunctional computation device operates in the FFT mode,
Wherein the read data group includes one or more rotation factors and a plurality of butterfly inputs as the plurality of read data and the write data group includes a plurality of butterfly outputs as the plurality of write data,
And a butterfly operation is performed by the MAC unit. 12. The method of claim 11,
Wherein the address generator controls the memory such that the plurality of butterfly outputs are respectively stored at the positions where the plurality of butterfly inputs were in the memory. 12. The method of claim 11,
Wherein the memory stores initial read data groups in a predetermined order so that collision between the plurality of banks does not occur during an FFT operation. 14. The method of claim 13,
Wherein the predetermined order is not sequential but sequential in row units. 12. The method of claim 11,
Wherein the lookup table comprises a rotation factor lookup table for outputting one or more rotation factor addresses corresponding to the value output from the counter; And a butterfly look-up table for outputting a plurality of butterfly input addresses corresponding to the value output from the counter,
Wherein the address generator further includes a register for outputting a plurality of butterfly output addresses delaying the plurality of butterfly input addresses,
And transfers the one or more rotation factor addresses and the plurality of butterfly input addresses to the memory as the plurality of read addresses and transfers the plurality of butterfly output addresses to the memory as a plurality of write addresses. 12. The method of claim 11,
The MAC unit includes first to fourth MAC circuits as the plurality of MAC circuits,
The first MAC circuit multiplies the first MAC input and the second MAC input,
The second MAC circuit multiplies the third MAC input and the fourth MAC input,
The third MAC circuit multiplies the fifth MAC input and the sixth MAC input,
The fourth MAC circuit multiplies the seventh MAC input and the eighth MAC input,
Wherein the arithmetic unit outputs the first to fourth MAC outputs as the one or more MAC outputs,
The first MAC output corresponds to a value obtained by adding the output of the first MAC circuit to the ninth MAC input and subtracting the output of the second MAC circuit,
The second MAC output corresponding to subtracting the output of the first MAC circuit to the ninth MAC input plus the output of the second MAC circuit,
The third MAC output corresponds to a value obtained by adding the output of the third MAC circuit to the tenth MAC input plus the output of the fourth MAC circuit,
And the fourth MAC output corresponds to a value obtained by subtracting the output of the third MAC circuit from the tenth MAC input minus the output of the fourth MAC circuit. 17. The method of claim 16,
Wherein a real value of a first butterfly input from among the plurality of butterfly inputs is passed to the ninth MAC input,
An imaginary value of the first butterfly input is passed to the tenth MAC input,
Wherein a real value of a second butterfly input from among the plurality of butterfly inputs is passed to the first and fifth MAC inputs,
An imaginary value of the second butterfly input is passed to the third and seventh MAC inputs,
Wherein a real value of one of the one or more rotation factors is passed to the second and eighth MAC inputs,
And an imaginary value of the one rotation factor is transmitted to the fourth and sixth MAC inputs. 18. The method of claim 17,
Wherein the first MAC output corresponds to a real value of a first one of the plurality of butterfly outputs,
The second MAC output corresponding to a real value of a second butterfly output of the plurality of butterfly outputs,
Wherein the third MAC output corresponds to an imaginary value of the first butterfly output,
And the fourth MAC output corresponds to an imaginary value of the second butterfly output. 12. The method of claim 11,
Further comprising a controller for storing initial FFT inputs in said memory and for driving said address generator after storing a plurality of butterfly input addresses in said address generator.

Images