KR19990078452A - Embedded dram with noise protecting shielding conductor - Google Patents

Abstract

The shielding conductors are spaced apart from the matrix of memory cells in a dynamic random access memory (DRAM) to shield the memory cells from noise signals such as noise generated by components of the system level integrated circuit (SLIC). Shielding conductors spread out the noise effects and maintain an even reference potential with respect to the DRAM components being overlaid or connected. The shielding conductor includes a plurality of conductors that are connected in an intersecting manner to form a mesh that substantially overlays the entire matrix. The mesh is connected to components such as insulating wells or capacitor reference potential conductors at multiple spaced locations throughout the entire matrix. The shielding conductor may also be a single integral conductor that overlays the entire matrix including the bit and word lines.

Description

Built-in dynamic random access memory with anti-noise shielded conductor {EMBEDDED DRAM WITH NOISE PROTECTING SHIELDING CONDUCTOR}

DETAILED DESCRIPTION The present invention relates to dynamic random embedded in silicon chips as part of an integrated circuit (IC), such as an application specific integrated circuit (ASIC), a mixed signal ASIC, or a system level integrated circuit (SLIC). An access memory (DRAM). In particular, the present invention relates to a newly improved DRAM with internal protection means against the adverse effects of spurious electrical signals or "noise". Internal noise protection is when DRAM is embedded in a SLIC with noisy integrated circuit elements, when the SLIC with embedded DRAM is used with external noisy elements, or when the SLIC is frequently affected from radiation alpha particulates, etc. Increasing the DRAM's ability to supply accurate data.

DRAM is a memory element that holds and supplies information for use with electronic digital computing and logic elements such as microcontrollers, microprocessors, logic arrays, and the like. ASICs or SLICs are single ICs containing a combination of various electronic components such as microcontrollers, microprocessors, logic gates, resistors, amplifiers, linear circuit elements, etc., and are selected, connected, and integrated to perform specific functions for specific applications. do. Examples of SLICs include controllers for computer memory disk drivers, graphics controllers, LAN switches, fuel injection control systems for internal combustion engines, position tracking systems (GPS), and control devices for a wide range of consumer products. SLICs are desirable for use in high volume products because of the functionality that can be obtained at a very low cost. This type of SLIC is referred to as a "system on a chip" because of the complete functionality obtained from a single chip or IC.

Only recently have DRAMs been "embedded" or merged as part of SLIC. Previously, if SLIC needed a memory function, a separate memory or DRAM chip had to be provided on a printed circuit board (PCB). Embedding DRAM on the SLIC chip avoids the extra cost of a separate memory chip. Since separate DRAM chips have significant cost and memory size, it is desirable to avoid separate DRAM chips when SLIC itself requires a small amount of memory. Even when more memory is actually needed, memory consolidation on a single SLIC chip is less expensive than purchasing a separate DRAM chip.

A typical DRAM is formed of thousands of individual memory cells arranged in a matrix configuration and formed on the substrate of the SLIC. Each DRAM cell includes a capacitor that is electrically charged or discharged in a "write" operation. Charge creates a voltage in the capacitor, and the voltage level represents a bit of data. The data bits represented by the capacitor charge are determined by comparing the capacitor voltage with a reference threshold. The voltage level that must be sensed to make the data bit level in the DRAM is relatively small, for example 50 to 100 millivolts, and level differences of less than 50 millivolts differ between accurate and inaccurate data bit measurements. It may have consequences.

Memory cells of the DRAM matrix are addressed by signals supplied on word lines and bit lines. The word line extends in the horizontal reference direction in the matrix and is connected to the memory cells in the horizontal row and intersects the vertical column of memory cells in the matrix. The bit lines extend in the vertical reference direction in the matrix, are connected to the memory cells in the vertical column, and cross the horizontal rows of the cells. By applying a voltage to the selected word line, the voltage from the memory cells in the horizontal row corresponding to the selected word line appears in the bit line that is determined in each cell.

DRAM memory arrays are generally divided into one or more segments, each segment being further divided into bit blocks. Each bit block has a number of memory cells, which are organized into rows and columns of a matrix. Each word is selected by addressing a DRAM segment, selecting each column in the bit block, and selecting the desired word line.

The disadvantage of embedding DRAM in a SLIC is that noise from other logic components of the SLIC can degrade the performance of the DRAM. Other logic and integrated circuit components continuously switch between conductive and nonconductive states, and lead bonds that connect their components, conductors throughout the SLIC, the substrate of the SLIC, and the SLIC chip to external components. ) And the flow of current in the external component itself starts and ends. In general, when the current flow suddenly stops, electrical spikes or pulses ripple through the circuit components on the SLIC substrate due to the electrical inductance of the associated circuit elements. The voltage pulse may be sufficient for the voltage on the substrate to fluctuate or "bounce". The voltage bounce can reach up to 1V and damage the bit line signals and data stored in some memory cells. In particular, when the memory cell capacitor discharges on the bit line, the typical voltage on the bit line is much smaller than the voltage present on the memory cell capacitor because of the larger bit line capacitance compared to the memory cell capacitor. Typical memory cell capacitor voltages range from 1 to 3V, while typical bit line voltages range from tens or hundreds of mVs. With such low bit line voltages, substrates affected by relatively large voltage bounces make it impossible and difficult to accurately sense the bit line voltages.

Noise effects in DRAM can occur, especially when an external device induces a large amount of current, due to the connection between the SLIC and a device external to the SLIC on the printed circuit board. Transient currents conducted through lead bonds and other conductors can generate voltage pulses due to the inductance of the current conducting elements. For example, an external data bus is typically connected to the SLIC and reads data bit signals over the bus. The read process can induce a large amount of current in a very short time. As a result, current surges generate voltage pulses that adversely affect DRAM performance.

In order to avoid noise problems, several approaches have been studied. One approach is to determine when noise occurs and perform a DRAM read operation only during a stable time. Since most operations in a simple system are controlled by clock pulses, it is possible to predict when some functional operation will occur and generate noise. However, this approach is not practical in most complex SLICs because multiple clocks are used to control other components of the SLIC. Determining when noise occurs consistently requires that multiple clocks be synchronized, which is either impossible or impractical in practice. Also, given the many operations that SLIC should perform based on continuity, a significant number of operations may not exist for a sufficient long period of time to enable satisfactory DRAM operation.

Another approach to avoid noise problems is an attempt to find a substantially noise free location on the SLIC substrate for DRAM. However, a location that is not affected by noise does not exist in most SLICs. Because each SLIC chip is generally different in configuration and layout, the location of the DRAM in the SLIC varies from one SLIC chip to another. Each SLIC is for a different specific application and uses different elements to accomplish its different functions. Thus, a stable position on one SLIC chip may not be a stable position on another SLIC chip.

Another approach to reduce the effects of noise on DRAMs is to use biasing techniques. Because the voltage of each memory cell must be compared to the threshold voltage to determine whether the data bit is high or low, some amount of noise reduction change in the sensed voltage is caused by adjusting or biasing the threshold voltage. Are accepted. However, the bias is inevitable because the noise from the large voltage bounce on the substrate is too large compared to the bit line voltage. Often, the entire substrate is biased to reduce the effect of noise caused by voltage bounce. The substrate is typically connected to a negative voltage power supply. By having the substrate at a negative voltage, the voltage fluctuations can less affect the data signals stored in the memory. Substrate voltage variations usually result in uneven voltage distribution and voltage differential across the substrate. Non-uniform voltage distribution affects the signal of the bit line to a different degree depending on the position of the bit line relative to the position of the voltage differential on the substrate. In this environment, biasing the entire substrate does not compensate for voltage differential. For these and other reasons, the different physical locations of the DRAMs of each SLIC's unique noise-environment chip, and the different external components to which the SLIC chip can be connected, make biasing techniques inefficient in solving noise problems. .

Another source of data loss in DRAM is alpha particles. Alpha particles are high-energy cosmic rays that are somewhat natural in the environment. Alpha particles often pass through the substrate of the SLIC and create small clouds or wakes of positive and negative charge carriers (holes and electrons). Some of these charged carriers, in combination with the charge in the memory cell capacitors, discharge the capacitors, corrupting the data stored in the cells. This state creates so-called "soft-errors" because the cells have not been permanently damaged but lost stored data due to the effects of alpha particulates.

The present invention relates to these and other considerations for noise in DRAM embedded in SLIC.

One improvement of the present invention relates to a DRAM configuration embedded in SLIC that obtains a relatively high level of noise immunity and protection from various types of other noise sources. Other improvements relate to increasing the immunity of embedded DRAM to substrate voltage bounce, voltage differential across the substrate, external switching current flow effects and noise generated by transients and the operation of other electrical elements in the SLIC. These are made substantially independent of the location of the DRAM embedded in the substrate of the SLIC. Another improvement relates to increasing the immunity of embedded DRAM to noise and signal degradation caused by alpha particulates. Another improvement is to obtain these and other improvements while embedding DRAM in SLIC, which should in principle be manufactured using semiconductor logic manufacturing processes, rather than refined DRAM fabrication for that purpose.

These and other improvements are obtained in a DRAM segment that includes a plurality of memory cells formed in a matrix on a substrate of an integrated circuit. Improvements relate to logical complementary pairs of charge storage capacitors that produce data bit signals in each cell by the relative charge difference stored in the capacitors. The adverse effect of noise is reduced or eliminated because the noise affects both the complementary capacitor as well as the complementary bit line connected to the capacitor. Differential sensing of the bit lines also avoids the effects of noise.

Further preferred aspects of the present invention also improve noise immunity of memory cells. Each memory cell includes a charge storage capacitor to create a data bit signal in each cell. The improvement is for shield conductors spaced apart from the matrix of memory cells to shield the memory cells from signals, ie noise signals, which are mainly challenged by other components of the integrated circuit. The shielding conductor is preferably connected to one of a reference or potential source that is connected to the outside of the DRAM segment. The shielding conductor distributes the effect of noise on the overlaying or connecting DRAM components and maintains an even reference potential.

The following additional preferred aspect of the present invention improves the noise immunity of the memory cell. The shielding conductors comprise a plurality of individual conductors which are connected in cross with each other to form a mesh that substantially overlays the entire matrix. The mesh is connected to at least one component of the DRAM segment at a plurality of spaced locations substantially throughout the entire matrix. The DRAM component to which the mesh can be connected is, among others, a capacitor reference potential conductor connected to a reference potential plate of an electrically isolated well or memory cell capacitor formed in the substrate. One or more meshes may be included in a DRAM, each connected to its own DRAM component. The shielding conductor overlays the entire matrix and may be a single complete conductor comprising bit and word lines. The noise shielding improvement of the present invention is particularly useful when a matrix of memory cells is embedded in the SLIC, and some conductors of multiple interconnect layers of the SLIC, such as data and address bus conductors, and power supply conductors, are shielded from the memory cell. It is located opposite the conductor.

A more complete understanding of the invention and its scope can be obtained by reference to the accompanying drawings, detailed description of preferred embodiments of the invention, and claims.

1 is an explanatory diagram of an overall layout independent of a scale or ratio representing a typical SLIC with embedded DRAM incorporating the present invention, and a block diagram of external components used with the SLIC.

FIG. 2 is an exploded perspective view of a portion of the embedded DRAM shown in FIG. 1 (where, for illustrative purposes, some individual portions are shown at different rates than other individual portions). FIG.

FIG. 3 is a circuit diagram of two memory cells of the embedded DRAM shown in FIG.

4 is a block diagram of a cross-coupled sense amplifier connected by bit lines extending from the memory cell shown in FIG.

FIG. 5 is a plan view of two memory cells of the embedded DRAM shown in FIG. 2 structurally corresponding to the circuit diagram elements shown in FIG.

Figure 6 is an enlarged cross sectional view taken substantially in the plane of lines 6-6 in Figure 5;

Figure 7 is an enlarged cross sectional view taken substantially in the plane of lines 7-7 in Figure 5;

FIG. 8 is an enlarged cross sectional view taken substantially in the plane of lines 8-8 in FIG. 5; FIG.

* Explanation of symbols for main parts of the drawings

20: SLIC 22: Chip

28: positive voltage power supply 30: stable positive voltage power supply

34: negative voltage power supply 36: stable negative voltage power supply

A system level integrated circuit (SLIC) 20 incorporating the present invention is shown in FIG. 1 in the form of not-to-scale and not-to-proportion. SLIC 20, which does not incorporate the present invention, is conventional. SLIC 20 is formed as an integral unit in silicon die or chip 22. The silicon chip 22 includes a P-type substrate 24 on which functional components of the SLIC are formed. The pads 26 are formed outside of the chip 22, and have a positive voltage (Vdd) power supply 28, a "quiet" positive voltage power supply 30, a negative voltage (Vss) An external electrical conductor comprising a power supply 34 and a stable negative voltage power supply 36 is connected to the package pin 26 via a lead bond. Pad 26 is connected to various functional components of SLIC 20 by conductors (not shown). The functional components of the SLIC are interconnected by the conductor 38 in the form of conventional buses and bus conductors. Functional components vary with SLIC, but in general, these components are, for example, processor 40, read-only memory (ROM) 42, logic array 44 as well as other known digital or analog components. ) And register 46.

The dynamic random access memory (DRAM) array 48 is embedded in the substrate 24 of the SLIC 20. Embedded DRAM array 48 is preferably formed of a number of separate DRAM segments 50 (four DRAM segments shown in FIG. 1). DRAM segments 50 are interconnected by electrical conductors in the DRAM array. DRAM array 48 is interconnected with other components of SLIC 20 in a conventional manner by a bus formed of conductor 38. In addition, bus conductor 38 is coupled to other components of the SLIC and includes a processor 40 and various other components 42, 44, 46, and the like. In general, the number, type and layout or arrangement of specific SLIC components in the chip 22 will vary depending on the application of the different SLICs.

As shown in FIG. 2, each DRAM segment 50 is formed of a plurality of memory cells 54 formed on the substrate 24 in a matrix-like configuration 56. As shown in FIG. Although the configuration of some memory cells may differ slightly from other memory cells 54 in order to allow the entire segment 50 of cell 54 to be configured in matrix 56 in a space efficient manner. Each memory cell 54 is a copy of another memory cell. Memory cells 54 in matrix 56 are arranged in horizontal rows and vertical columns.

The memory cell of each DRAM segment 50 is divided into bit blocks, two of which are shown in FIG. Each bit block 55 is formed of a predetermined number of columns of memory cells 54. The number of rows and columns of memory cells in each bit block varies, but for example 265 columns and 32 rows can be usefully considered. Thus, in this example each bit block will contain 8K data bits. Reading or writing is done by applying voltage to the selected word line, selecting the desired column of the bit block, and reading or writing data bits from the intersected addressed column and the selected column.

As shown in Figs. 3 and 5, each DRAM memory cell 54 is preferably formed of two field effect transistor (FET) -capacitor combinations 58t and 58c. Using two transistor-capacitor combinations 58t, 58c as each memory cell 54 allows differential sensing of the bit line voltage, which is beneficial to prevent the effects of noise. As with many other elements associated with the DRAM cell 54 described herein, the two transistor-capacitor combinations operate in a logical complementary to each other and are true ("t") and complementary to each other. ("c"). However, if differential sensing is not desired, other improved aspects of the present invention can be implemented by using only a single transistor-capacitor combination as each DRAM cell 54, which combination is common in DRAM.

As shown in FIG. 3, each transistor-capacitor combination 58t, 58c from an electrical circuit perspective includes P-channel transistors 60t, 60c connected in series with capacitors 62t, 62c, respectively. As shown in FIG. 2, one plate of each capacitor 62t, 62c is connected to a capacitor reference potential conductor 63 extending in the horizontal reference direction across the substrate 24. . As schematically shown from an electrical point of view in FIG. 3, and also from a structural point of view in relation to FIG. 5, horizontally extending capacitor reference potential conductors 63 are vertically adjacent in each vertical column. The two memory cells 54 overlap. From a structural point of view, the capacitor reference potential conductor 63 is wide enough to function as the reference potential plate of the capacitors 62t and 62c of the vertically adjacent pair of memory cells 54. In the preferred embodiment described herein, the capacitor reference potential conductor 63 extends between adjacent horizontal rows of the memory cells 54 in all bit blocks of the DRAM segment, and has an external stable negative voltage power supply 34 ( 1). In other embodiments of the DRAM, the capacitor reference potential conductor 63 may be connected to another potential or reference source.

The drain terminal of the transistor 60t is connected to one bit line 64t, and the drain terminal of the transistor 60c is connected to the other bit line 64c. As shown in FIG. 2, the bit lines 64t and 64c extend vertically in the matrix 56. As shown in FIG. Each complementary bit line set 64t, 64c is connected to all transistors 60t, 60c in individual vertical columns of the cell 54. Thus, each separate column of cell 54 has its own complementary bit line set 64t, 64c.

As shown in Figure 3, the gates of transistors 60t and 60c are typically connected to a single word line 66. 2, each word line 66 extends horizontally across the matrix 56. As shown in FIG. Each word line is connected to the gates of transistors 60t and 60c of all memory cells 54 in each horizontal row of memory cells of matrix 56. Thus, each horizontal row of memory cells 54 has its own word line 66.

DRAM memory cell 54 stores data "bits". Data bits are the fundamental elements of data that are recognized by logic elements and are high or low and are usually described as "0" or "1". "1" and "0" are combined to form a binary word or code representing useful data. Capacitors 62t and 62c store charge to represent data bits. Since capacitors 62t and 62c are complementary in each memory cell, charge is stored in either capacitor while the other capacitor is discharged. The voltage from each capacitor is associated with the stored charge.

Transistors 60t and 60c connect or disconnect capacitors 62t and 62c to bit lines 64t and 64c. The bit line is connected to a write amplifier and a sense amplifier located at the vertical terminal end of the bit line extending across the memory matrix 56 (see FIG. 2). When capacitors 62c and 62c are connected to a sense amplifier, the voltages of bit lines 64t and 64c generated by the charge of the capacitor are sensed to "write" the data bits held by memory cell 54. Memory cell capacitors are charged and discharged by conducting current from the write amplifier through transistors 60t and 60c along the bit lines to charge or discharge capacitors 62t and 62c to " write " data in the memory cells. Is done.

A voltage is applied to the word line 66 to access each cell 54 in the horizontal row in the block of bits for reading or writing. Voltage from word line 66 causes transistors 60t and 60c of all memory cells 54 in the horizontal row of the matrix to be in a conductive state. When the transistors 60t and 60c are in the conductive state, the read or write operation may be continued for the memory cells in the horizontal row.

During the read operation, the voltage present on capacitors 62t and 62c is transferred to bit lines 64t and 64c because transistors 60t and 60c are in a conductive state. Because the bit line is physically larger than the plate of the memory capacitor, the voltage present at the bit line is significantly less than the voltage at the memory cell capacitor before the memory cell capacitor is connected to the bit line. This factor makes it more difficult to detect the bit line voltage because memory cell voltages in the range of several volts (V) appear in tens of millivolts (mV) in the bit line.

As shown in Fig. 4, after the memory cell capacitor voltage is applied to the bit lines 64t and 64c, the differential sense amplifier 67 is enabled by the signal supplied at " 69 ". As shown in the figure, the sense amplifier 67 is formed as a cross-coupled inverter. The voltages of the capacitors 62t, 62c (FIG. 3) are initially applied to the input of the cross-coupled inverter. In response to this initial small signal differential, the cross-coupled inverter amplifies the difference until the signal on the bit lines 64t, 64c becomes larger, which is almost the maximum differential available from the cross-coupled inverter. Thus, the cross-coupled inverter sense amplifier 67 amplifies the initial small signal differential at the bit line signal level to the signal level of the larger signal differential, and these amplified signals may be transferred to other parts of the DRAM such as a latch (not shown). Applied to logical elements.

The use of two capacitors 62t and 62c and two bit lines 64t and 64c for each memory cell 54 and the use of differential bit line sensing, more than the traditional DRAM configuration of a single capacitor and bit line per memory cell Great noise immunity is obtained. The cell data level in a single capacitor and bit line per memory cell is determined by comparing the voltage level of the bit line with the threshold voltage level. The impact from noise can change the bit line voltage level relative to the threshold level, thus hampering the accurate determination of the data bit signal level in the memory cell. In differential sensing, the noise will affect the signal levels of the bit lines 64t, 64c evenly, and the differential voltage level sensed by the sense amplifier 67 will not be altered by the noise. In conclusion, noise does not hinder the determination of the data level of the memory cell.

The structural shape of the memory cell 54 is shown in Figs. As shown in Fig. 5, the transistor-capacitor combinations 58t and 58c are formed in a rectangle extending vertically. Bit lines 64t and 64c extend over transistor-capacitor combinations 58t and 58c. Gate conductor 70 connected to the word line extends transversely across a number of transistor-capacitor combinations 58t, 58c that form all of the memory cells in a row of bit blocks. Capacitor reference potential conductor 63 overlays adjacent portions of transistor-capacitor combinations 58t, 58c of two cells 54 that are vertically adjacent in two horizontal rows of cells. Bit lines 64t and 64c and gate conductor 70 are connected to the elements of each memory cell 54 in the manner shown and described with reference to FIGS. 6 and 7.

As represented by the transistor-capacitor combinations 58t, 58c shown in FIG. 6, transistor-capacitor combinations 58t, 58c are formed in the N-well 68 of the substrate 24. As shown in FIG. N-well 68 is preferably produced in a conventional manner on the substrate by implantation and diffusion. The N-type material is first implanted to a predetermined depth in the region of the P-type substrate 24. At this time, the implanted N-type material is diffused in a thermal process and generates N-wells up to a predetermined depth. Preferably the N-well 68 is large enough (in terms of depth, length and width) to accommodate all the memory cells 54 of all DRAM segments 50. However, one or more N-wells 68 may be required to accommodate all cells 54 of the DRAM segment 50.

P-channel transistor 60t is typically made by implanting or diffusing a P-type material in N-well 68 to form P-type drain and source regions 72 and 76. Channel region 74 will exist between source and drain regions 72 and 76. P-type channel region 78 is formed extending from source region 76. Channel region 78 forms a charge plate of capacitor 62t that is coupled to transistor 60t (FIG. 3). As shown in Figure 6, the portion of the capacitor reference potential conductor 63 that overlays the P-type channel region 78 forms another reference potential plate of the capacitor 62t. Between the capacitor plate P-type channel region 78 and the overlying conductor 63, a very thin nonconductive oxide layer 79 (FIG. 6) forms a dielectric for the capacitor 62t. After the channel region 78 is formed and before the capacitor reference potential conductor 63 is formed, an oxide layer 79, preferably silicon dioxide, grows on the top surface of the channel region 78.

An oxide layer 79 of the capacitor dielectric is formed simultaneously with the gate oxide of the transistor deposited between the region 74 and the gate conductor 70. Using oxide layer 79 as the capacitor dielectric allows standard logic fabrication processes to be used to fabricate embedded DRAM. As in the case where DRAM integrated circuits are fabricated on separate chips, no special processes are required to form the memory capacitors. Using the DLAM process to manufacture SLICs is difficult to achieve at low cost, because most SLICs make up logic components, or components that are more equivalent to logic components than special DRAM structures. In conclusion, a standard logic fabrication process that already requires the use of an oxide layer 79 to form the gate of the transistor allows the memory capacitors to be fabricated simultaneously in SLIC without adding complexity. In conclusion, DRAM memory capacitors are effectively embedded in SLIC.

Gate conductor 70 (FIGS. 3 and 5) is formed horizontally over channel region 74 to create the gate of transistor 60t. Preferably both the gate conductor 70 and the capacitor reference potential conductor 63 are simultaneously formed of polysilicon. Thereafter, an insulating layer 80 is applied to cover the gate conductor 70 and the capacitor reference potential conductor 63.

The capacitor 62t is charged when a positive carrier (hole) is conducted to the channel region 78 of the N-well extending in the region 76 of the transistor 60t. The channel region 78 immediately charges or discharges a positive carrier (hole) when the transistor 60t is biased into a conductive state in accordance with a signal applied to the gate conductor 70. Transistor 60t is biased into a non-conductive state after channel region 78 is charged or discharged. Channel region 78 tends to retain charged carriers after the transistor is in an unconductive state. However, junction leakage currents and channel leakage currents generate small but significant currents that are easy to change the charge stored in channel region 78. Because of these currents in a typical DRAM, memory cell capacitors must be repeatedly refreshed at approximately 1-2 ms intervals. Cell refreshing involves reading a memory cell and rewriting a signal read from the memory cell. The rewrite operation supplies the leakage current and the charge consumed by the read operation since the last refresh operation.

As shown in Figs. 6 and 7, the bit lines 64t and 64c are formed on the upper surface of the insulating layer 80. Figs. The bit lines 64t and 64c are preferably formed of a first metal layer positioned over the insulating layer 80 over the polysilicon layer used to form the conductors 63 and 70. As shown in Figures 5 and 6, the bit lines 64t, 64c generally extend parallel to the length of the rectangular transistor-capacitor combinations 58t, 58c. Bit lines 64t and 64c are connected to drain regions 72 of transistors 60t and 60c by extension posts 82 of the underlying bit line material in contact with drain region 72.

N-well 68 is connected to positive voltage conductor 84 at multiple spaced intervals. As shown in FIG. 7, in order to apply a positive voltage to the N-well 68 in a stable positive voltage power supply 30 (FIG. 1), the N ⁺ region 86 is preferably (not shown) The N ⁺ region of another transistor formed in a manner similar to the N ⁺ region of the transistor and complementary to the P channel transistors 60t and 60c is formed in SLIC. As shown in FIG. 2, the conductor 84 extends vertically in a matrix 56 parallel to the rows of memory cells. Preferably one conductor 84 extends perpendicularly across each transverse axis of each bit block 55. In other words, vertical conductors 84 are present on each side of each bit block 55.

As shown in FIG. 7, a positive voltage conductor 84 extending vertically after the insulating layer 80 is placed is formed on top of the insulating layer 80. As shown in FIG. A vertically extending positive voltage conductor 84 is located in the first metal layer of the DRAM segment along the bit lines 64t and 64c. The extension post 88 in the conductor 84 extends through the hole in the insulating layer 80 and contacts the N ⁺ region 86.

Next, the insulating layer 90 is placed, and a horizontally extending voltage conductor 92 is formed on the top of the insulating layer. The horizontal power supply conductor 92 is located in the second metal layer of the DRAM segment 50. The extension post 94 in the conductor 92 connects both conductors 84 and 92 by extending downward through holes formed in the insulating layer 90 in contact with the conductor 84.

The horizontally oriented positive voltage conductor 84 is connected intersecting with the positive voltage conductor 92 extending horizontally at spaced intervals created by the location of the extension post 94 throughout the matrix of memory cells. In particular, one horizontal conductor preferably extends at two vertically adjacent events in the memory cell. In other words, one horizontal conductor exists for each pair of horizontal rows in the memory cell.

The crossing conductors 84, 92, spaced in this manner, form a mesh 96 of vertically intersecting positive voltage conductors extending across the DRAM segment 50. Mesh 96 is connected to N-well 68 at multiple intervals made by the location of extension post 86 (FIGS. 5 and 7). A stable positive voltage power supply 30 (FIG. 1) is connected to the mesh 96. Multiple amount of dispersion connected by a large post N 88 to a large single N-well 68 or a large number of small N-wells 68 (including fewer than all memory cells in a DRAM segment) at multiple periodic intervals. Because of the voltage conductors 84 and 92, the N-well voltage is maintained at a stable level. The specified effect from noise is prevented due to the reduced inductance of the multiple conductor paths and the multiple connecting conductors 84, 92. The reduced inductance of the mesh 96 provides a reduced impedance for rapidly changing and transitioning currents that are typically challenged by the components of the SLIC, including the substrate. Thus, the reduced impedance of mesh 96 prevents transients from inducing significant voltages in memory cells and bit lines. As a result, signals from memory cells and bit lines are more accurately read and preserved in a stable state.

As shown in Figures 2, 5 and 8, the metal reference conductor 98 extends in parallel with each polysilicon capacitor reference potential conductor 63. The metal reference conductor 98 extends in the second metal layer of the DRAM segment. The reference conductor 98 is connected by an extension post 100 at each end of the capacitor reference potential conductor 63 extending the rows of each bit block 55 (FIG. 2). The extension post 100 extends through holes formed in the insulating layer 80 of the DRAM segment. Also, as shown in FIGS. 2 and 5, the plurality of metal conductors 102 are vertically intersected with the conductors 98 to be connected to form the second mesh 104. Conductors 98 and 102 are conducted by multiple extension posts 103 in the same manner as other conductors are connected as described above. As shown in Fig. 2, the conductor 102 extends in parallel with the conductor 84 side and is laterally displaced to the conductor 84 side. Thus, conductor 102 extends on the opposite side of each bit block 55. Conductor 98 extends directly over the capacitor reference potential conductor 63, and one conductor 98 exists for two rows in the memory cell. Thus, the conductor 102 is located in the first metal layer and the conductor 98 is located in the second metal layer. Mesh 104 and conductors 98, 102 of mesh 104 are connected to a stable voltage power supply 34 (FIG. 1). As shown in FIG. 2, mesh 104 overlays DRAM cells 54 of matrix 56.

As with the mesh 96 connected to the N-well 68, the reduced inductance of a number of distributed and interconnected conductors 98, 102 may cause a wide range of voltage fluctuations in which transients are specified in the reference potential plate of the memory capacitor. Prevent induction. Thus, the mesh 104 maintains an even reference potential voltage for the memory cell capacitor. More uniform reference potential voltages allow memory cells to be charged more smoothly and accurately, allowing more precise voltage levels to be grown. Some memory cell capacitors that do not have the equivalent reference potential voltage provided by the mesh 104 will exhibit more charge accumulation than others under the same charging conditions, especially when subjected to variable and unexpected effects of noise. In conclusion, although the noise effect does not cause voltage fluctuations in the memory cell capacitor, the capacitor reference potential conductor 63 is not perfectly evenly connected to the stable reference potential 34 (FIG. 1) by the mesh 104. Noise effects will cause voltage fluctuations. Thus, the signal stored in the memory cell capacitor more accurately represents the intended data and is read more accurately in the bit line.

5 and 8, a polysilicon gate conductor 70 is connected to a metal word line conductor 66 located in the second metal layer of the DRAM segment 50. As shown in FIG. As shown in FIG. 8, each metal word line 66 is connected by an extension post 106 extending through holes formed in the insulating layer 80 to contact the polysilicon gate conductor 70. The extension post 106 is connected to the polysilicon gate conductor 70 at the beginning of each row of memory cells in the bit block. Periodic connections in the metal word line conductor 66 and the extension post 106 reduce the amount of resistance, but would appear different if the polysilicon gate conductor 70 did not fully extend across the DRAM segment. By removing the substantial amount of resistance in the polysilicon gate conductor 70 using the metal word line conductor 66, the propagation time of the word line signal is reduced to accelerate the DRAM's operational capability.

6 and 7, another insulating layer is placed on top of the conductor 92 and the top of the insulating layer 90 to complete the construction of the DRAM segment. Thereafter, the shielding conductor formed by the integral metal layer 116 is placed on top of the insulating layer 114. The integral metal layer 116 is connected to a stable negative voltage power supply 34 (FIG. 1). Although not shown, additional metal layer conductors separated by an insulating layer may be fabricated on top of the metal layer 116. For example, address bus and power supply conductors may be disposed in these layers over metal layer 116. The integral metal layer 116 shields underlying DRAM components from the effects of noise induced by transient voltages conducted by conductors overlying the metal layer 116. Thus, the metal layer 116 connected to the stable negative voltage power supply 34 (FIG. 1) provides a shield against noise induced from the outside in the DRAM segment 50. As shown in FIG.

Since each memory cell 54 is inevitably isolated from the substrate 24 through the N-well 68, improving the formation of the memory cell 54 in the N-well 68 may result in memory cell 54. Reduces the effect of noise on the When the voltage at the substrate 24 fluctuates or bounces, the mesh 96 reduces the influence of externally induced voltages in the N-well 68. The stable positive voltage power supply 30 (FIG. 1), in which the mesh 96 is electrically connected, is not a printed circuit board (not shown) to which the SLIC (FIG. 1) is connected or any other element in the SLIC. An N-well 68 is inevitably provided to conduct the voltage. No stray transient current is induced in the N-well 68 because no other devices are connected to the stable positive voltage power supply 30. Also, if transient currents appear in the N-well, the low inductance of the mesh 96 prevents voltage induction in the N-well 68, the memory cell 54, and / or the bit line 64. Therefore, the signal detected at the bit lines 64t and 64c is more accurate.

N-well 68 further provides the advantage of reducing the likelihood of error induced in memory cell 54 with alpha particulates or other radioactive material. The substrate 24 is connected to the negative voltage power supply 34 (FIG. 1), and the N-well 68 is connected to the positive voltage power supply 30 (FIG. 1). Since the P-type substrate 24 has most of the positively charged carriers (holes), and the N-well 68 has abundant negatively charged carriers (electrons), the positively charged carriers produced by the alpha particulates do not affect the capacitor charge. It will be eliminated substantially before it affects. The positively charged transient carriers (holes) are conducted by the P-type substrate to the negative voltage power supply 34 (FIG. 1), leaving only the negatively charged carriers (electrons) to migrate from the substrate to the N-well. However, the N-well is connected to a stable positive voltage power supply 30 (FIG. 1), and electrons entering the N-well are connected to a stable positive voltage power supply 30. In this way, only a few holes generated by the alpha particles in the N-well can escape the collection and dissipation, thus substantially reducing the adverse effects of the alpha particles on the DRAM.

In addition, the DRAM segment 50 is not affected by spurious noise because each cell 50 uses two capacitors 62t and 62c to store a charge representing a single bit of data. Comparing the two voltages produced by the charge at the two capacitors 62t, 62c yields a more reliable determination of the data level of the cell than comparing the voltage at the single capacitor and the reference voltage level. Because the two capacitors 62t and 62c are located relatively close on the chip 22, and typically the noise affecting one capacitor affects the other to the same extent, it stores charges representing one data level. Using two memory capacitors 62t and 62c to reduce the effect of noise on DRAM segment 50, but will not hinder the relative voltage difference between the two capacitors. Most of the noise affects both capacitors 62t and 62c substantially equally to maintain the stored charge difference of the two capacitors 62t and 62c.

In addition, the bit lines 64t, 64c which conduct the voltage signals for the complementary memory capacitors 62t, 62c are preferably close to each other with only 1 micron (a micron) in between. Therefore, the induced voltage generated at the bit line 64t will be similar and nearly the same as that derived at the other bit line 64c. Thus, the difference between the two bit line voltages is maintained in the presence of noise. In conclusion, the voltage sensed by the sense amplifier 67 (FIG. 4) yields an accurate signal for reliable sensing and detection. Although the configuration of the memory cell has been described with respect to the structure of the DRAM segment 50, the first, second and third metal layers of the DRAM segment will continue in other components of the SLIC 20.

Improvements available from the present invention are made by using embedded DRAM using standard logic fabrication processes. More complex hybrid manufacturing processes that combine logic and DRAM technology are not required to form SLICs or improve critical DRAM in the environment of DRAMs embedded in SLICs.

Preferred embodiments of the invention have been described in detail. This description is a preferred example for implementing the invention and is not intended to limit the scope of the invention. The scope of the invention is defined by the claims.

Thus, the present invention is created by a component of a system level integrated circuit (SLIC) by using shielded conductors comprising a plurality of individual conductors that are connected and intersecting with each other to form a mesh that substantially overlays the entire matrix. There is an effect that the memory cells can be shielded from noise signals such as noise.

Claims (18)

A dynamic random access memory (DRAM) segment comprising a plurality of memory cells formed in a matrix, wherein each memory cell includes a charge storage capacitor to produce a data bit signal in each cell. A shielding conductor spaced apart from the matrix of memory cells to shield the memory cell from a noise signal; and Means for connecting the shielding conductor to either a reference or potential source DRAM segment comprising a. The method of claim 1, In combination, a substantially sourced stable source feeder DRAM segment further comprising. The method of claim 1, The shielding conductor includes a plurality of individual conductors that cross each other and are connected to each other. DRAM segment. The method of claim 3, wherein The cross-connected conductors form a mesh that substantially overlays the entire matrix. DRAM segment. The method of claim 4, wherein The mesh is connected to at least one component of the DRAM segment at a plurality of spaced locations substantially through the entire matrix. DRAM segment. The method of claim 5, The matrix of memory cells is formed on a substrate of an integrated circuit, and the DRAM segment is A well formed in a substrate and containing said memory cell, said well being of one majority carrier type and said substrate being of another majority carrier type; And And said plurality of electrical connection means extending to said well. The method of claim 6, Each of said charge storage capacitors of said memory cell comprises a reference potential plate, said plurality of electrical connecting means extending to said reference potential plate of said storage capacitors; DRAM segment. The method of claim 7, wherein And a plurality of capacitor reference potential conductors extending across said matrix and connected to said reference potential plates of said storage capacitors of each memory cell, wherein said plurality of electrical connection means comprise said capacitor reference. Extending to the potential conductor DRAM segment. The method of claim 8, The conductors of the mesh being crossed and connected are metal and the capacitor reference potential conductors are polysilicon DRAM segment. The method of claim 5, Each memory cell further includes a word line and at least one bit line coupled to the memory cell, wherein the mesh also overlays the bit and word lines. DRAM segment. The method of claim 1, The shielding conductor comprises a single integral conductor DRAM segment. The method of claim 11, The shielding conductor substantially overlays the entire matrix. DRAM segment. The method of claim 12, Each memory cell includes a word line and at least one bit line coupled to the memory cell. DRAM segment. The method of claim 12, The shielding conductor includes an integral metal layer DRAM segment. The method of claim 14, The matrix of memory cells is embedded in a system level integrated circuit (SLIC), wherein the SLIC includes a plurality of metal conductive layers, Some of the conductors are located in at least one metal layer spaced from the memory cell opposite the integral metal layer shielding conductor. DRAM segment. The method of claim 15, The conductors of the one metal layer are part of a bus that conducts electrical signals to and from the DRAM segment. DRAM segment. The method of claim 15, The conductor of the one metal layer conducts power to the DRAM segment. DRAM segment. The method of claim 1, Each memory cell includes a transistor and a capacitor connected to and from the charge to and from the memory cell capacitor, the memory cell capacitor being formed simultaneously with the gate of the transistor between the plates of the capacitor. material DRAM segment.