KR19990076102A - Static semiconductor memory device operates at high speed under low power supply voltage - Google Patents

Abstract

As a bit line load element for reducing the bit line amplitude at the time of data reading, a parallel connection of a p-channel MOS transistor and an n-channel MOS transistor is used. When the word line is driven in the selected state, the p-channel MOS transistor is kept off. At the time of data writing, the n-channel MOS transistor and the p-channel MOS transistor are simultaneously driven off. Even under a low power supply voltage, a bit line amplitude of sufficient magnitude can be generated without being affected by the size of the bit line load element. In addition, by setting the bit line load element at the time of data writing in an inactive state, it is possible to prevent the generation of a DC current at the time of data writing.

Description

Static semiconductor memory device operates at high speed under low power supply voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to static type semiconductor memory devices that operate stably at high speeds even under low power supply voltages. More specifically, it relates to the configuration of a bit line load circuit and a data read circuit of this static semiconductor memory device.

1 is a diagram schematically showing the configuration of main parts of a conventional semiconductor memory device. In Fig. 1, the semiconductor memory device is arranged in correspondence with a plurality of static random access memory cells (SRAM cells) SMC arranged in a plurality of rows and a plurality of columns, and each row of the memory cells, A plurality of word lines WL connected to the SRAM cell SMC and a plurality of pairs of bit lines BL and / BL connected to each column of the SRAM cell SMC and connected to the SRAM cell SMC in the corresponding column are included. 1 representatively shows SRAM cells SMC arranged in two rows and two columns. Word lines WL0 and WL1 are arranged respectively in correspondence with each row, and bit line pairs BL0, / BL0 and BL1, / BL1 are arranged in correspondence with each column.

The semiconductor memory device further includes bit line pairs BLP0, BLP1,... Corresponding to the column selection signals Y0, Y1. Column select gates CG0, CG1... And bit lines BL0, / BL0, BL1, / BL1... A bit line load circuit LK is provided correspondingly to the bit line load circuit LK which maintains each bit line potential at the power supply voltage Vcc level during the standby cycle and limits the amplitude of the corresponding bit line during data reading.

Column select gates CG0, CG1... Each of the circuits includes an n-channel MOS transistor T which is connected between each bit line of the corresponding bit line pair and the internal data bus and receives a column selection signal corresponding to the gate thereof. The bit line load circuit LK is provided for each bit line, and includes an n-channel MOS transistor Q whose gate and drain are connected to a power supply node, and whose source is connected to its corresponding bit line. The internal data bus IOB is coupled to the data input / output circuit WRC for carrying data with the outside. Next, the operation of the semiconductor memory device shown in FIG. 1 will be described with reference to the signal waveform diagram shown in FIG.

At time t0, for example, the external address signal extAd at the TTL level changes, and the internal address signal intAd output from the address input buffer (not shown) changes at time t1. The level of the internal signal of the semiconductor memory device is the MOS level. In accordance with this internal address signal intAd, a row decode circuit (not shown) performs a decode operation, and the word line WL for the addressed row is driven in a selected state at time t2. In parallel with the potential rise of the selection word line, the potential of the non-selection word line decreases, and the state shifts from the selection state to the non-selection state. In parallel with this word line selection operation, a column selection operation is performed in accordance with the internal address signal intAd, and a column selection gate provided for the bit line pair corresponding to the addressed column conducts in response to the column selection signals Y (Y0, Y1 ...), The addressed bit line pair is connected to the internal data bus IOB. When the word line WL is driven in the selected state, the storage data of the SRAM cell is read into the corresponding bit line pair BLP (BLP0, BLP1 ...), and the internal data bus IBO is passed through the column select gate in which the potential change on the bit line pair is conductive. The potential of the internal data bus IOB changes at time t3.

When the potential of the internal data bus IOB is stabilized, the sense amplifier included in the data input / output circuit WRC is operated to amplify the signal on the internal data bus IOB, and then read at time t5 through the output buffer circuit included in the data input / output circuit WC. The data DOUT (DQ) is output.

This semiconductor memory device operates statically in accordance with a given address signal and reads data stored in an SRAM cell, thereby enabling high-speed data reading (a standby cycle for precharging a signal line in particular during a memory cell selection operation). Because you do not need to install it).

3 is a diagram illustrating an example of a configuration of an SRAM cell SMC shown in FIG. 1. In Fig. 3, the SRAM cell SMC includes a cross-coupled driver transistor DTa and DTb for storing data in the storage nodes SNa and SNb, and a high resistance load element Za for pulling up the memory nodes SNa and SNb to the power supply voltage Vcc level. And access transistors ATa and ATb for connecting the storage nodes SNa and SNb to the bit lines BL and / BL, respectively, in response to the signal potential on the word line WL and Zb. The driver transistor TDa has a gate connected to the storage node SNb, a drain connected to the storage node SNa, and a source thereof coupled to the ground node. The driver transistor DTb has a gate connected to the storage node SNa, a drain connected to the storage node SNb, and a source connected to the ground node. The access transistors ATa and ATb are constituted of, for example, n-channel MOS transistors, and conduct when the potential of the word line WL is H level (logical high level). Each of the high resistance load elements Za and Zb is made of, for example, polysilicon of high resistance. Next, the data read / write operation of the SRAM cell shown in FIG. 3 will be described with reference to the signal waveform diagram shown in FIG.

When the word line WL is selected and its potential level rises, the access transistors ATa and ATb are turned on, and the storage nodes SNa and SNb are connected to the bit lines BL and / BL, respectively. Now, a case where the data at the H level is stored in the storage node SNa, and the data at the L level is held in the storage node SNb. The bit lines BL and / BL are precharged to the voltage level of Vcc-Vth by the bit line load element Q. Here, Vth represents the threshold voltage of the bit line load transistor Q.

If the memory node SNa is at the H level, the voltage level of the memory node SNa is maintained at the power supply voltage Vcc level by the high resistance load element Za, while the memory node SNb is the ground voltage level, and the driver transistor DTa is in the off state. . Therefore, even when the storage node SNa is connected to the bit line BL through the access transistor ATa, no current flows in the bit line BL, and the bit line BL maintains the level of the precharge voltage level Vcc-Vth.

On the other hand, the driver transistor DTb is in the ON state by the H level data of the storage node SNa, so that a DC current flows from the bit line load transistor Q to the ground node through the access transistor ATb and the driver transistor DTb. This DC current is called a column current, and the voltage level of the bit line / BL is lowered by this current. The voltage level of the bit line / BL is determined by the resistance division of the channel resistance of the bit line load transistor Q and the channel resistance of the access transistor ATb and the driver transistor DTb. As a result, the voltage level of the bit line / BL is lowered by the voltage? V called the bit line amplitude more than the precharge voltage Vcc-Vth. The voltage difference DELTA V between the bit lines BL and / BL is transferred to the internal data bus IOB shown in FIG. 1, amplified by a sense amplifier included in the data input / output circuit WRC, and data is read out.

When one memory cycle is completed, the potential of the word line WL drops to the L level, the access transistors ATa and ATb are turned off, and the memory nodes SNa and SNb are separated from the bit lines BL and / BL. Although the voltage level of the storage node SNb rises at the time of access, when the access transistor ATb is turned off, the storage node SNb is driven to the ground potential level by the driver transistor DTb again. The voltage Vcc-Vth-ΔV of the bit line / BL rises again to the original precharge voltage Vcc-Vth level by the bit line load transistor Q again.

At the time of data writing, the word line WL is selected as in the case of data reading, and the storage nodes SNa and SNb are connected to the bit lines BL and / BL, respectively.

A column current flows to one of the bit lines BL and / BL, and the potential of the one bit line decreases. In this state, by the write driver included in the data input / output circuit WRC shown in FIG. 1, the bit lines BL and / BL are driven to the precharge voltage Vcc-Vth and the ground potential Vss level in response to the write data, respectively. Even if the H level of the write driver output signal is the power supply voltage Vcc level, the voltage level of the H-level bit line is the precharge voltage Vcc-Vth due to the decrease in the threshold voltage at the column select gate CG. Here, it is assumed that the threshold voltages of the transistor T of the column select gate and the bit line load transistor Q are the same magnitude.

FIG. 5 is a diagram showing a path through which a column current flows for one bit line BL (or / BL). The bit line load transistor Q is connected between the power supply node and the bit line BL (/ BL). An access transistor AT and a driver transistor DT are connected in series between the bit line BL and the ground node.

During the standby cycle, the access transistor AT and the driver transistor DT are turned off, and the bit line load transistor Q maintains the bit line BL (or / BL) at the voltage level of Vcc-Vth. Here, the bit line BL (/ BL) has the column select gate CG in the off state and is connected to the power supply node by the bit line load transistor Q.

At the time of memory cell selection, the access transistor AT and the driver transistor DT are turned on at the same time (the gate voltage of the driver transistor DT is set to H level). In this case, column current flows through the transistors Q, AT, and DT from the power supply node to the ground node. The channel resistance of the bit line load transistor Q is Rq, the channel resistance of the access transistor AT is Ra, and the channel resistance of the driver transistor DT is Rd. In this case, the voltage of the bit line BL is given by the following equation.

Vcc-Vth-Vcc Rq / (Ra + Rd + Rq)

It is necessary to make the bit line amplitude ΔV as large as possible for accurate data reading. However, when the level of the power supply voltage Vcc is lowered, the bit line amplitude [Delta] V (paragraph 3 of the above formula) becomes smaller, resulting in a smaller sense amplifier margin, which makes it difficult to accurately read memory cell data.

In the data write operation, the potential of the bit line driven at the L level is only a bit line load transistor Q composed of the n-channel MOS transistor, and is pulled up to the precharge voltage Vcc-Vth level. In order to accelerate the precharge of the bit line after the data write operation and the read operation, it is preferable to increase the size (channel width) of the bit line load transistor Q and increase the current driving force. If the precharge period (recovery period) of the bit line is long, the next access cannot be performed at an early timing, and there is a possibility that data collision occurs on the bit line.

When the size of the bit line load transistor Q is increased to increase the current driving force, the voltage level of the L level of the bit line through which this column current flows is increased by the channel resistance values Ra and Rd of the access transistor AT and the driver transistor DT. Therefore, a voltage difference of sufficient magnitude cannot be generated between the bit lines BL and / BL, and there is a possibility that the sense operation cannot be performed correctly. If the current driving capability is slightly increased without reaching such a state, it may take time until sufficient read voltage (bit line amplitude) is generated, and the activation timing of the sense amplifier may be delayed, thereby making fast access impossible. .

In this case, when the current driving force of the bit line load transistor is increased, the L level bit line is driven to the ground voltage level when the write driver is operated at the time of data writing. Therefore, the bit line load transistor and the write driver can be The flowing DC current becomes large and the problem that consumption current increases arises.

An object of the present invention is to provide a semiconductor memory device capable of stably and rapidly writing / reading data even under low power supply voltage.

Another object of the present invention is to provide a semiconductor memory device capable of precharging bit lines at high speed.

It is still another object of the present invention to provide a semiconductor memory device which operates at a high speed even under a low power supply voltage without increasing the current consumption.

The semiconductor memory device according to the present invention includes a bit line load element which becomes in a non-conductive state during data writing and whose current driving force becomes smaller than in standby during data reading. Each of the bit line load elements includes a p-channel MOS transistor and an n-channel MOS transistor connected in parallel with each other.

By making the bit line load element non-conductive during data writing, the path through which a column current flows in the bit line is cut off, and generation of a direct current during data writing can be prevented. Further, at the time of data reading, the current driving force of the bit line load element is smaller than at standby time, and the voltage level at the L level at the time of data reading can be sufficiently low. Since the p-channel MOS transistor is turned off both during data writing and data reading, the channel width (the ratio of the channel width to the channel length) can be increased, and the bit line recovery at the data writing and after reading can be performed at high speed. There is a number. Further, even under low power supply voltage, the current supply force of the bit line load element is sufficiently small, so that the bit line amplitude of sufficient magnitude can be realized even under the low power supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing a configuration of an array portion of a conventional semiconductor memory device.

Fig. 2 is a signal waveform diagram showing an operation during data reading of a conventional semiconductor memory device.

3 is a diagram showing an example of the configuration of a memory cell of a conventional semiconductor memory device;

Fig. 4 is a signal waveform diagram showing data reading and writing operations of a conventional semiconductor memory device.

Fig. 5 is a diagram showing an electric equivalent circuit diagram of a bit line when reading data in a conventional semiconductor memory device.

Fig. 6 is a diagram schematically showing the configuration of an entire semiconductor memory device as one embodiment of the present invention.

FIG. 7 is a signal waveform diagram showing the operation of the semiconductor memory device shown in FIG. 6; FIG.

FIG. 8 is a diagram schematically showing a configuration of main parts of the semiconductor memory device shown in FIG. 6; FIG.

9 is a diagram schematically showing a configuration of a bit line load control signal generator shown in FIG. 8;

FIG. 10 is a signal waveform diagram showing the operation of the semiconductor memory device shown in FIG. 8; FIG.

FIG. 11 is a diagram showing an example of the configuration of an SRAM cell shown in FIG. 8; FIG.

12A to 12C schematically show a switching operation of a bit line load element in one embodiment of the present invention;

FIG. 13 is a diagram schematically showing the configuration of the main control circuit shown in FIG. 6; FIG.

FIG. 14 is a diagram schematically showing a configuration of a second embodiment of the semiconductor memory device shown in FIG.

FIG. 15 is a timing chart showing the operation of the semiconductor memory device shown in FIG. 14;

FIG. 16 is a diagram showing an example of the configuration of the recording / reading circuit shown in FIG. 6; FIG.

FIG. 17 is a timing chart showing the operation of the write / read circuit shown in FIG. 16; FIG.

FIG. 18 is a diagram schematically illustrating a configuration of a sense amplifier activation signal generator shown in FIG. 16. FIG.

FIG. 19 is a diagram showing a second configuration of a reading section of the recording / reading circuit shown in FIG. 6; FIG.

20 is a timing chart showing an operation of a read circuit shown in FIG. 19;

FIG. 21 is a view showing a third configuration of a reading section of the recording / reading circuit shown in FIG.

FIG. 22 is a timing chart showing an operation of a read circuit shown in FIG. 21;

FIG. 23 is a diagram schematically showing the configuration of the sense amplifier equalization instruction signal generator shown in FIG. 21; FIG.

FIG. 24 is a view showing a fourth configuration of a data reading unit of the recording / reading circuit shown in FIG.

FIG. 25 is a timing chart showing a data reading operation of the semiconductor memory device shown in FIG. 24;

FIG. 26 is a diagram schematically showing a configuration of an output circuit portion of the input / output circuit shown in FIG. 6; FIG.

27 is a diagram schematically showing the configuration of a part related to data recording of the semiconductor memory device shown in FIG.

Fig. 6 is a block diagram schematically showing the overall configuration of a semiconductor memory device according to an embodiment of the present invention. In Fig. 6, the semiconductor memory device comprises a memory cell array 1 having a plurality of static memory cells arranged in a matrix form, a low address buffer 2 for buffering a low address signal supplied from the outside to generate an internal low address signal; Decodes the internal low address signal from the low address buffer 2 and buffers the row selection circuit 3 for driving the word line arranged in the selected state corresponding to the addressed row of the memory cell array 1 and the column address signal from the outside. A column address buffer 4 for generating an internal column address signal, and a column select circuit 5 for decoding the internal column address signal from the column address buffer 4 to drive the addressed column of the memory cell array 1 in a selected state. .

The memory cell array 1 includes word lines arranged corresponding to each row of memory cells and bit line pairs arranged corresponding to each column of the memory cells. The row select circuit 3 includes a row decoder that decodes an internal low address signal, and a word line drive circuit for driving a word line arranged in a selected state corresponding to a row addressed in accordance with a decode signal from the row decoder. The column select circuit 5 includes a decode circuit for generating a column select signal which decodes the internal column address signal from the column address buffer and selects a bit line arranged corresponding to the addressed column.

The semiconductor memory device is also provided in the multiplexer 6 for selecting a pair of bit lines corresponding to the addressed column of the memory cell array 1 and the respective bit lines of the memory cell array 1 in accordance with the column selection signal from the column selection circuit 5, respectively. Bit line load circuit 7 for setting the above in accordance with the operation mode is included. The configuration of the bit line load circuit 7 will be described later in detail. However, in the standby state, each bit line is precharged to the power supply voltage Vcc level, becomes inactive when data is written, and the current supply capability is much smaller. By adjusting the current supply amount of the bit line load circuit 7 in accordance with the operation mode, the bit line amplitude is set to an optimum level even at a low power supply voltage, thereby ensuring high speed and stable operation.

The semiconductor memory device is also coupled to the selection column of the memory cell array 1 through the multiplexer 6, and transmits a data signal between the write / read circuit 8 for writing / reading data and the write / read circuit 8 and the outside. The receiving input / output circuit 9 is included.

The write / read circuit 8 generates complementary data according to the data given by the input / output circuit 9 during data writing, and transfers the complementary data to the pair of bit lines of the selected column through the multiplexer 6. When reading data, the write / read circuit 8 amplifies the memory cell data read through this multiplexer 6 and gives it to the input / output circuit 9.

The semiconductor memory device also receives the address signals from the low address buffer 2 and the low address buffer 4, the input data given from the input / output circuit 9, and the internal write command signal WE i generated in response to the external write enable signal / WE. When the received signals change, the main circuit 10 outputs (activates) the word line activation signal WLE and the sense amplifier activation signal SE, the word line activation signal WLE, and the write enable signal / WE from the outside. The write / read control circuit 11 which generates the write instruction signal WEi and controls the operations of the write / read circuit 8 and the input / output circuit 9, and the bit line load circuit 7 in accordance with the word line activation signal WLE and the internal write instruction signal WEi. And a bit line load control circuit 12 for controlling.

Next, the operation of the semiconductor memory device shown in FIG. 6 will be briefly described with reference to FIG.

When the address signal changes, the main control circuit 10 detects the change in the address signal and maintains the word line activation signal WLE in the active state for a predetermined period at time t0.

In accordance with this address signal, the row select circuit 3 and the column select circuit 5 perform row and column select operations, and the data of the selected memory cell is read on the bit lines BL and / BL. At the time of data recording, the write enable signal / WE from the outside becomes active to instruct data recording at time t1, so that the internal write instruction signal WEi in the write / read control circuit 11 goes up to H level. In response to the activation of the internal write instruction signal WEi, the write / read circuit 8 writes data in the selection column of the memory cell array 1 via the multiplexer 6.

When the word line activation signal WLE is deactivated at time t2, the voltage level of the selected word line is driven in a non-selected state, the column select circuit 5 is also deactivated, and the multiplexer 6 is turned off. In this state, each bit line is precharged to a predetermined voltage (power supply voltage) level by the bit line load circuit 7 in the memory cell array 1.

When the address signal changes again at time t3, the word line activation signal WLE rises to H level, and the selected memory cell data is read on the bit lines BL and / BL. The internal write instruction signal WEi is at L level, and the data read mode is designated. After a predetermined period has elapsed since the word line activation signal WLE rose, the sense amplifier activation signal SE became active for a predetermined period, and the write / read circuit 8 Amplifies the selected memory cell data read through this multiplexer 6 and supplies it to the input / output circuit 9. The input / output circuit 9 buffers the given data to generate external read data.

When the word line activation signal WE is activated, the bit line load circuit 7 reduces its current driving force based on the control of the bit line load control circuit 12.

During data writing, the bit line load circuit 7 is inactive while the write data in the write / read circuit 8 is actually written to the memory cell, i.e. while the word line activation signal WLE and the internal write instruction signal WEi are simultaneously active. Becomes Therefore, at this time, the path through which the DC current flows in the bit line load circuit to the write / read circuit 8 is cut off, thereby reducing the consumption current. When the word line activation signal WLE is deactivated, the driving force of the bit line load circuit 7 becomes large. Therefore, each bit line is precharged at a precharge voltage level at high speed, and recovery of bit line potential can be performed at high speed.

At the time of reading data, the current driving force of the bit line load circuit 7 is reduced in accordance with the activation of the word line activation signal WLE. Therefore, the low level potential of the bit line can be sufficiently low even under a low power supply voltage, and a bit line amplitude of sufficient magnitude can be realized even under a low power supply voltage.

Therefore, in the configuration shown in Fig. 1, by adjusting the current driving force of the bit line load circuit 7 in accordance with the operation mode, it is possible to read the memory cell data with low power consumption and high speed and stability even under low power supply voltage. Hereinafter, the structure of each part is demonstrated.

[Configuration of Memory Cell Array]

FIG. 8 is a diagram showing the configuration of the memory cell array 1 and its peripheral circuit portion of the semiconductor memory device shown in FIG. In FIG. 8, SRAM cells SMC arranged in two rows and two columns are shown as one column. Word lines WL0 and WL1 are arranged corresponding to each row of the SRAM cell SMC, and bit line pairs BLP0 and BLP1 are arranged corresponding to each column of the SRAM cell SMC. Bit line pair BLP0 has bit lines BL0 and / BL0, and bit line pair BLP1 has bit lines BL1 and / BL1.

The multiplexer 6 is provided corresponding to each of the bit line pairs BLP0 and BLP1 and conducts in response to the column selection signals Y0 and Y1, and each of the column select gates CG0 and CG1 connecting the corresponding bit line pairs BLP0 and BLP1 to the internal data bus 8a is respectively provided. In response to the complementary sequence selection signals Y (Y0, Y1) and / Y (/ Y0, / Y1) and connecting the corresponding bit lines BL (BL0, BL1) to the bus line 8aa of the internal data bus 8a. CMOS transmission gate TMb that conducts in response to the transmission gate TMa and the complementary sequence selection signals Y and / Y, and connects the corresponding bit lines / BL (/ BL0, / BL1) to the bus line 8ab of the internal data bus 8a. It includes. By using the CMOS transmission gates TMa and TMb as the column select gates, the H levels of the bit lines BL and / BL are set to the power supply voltage Vcc level, and the larger conductance is compared with that of the column select gate composed of another MOS transistor. The data can be transmitted and received between the selection bit line and the internal data bus 8a at high speed.

The internal data bus 8a is provided with an IO line load circuit 8b for precharging the internal data bus lines 8aa and 8ab to the power supply voltage Vcc level in response to the deactivation of the word line activation signal WLE. The IO line load circuit 8b conducts when the word line activation signal WLE is inactive and has p-channel MOS transistors Pa and Pb that transfer the power supply voltage Vcc to the internal data bus lines 8aa and 8ab.

The bit line load circuit 7 includes a bit line load element 7a provided corresponding to each of the bit lines BL and / BL and whose current driving force (conductance) is controlled in response to the control signal? NZ and the word line activation signal WLE. . The bit line load element 7a conducts when the control signal? NZ is at the H level, conducts when the n-channel MOS transistor NQ for supplying current to the corresponding bit line BL or / BL and the word line activation signal WLE are deactivated. And a p-channel MOS transistor PQ for supplying current to the corresponding bit line BL or / BL. The current supply of the n-channel MOS transistor NQ is much smaller.

Fig. 9 is a diagram showing the configuration of the bit line load control circuit 12 for generating the control signal? NZ. In FIG. 9, the bit line load control circuit 12 includes an inverter 12a for inverting the word line activation signal WLE in the main control circuit 10 shown in FIG. 6, a NOR circuit 12b for receiving the output signals of the internal write instruction signal / WEi and the inverter 12a; And an inverter 12c which inverts the output signal of the NOR circuit 12b to generate the control signal? NZ. The internal write instruction signal / WE is generated by buffering the write instruction signal / WE given from the outside. Therefore, this control signal? NZ is at the L level when the word line activation signal WLE is at the H level, the word line is at the selection state, and the internal write instruction signal / WEi is at the L level, and data writing to the selected memory cell is performed. The n-channel MOS transistor NQ of the bit line load element 7a is driven to the off state.

While the word line activation signal WLE is at the H level, the p-channel MOS transistor PQ of the bit line load element 7a is in an off state. Therefore, when data is written to the selected memory cell at the time of data writing, the MOS transistors NQ and PO of the bit line load element 7a are turned off at the same time, so that only the selected bit line pair receives data and each of the remaining unselected bit line pairs The bit line receives the data of the corresponding memory cell, and the potential of the bit line receiving the L level data is slightly lowered. Next, the operation of the semiconductor memory device shown in FIG. 3 will be described with reference to the operation waveform diagram shown in FIG. 10.

First, the recording operation will be described. If at least one of the signal DTD activated in response to the change of the external write command signal / WE or the input data signal Din, or the address change detection signal ADT generated by detecting a change in the external address signal is activated, the word line enable signal is activated. The WLE is driven in an active state of H level for a predetermined period. In Fig. 10, when the address signal changes, an operation mode in which the word line activation signal WLE is activated for a predetermined period in response to the address change is shown as an example. Word line selection is performed in accordance with the external address signal, and column selection signal Y is changed by the decoding operation by the column selection circuit. The bit line pairs provided corresponding to the selection columns are connected to the internal data bus 8a via corresponding column selection gates CG (CG0 or CG1).

When the word line activation signal WLE is at the H level and the internal write instruction signal WEi is at the H level, the control signal? NZ is at the H level, and the n-channel MOS transistor NQ is turned on in the bit line load element 7a. have. On the other hand, in response to the activation of the word line activation signal WLE, the p-channel MOS transistor PQ of the bit line load element 7a is turned off. The current driving force (size: channel width) of the n-channel MOS transistor NQ is much smaller. In response to the word line activation signal WLE, the IO line load circuit 8b is deactivated, and the precharge to the power supply voltage Vcc level of the internal data bus lines 8aa and 8ab is stopped. Therefore, in the data write mode, before the actual data write, the n-channel MOS transistor NQ included in the bit line load element 7a is in the on state, and the p-channel MOS transistor PQ of the bit line load element 7a and p in the IO line load circuit 8b. The channel MOS transistors Pa and Pb are turned off.

When the external write command signal / WE becomes L level active, and therefore the internal write command signal / WEi becomes L level, the control signal? NZ becomes L level, and the n-channel MOS transistor NQ of the bit line load element 7a becomes It turns off. Therefore, at the time of data writing, both the MOS transistors NQ and PQ of the bit line load circuit and the p-channel MOS transistors Pa and Pb of the IO line load circuit 8b are turned off and the charges charged in the parasitic capacitances of the respective wirings are maintained. It becomes a state. In response to the activation of the internal write instruction signal / WEi, the write driver included in the write / read circuit 8 shown in Fig. 6 is activated, and data is written to the selected bit line pair BLP in accordance with the input signal. At this time, in the internal data bus 8a, the internal data bus lines 8aa and 8ab are driven to the power supply voltage Vcc level and the ground voltage Vss level in accordance with data recording. The signal potentials on the internal data bus lines 8aa and 8ab are transferred on the selection bit line pair BLP through the column selection gate CG provided corresponding to the selection string. Data is written to the selected bit line pair through the CMOS transmission gates TMa and TMb included in the column select gates. In FIG. 10, as an example, the bit line from which the H level data is read maintains the H level of the power supply voltage Vcc level, while the bit line from which the L level data is read is driven to the ground voltage level. At the time of writing this data, the bit line load element 7a is in a non-conductive state, the IO line load circuit 8b is also in an inactive state, and no direct current flows.

When the word line activation signal WLE is inactivated and becomes L level, when the write operation is completed, the control signal? NZ becomes H level, and the MOS transistors NQ and PQ of the bit line load element 7a are simultaneously turned on, and the IO line load circuit The p-channel MOS transistors Pa and Pb of 8b are also turned on. At this time, the select word line is driven in an unselected state. Therefore, the bit line to which the L level data of the ground voltage level is transferred and the internal data bus line are high-speed and are precharged to the power supply voltage Vcc level.

Next, the data reading operation will be described. When reading data, the external write command signal / WE maintains the H level, and the control signal? NZ maintains the H level. Therefore, the n-channel MOS transistor NQ included in the bit line load element 7a remains on. When the address signal changes and the word line activation signal WLE is activated, the p-channel MOS transistor PQ of the bit line load element 7a and the p-channel MOS transistors Pa and Pb of the IO load circuit 8b are turned off. In this state, each bit line is connected to the power supply node through the n-channel MOS transistor NQ of the bit line load element 7a. In the memory cell connected to the select word line, the bit line from which the H level data is read maintains the power supply voltage Vcc level. On the other hand, since the column current flows through the n-channel MOS transistor NQ of the bit line load element 7a in the bit line from which the L level data is read, this voltage level becomes Vcc-Vth-ΔV. Here, Vth represents the threshold voltage of the n-channel MOS transistor NQ included in the bit line load element 7a. The voltage shown on this bit line is transferred to the internal data bus 8a through the CMOS transmission gates TMa and TMb included in the selected column select gate. CMOS transmission gates TMa and TMb deliver voltages without accompanying threshold voltage losses. Therefore, the bus line to which the H-level data is transferred from the internal data bus 8a maintains the power supply voltage Vcc level, while the internal data bus line from which the L-level data is read is driven at a voltage level of Vcc-Vth-ΔV. Subsequently, this internal data bus 8a is amplified by a sense amplifier included in the recording / reading circuit 8 shown in FIG. 6 to read data.

When the word line activation signal WLE becomes L level and the selected word line is driven in an unselected state to complete the data read operation, the p-channel MOS transistor PQ and IO line load circuit 8b included in the bit line load element 7a are included. The p-channel MOS transistors Pa and Pb are turned on, and the bit lines and the internal data bus lines are precharged at high speed to the power supply voltage Vcc level.

FIG. 11 is a diagram illustrating an example of a configuration of the SRAM cell SMC shown in FIG. 6. In Fig. 11, the SRAM cell SMC stores the cross-coupled driver transistors DTa and DTb for holding data of the memory nodes SNa and SNb, and stores the memory nodes SNa and SNb in response to a signal on the word line WL. Access transistors ATa and ATb connected to the BL, respectively, and cross-coupled p-channel MOS transistors PUa and PUb for pulling up the voltage levels of the storage nodes SNa and SNb.

The SRAM cell SMC shown in FIG. 11 differs in that the p-channel MOS transistors PUa and PUb are used in place of the high resistance load type SRAM cell shown in FIG. 3 and the high resistance load element. The pull-up transistor whose gate is connected to the storage node holding the H level data is turned off and the current path is cut off. Therefore, the current consumption can be reduced as compared with the case of using a high resistance load type SRAM cell. The pull-up transistors PUa and PUb may be configured using, for example, a thin film transistor (TET). In the present invention, the high resistance load type SRAM cell shown in FIG. 3 may be used.

12A is a diagram showing the voltage level of the bit line when the word line activation signal WLE is in an inactive state. When the word line activation signal WLE is in an inactive state of L level, both the MOS transistors PQ and NQ included in the bit line load element 7a are in the on state, and the bit lines are precharged to the power supply voltage Vcc level. In this state, the internal data bus lines are also precharged to the power supply voltage Vcc level.

Next, as shown in Fig. 12B, when the word line activation signal WLE is at the H level and the internal write instruction signal / WEi is at the H level, only the n-channel MOS transistor NQ is turned on in the bit line load element 7a. On the other hand, in the memory cell, the access transistor AT and the driver transistor DT that transfer the L level data on the bit line are turned on. Therefore, in this state, the voltage level of the bit line is lowered to the voltage level of Vcc-Vth- DELTA V by the column current. The n-channel MOS transistor NQ is kept on in the bit line load element 7a in order to prevent the low level voltage Vcc-Vth-ΔV read out on the bit line from lowering and increasing the bit line amplitude. (When the bit line amplitude increases, the precharge operation to the power supply voltage Vcc level after the read completion, that is, the recovery deteriorates.) The n-channel MOS transistor NQ is merely to prevent the low level voltage level of the bit line from going too low, and this current driving capability (size: channel width) may be sufficiently small. In this case, therefore, a large column current can be prevented from flowing, and a bit line amplitude of sufficient magnitude is obtained.

Next, as shown in Fig. 12C, when the word line activation signal WLE becomes H level and the internal write instruction signal / WEi becomes L level, data writing to the memory cell is performed. In this state, the bit line load element 7a is in an inactive state, and the bit line is separated from the power supply node. The ground voltage Vss from the write driver is transferred to the bit line, and the memory node is held at the ground voltage level by the driver transistor DT through the access transistor AT.

When data writing is completed, the state shifts to the state shown in Fig. 12A, and both the MOS transistors PQ and NQ of the bit line load element 7a are turned on. By increasing the size of the p-channel MOS transistor PQ, the ground voltage Vss level can be driven to the power supply voltage Vcc level at high speed.

By making the bit line load element 7a inactive during data writing, the DC current at the time of data writing can be cut off. In addition, since the p-channel MOS transistor PQ is used for bit line voltage recovery in the bit line load element 7a, and is driven off during data reading and writing, this p-channel MOS transistor PQ does not contribute to the column current. . Therefore, the size (current driving force) of the p-channel MOS transistor PQ can be increased, and the recovery of the bit line voltage after data read and write completion can be speeded up without increasing the current consumption. In addition, by reducing the size of the n-channel MOS transistor NQ of the bit line load element even under the power supply voltage, the bit line read amplitude can be increased, and accurate data can be read reliably.

FIG. 13 is a diagram schematically showing the configuration of the main control circuit word line activation signal generator shown in FIG. In Fig. 13, the main control circuit 10 includes a signal change detection circuit 10a for detecting a change in the external write command signal / WE, a data change detection circuit 10b for detecting a change in the input data Din, a signal change detection circuit 10a, and a data change. OR circuit 10c receiving the output signal of detection circuit 10b, address change detection circuit 10d for detecting a change in address signal Ad from outside, and data change detection signal DTD from OR circuit 10c and address from address change detection circuit 10d. An OR circuit 10e receiving the change detection signal ADT and a word line activation signal generation circuit 10f for generating a word line activation signal WLE in accordance with the output signal of the OR circuit 10e.

The change detection circuits 10a, 10b, and 10d are configured using a known circuit, for example, a delay circuit for one signal, and an EXOR circuit for receiving a signal corresponding to the delay circuit output. When detecting a change in a plurality of signals, the change detection signal is generated by obtaining the OR of the output signal of the coincidence detection circuit EXOR.

The OR circuit 10c drives the data change detection signal DED in the active state for a predetermined period when the data write / read mode is changed or when the input data is changed. The address change detection circuit 10a makes the address change detection signal ADT active for a predetermined period in response to the address change (in Fig. 13, the active state is indicated by H level). Therefore, when at least one of the data change detection signal DTD and the address change detection signal ADT becomes active, the OR circuit 10e drives this output signal to the H level of the active state. The word line activation signal generation circuit 10f is constituted by, for example, a falling delay circuit, and activates the word line activation signal WLE by extending the pulse width of the output signal of the OR circuit 10e. As a result, when the input data changes at the time of address change or data writing, the word line activation signal WLE is driven in an active state for a predetermined period.

[Configuration of Memory Array Part 2]

14 is a diagram showing a second configuration of the memory array according to the embodiment of the present invention. In the configuration shown in Fig. 14, for each bit line pair BLP0 and BLP1 in the bit line load circuit 7, a p-channel MOS transistor 7b for equalization which is turned on when the word line activation signal WLE is deactivated is provided. In the IO line load circuit 8b, a p-channel MOS transistor Pc for equalization which electrically turns on the internal data bus lines 8aa and 8ab is provided when the word line activation signal WLE is inactivated. The other configuration is the same as that shown in Fig. 8, and corresponding parts are assigned the same reference numerals.

In the configuration shown in Fig. 14, when the word line activation signal WLE becomes inactive from the active state, the p-channel MOS transistors 7b and Pc for equalization are turned on, and the L-level bit line and the internal data bus line are turned on. It can be driven at the power supply voltage Vcc level at high speed. Next, the operation of the semiconductor memory device shown in FIG. 14 will be described with reference to the signal waveform diagram shown in FIG. 15.

First, the data recording operation will be described. 8, the p-channel MOS transistor PQ and the IO line load circuit 8b included in the bit line load element 7a, the period during which the word line is in the selected state, that is, the period during which the word line activation signal WLE is at the H level. The p-channel MOS transistors Pa and Pb contained in are turned off. At this time, the p-channel MOS transistor 7b for bit line equalization and the p-channel MOS transistor Pc for internal data bus line equalization are also in an off state. When the write command signal / WE (/ WEi) becomes L level, the n-channel MOS transistor NQ included in the bit line load element is also turned off. The bit line (bit line BL in FIG. 15) from which the H level data has been read maintains the power supply voltage Vcc level, and the voltage level of the bit line (bit line / BL in FIG. 15) from which the L level data is read decreases. Then, the write driver operates in accordance with the write data Di, and the full level of the bit line / BL is driven to the L level of the ground voltage level. On the other hand, the bit line BL is at the power supply voltage Vcc level (writing operation of the H level data).

When the word line activation signal WLE is driven in an inactive state of L level and data writing is completed, the control signal? NZ rises to H level, and the p-channel MOS transistor PQ and n-channel MOS transistor NQ and The p-channel MOS transistors Pa and Pb included in the IO line load circuit 8b are turned on. As a result, the voltage levels of the bit lines BL and the internal data bus lines 8ab that were at the L level are raised to the power supply voltage Vcc level at high speed. At this time, the equalizing MOS transistors 7b and Pc are turned on, electrically shorting the bit lines BL and / BL, and electrically shorting the internal data bus lines 8aa and 8ab. Therefore, charges are supplied from the L-level bit line and the internal data bus line 8ab to the H-level bit line BL and the internal data bus line 8aa, respectively, and the voltage level rises at a high speed. As a result, the bit lines BL and / BL and the internal data bus lines 8aa and 8ab reach the power supply voltage Vcc level after their voltage levels are the same. Therefore, by using the equalizing MOS transistors 7b and Pc, it is possible to precharge to the power supply voltage Vcc level faster.

Next, the data reading operation will be described. At the time of reading this data, the p-channel MOS transistors PQ, Pa, Pb and Pc and 7b are all in the off state while the word line WLE is active. In this state, the voltage level of the bit line BL becomes the power supply voltage Vcc level and the other bit line / BL becomes the L level of the voltage Vcc-Vth-ΔV. When the word line activation signal WLE becomes inactive and data reading is completed, all of these p-channel MOS transistors PQ, Pa, Pb, Pc, and 7b are turned off. Therefore, since the H level bit line BL and the L level bit line / BL and the H level internal data bus line 8aa and the L level internal data bus line 8ab are electrically shorted, respectively, the L level bit line / BL and The voltage level of the internal data bus line 8ab rises at a higher speed and is precharged to the power supply voltage Vcc level at a higher speed.

Therefore, as shown in FIG. 14, by providing an equalizing transistor in the bit line pair and the internal data bus, recovery at the completion of the data read operation and at the completion of the write can be performed at a higher speed.

[Configuration of recording / reading circuit]

FIG. 16 is a diagram showing the configuration of a read circuit included in the write / read circuit 8 shown in FIG. This write / read circuit 8 includes a cross-coupled sense amplifier 8c that externally amplifies signals I / O and I / OZ on internal data bus lines 8aa and 8ab. The cross-coupled sense amplifier 8c is connected between the power supply node and the output node NDb, and its gate is connected between the power supply node and the output node NDa, and the p-channel MOS transistor P1 is connected to the output node NDa. Channel MOS transistor P2 connected to the output node NDb, n-channel MOS transistors N1 and N3 connected in series between the output node NDb and the ground node, and in series between the output node NDa and the ground node. Also included are n-channel MOS transistors N2 and N4. The gates of the n-channel MOS transistors N1 and N2 are connected to internal data bus lines 8aa and 8ab, respectively. The sense amplifier activation signal SE1 is given to the gates of the n-channel MOS transistors N3 and N4.

The cross-coupled sense amplifier 8c is also connected between the power supply node and the output node NDb, and its gate is connected between the p-channel MOS transistor P3, which is connected to the output node NDb, and between the power supply node and the output node NDa. The p-channel MOS transistor P4 whose gate is connected to the output node NDa and the p-channel MOS transistors P5 and P6 which are turned on when the sense amplifier activation signal SE1 is inactivated and precharge the output nodes NDb and NDa to the power supply voltage Vcc level are also provided. Include. The P-channel MOS transistors P1 and P2 are cross-coupled with gates and drains, and differentially amplify the voltage levels of the output nodes NDa and NDb.

The configuration of the bit line load circuit provided for the IO line load circuit 8b and each bit line of the memory cell array 1 is the same as that shown in Fig. 14, and a bit line equalizing transistor and an internal data bus line equalizing transistor are provided. Next, the operation of the cross-coupled cent amplifier shown in FIG. 16 will be described with reference to the signal waveform diagram shown in FIG.

The operation of the cross-coupled sense amplifier 8c operates during data reading, and the internal write instruction signal / WEi (external write instruction signal / WE) is maintained at the H level.

When the address signal Ad changes, the word line activation signal WLE is driven in an active state of H level for a predetermined period, and the column selection signal Y for selecting an addressed column is driven in an active state according to the given address signal Ad. The data of the memory cells in the row addressed by this word line activation signal WLE is read out on the corresponding bit lines BL and / BL, and then the internal data bus lines 8aa and through the column select gate in a conductive state included in the multiplexer 6. Delivered on 8ab. The potentials I / O and I / OZ of the internal data bus lines 8aa and 8ab are precharged to the power supply voltage Vcc up to that point, and when the voltages Vcc and Vcc-Vth-ΔV from the selection bit lines BL and / BL are transferred, The voltage level changes in accordance with the transmitted bit potential.

In the inactive state of the sense amplifier activation signal SE1, the p-channel MOS transistors P5 and P6 are on, and the output signals SA1 and / SA1 are precharged to the power supply voltage Vcc level. In addition, the n-channel MOS transistors N3 and N4 are in an off state. In this cross-coupled sense amplifier 8c, the current path from the power supply node to the ground node is interrupted, and no sense operation is performed.

When the difference between the data signals I / O and I / OZ read on the internal data bus lines 8aa and 8ab becomes relatively large, the sense amplifier activation signal SE1 is driven to the H level which is active for a predetermined period. Since the voltage levels of the internal data bus lines 8aa and 8ab are relatively high, the conductances of the n-channel MOS transistors N1 and N2 are large in this cross-coupled sense amplifier 8c, and the voltage levels of the output nodes NDa and NDb decrease once. The rate of decrease of the voltage levels of the output nodes NDa and NDb varies depending on the voltage levels of the internal read data signals I / O and I / OZ. Now, it is assumed that the internal read data signal I / O is at the power supply voltage Vcc level, and the internal data read signal I / OZ is at a voltage level of the voltage Vcc-Vth-ΔV with the L level. In this state, the output node NDb is rapidly discharged through the MOS transistors N1 and N3, and the voltage level of the signal / SA1 from the output node NDb decreases. On the other hand, the current flowing through the n-channel MOS transistors N2 and N4 is smaller, and the rate of decrease of the voltage level of the signal SA1 from the output node NDa is slow.

When the voltage level of the output node NDb is lowered, first, the p-channel MOS transistor P2 is turned on, supplying current to the output node NDa, and raising the voltage level of the signal SA1 of the output node NDa. Current is supplied to this output node NDa to raise the voltage level of the signal SA1 of the output node NDa. As the voltage level of the output node NDa rises, the p-channel MOS transistor P1 remains off, and the signal / SA1 from the output node NDb falls to L level. On the other hand, the signal SA1 at the output node NDa is pulled up by the p-channel MOS transistor P2 and returns to the H level. In this state, the MOS transistors P3 and P4 function as pull-up elements, suppressing the signal / SA1 from falling to the ground voltage Vss level, and the voltage level of the signal SA1 from the output node NDa is controlled by this transistor P4. It is maintained at the voltage level of Vth. The pull-up functions of the p-channel MOS transistors P3 and P4 weaken the latch state of the cross-linked p-channel MOS transistors P1 to P2, and shorten the recovery time of the output nodes NDa and NDb.

When data reading is completed and the sense amplifier activation signal SA1 drops to L level, the n-channel MOS transistors N3 and N4 are turned off, and the p-channel MOS transistors P5 and P6 are turned on, and the signals from the output nodes NDa and NDb are turned off. SA1 and / SA1 are driven to the power supply voltage Vcc level again.

Then, the word line activation signal WLE becomes inactive at the L level, and the bit lines BL and / BL and the internal data bus lines 8aa and 8ab of the memory cell array 1 return to the power supply voltage Vcc level at high speed.

By using this cross-coupled sense amplifier 8c, even when the potential difference between the internal data bus lines 8aa and 8ab (bit lines BL and / BL) is small, a sense operation can be performed at high speed and reliably. This is because the feedback operation of the cross-coupled p-channel MOS transistors P1 and P2 is a negative feedback operation, and the voltage difference between the output nodes NDa and NDb is amplified at high speed. In the case of using the current mirror type circuit, the n-channel MOS transistor of the comparison stage has a large conductance because it receives a signal of a relatively high voltage level, and a relatively large current flows in both the master and slave stages of the current mirror stage. . Therefore, in the case of using the current mirror type differential amplifier, when the voltage levels of the signal I / O and I / OZ of the internal data bus lines 8aa and 8ab are both high, the gain of the current mirror type amplifier circuit is lowered, resulting in high speed and accurate amplification. The operation cannot be performed (because the operating region deviates from the region where the current mirror type sense amplifier has the highest sensitivity (strike zone)). By using this cross-coupled sense amplifier 8c, after precharging the internal data bus lines 8aa and 8ab to the power supply voltage Vcc level, even when the signal level changes and the change range is small, high speed and reliable amplification operation can be performed. (One side of the cross-coupled p-channel MOS transistor remains off).

In the case of the current mirror differential amplifier, the master transistor of the current mirror stage 1 is diode-connected, and the voltage amplitude at the drain end of the diode-connected MOS transistor is small. Therefore, when a current mirror differential amplifier is used, it is difficult to generate a differential signal pair. However, as shown in FIG. 16, a differential signal pair having a relatively large signal amplitude can be generated by using a cross-coupled sense amplifier.

As described above, by using the cross-coupled sense amplifier in the readout circuit as shown in Fig. 16, it is possible to reliably amplify a small signal amplitude to generate a differential signal pair. 18 is a diagram schematically illustrating a configuration of a circuit for generating a sense amplifier activation signal. This sense amplifier activation signal generator is included in the main control circuit 10 shown in FIG. In FIG. 18, the sense amplifier activation signal generator generates a one-shot pulse that generates a one-shot pulse signal having a predetermined time width in response to the delay circuit 10g delaying the word line activation signal WLE for a predetermined period and the output signal of the delay circuit 10g. Generation circuit 10h.

In the configuration shown in Fig. 18, the word line activation signal WLE becomes active, and after the memory cell data is transferred on the internal data bus line, the output signal of the delay circuit 10g rises and the sense amplifier from the one short pulse generation circuit 10h. Activation signal SE1 is driven to H level for a predetermined period. By adjusting the delay time of the delay circuit 10g, the memory cell data is transferred on the internal data bus line, and the sense amplifier can be activated when the voltage difference on the internal data bus line is sufficiently large.

[Configuration of Reading Circuit 2]

Fig. 19 shows a second configuration of the read circuit. In the configuration shown in Fig. 19, the readout circuit includes current mirror differential amplifiers 8d and 8e for differentially amplifying the output signals SA1 and / SA1 of the cross-coupled sense amplifier 8c and converting them into CMOS level signals. The current mirror differential amplifier 8d is connected between the power supply node and the node NDc, and is connected between the p-channel MOS transistor P7 and the node NDc and the ground node which are connected in response to the activation of the sense amplifier activation signal / SE1 (L level). P-channel MOS transistor P8 and n-channel MOS transistor N5 connected in series with each other, and p-channel MOS transistor P9 and n-channel MOS transistor N6 connected in series with each other between node NDc and the ground node. The p-channel MOS transistor P8 receives the output signal / SA1 of the cross-coupled sense amplifier 8c at its gate, and the p-channel MOS transistor P9 receives the output signal SA1 of the cross-coupled sense amplifier 8c at its gate. The gates of the n-channel MOS transistors N5 and N6 are connected to the drain node NDd of the n-channel MOS transistor.

The current mirror differential amplifier 8e is connected between the power supply node and the node NDe, and is connected in series between the p-channel MOS transistor P10 conducting in response to the activation of the sense amplifier activation signal / SE1, and between the node NDe and the ground node. P-channel MOS transistors P11 and n-channel MOS transistors N7 and p-channel MOS transistors P12 and n-channel MOS transistors N8 connected in series with each other between the node Nde and the ground node. The p-channel MOS transistor P11 receives the output signal SA1 of the cross-coupled sense amplifier 8c at its gate, and the p-channel MOS transistor P12 receives the output signal SA1 of the cross-coupled sense amplifier 8c at its gate. The gates of the n-channel MOS transistors N7 and N8 are connected to the drain node NDf of the n-channel MOS transistor N7.

In current mirror differential amplifiers 8d and 8e, p-channel MOS transistors P7 and P10 act as current source transistors, p-channel MOS transistors P8 and P9 and P11 and P12 of p-channel MOS transistors constitute differential amplifier stages, respectively. The MOS transistors N5 and N6 and the n-channel MOS transistors N7 and N8 form a current mirror stage, respectively. Next, the operation of the read circuit shown in FIG. 19 will be described with reference to the operation waveform diagram shown in FIG.

When the data is read, the word line activation signal WLE is driven in an active state, and the column selection signal Yi corresponding to the selection column is driven in an active state according to the address signal, and the data of the bit lines BL and / BL are stored in the internal data bus line 8aa. And 8ab. The sense amplifier activation signal SE1 is then driven in an active state, and the cross-coupled sense amplifier 8c performs a sense operation and generates complementary output signals SA1 and / SA1. This series of operations is the same as that of the read circuit shown in FIG.

When the sense amplifier activation signal / SE1 is at the H level, no current flow path exists in the current mirror type differential amplifiers 8d and 8e, and the internal node is in a floating state of high impedance. When the sense amplifier activation signal SE1 becomes H level, the sense amplifier activation signal SE1 becomes L level at which the active state is active, and the current mirror differential amplifiers 8d and 8e start the differential amplitude operation. Assume that signal SA1 is at H level and signal / SA1 is at L level. In the current mirror type differential amplifier 8d, the p-channel MOS transistor P8 remains almost off, while the p-channel MOS transistor P9 is turned on to supply current to the n-channel MOS transistor N6. The n-channel MOS transistors N5 and N6 form a current mirror circuit, and when the sizes are the same, currents of the same magnitude flow through these MOS transistors N5 and N6. Therefore, the signal SA2 in the high impedance state up to that time is rapidly discharged to the ground voltage Vss level. On the other hand, in the current mirror differential amplifier 8e, the signal / SA1 is almost at the supply voltage Vcc level (exactly the voltage level of Vcc-Vth), and the p-channel MOS transistor P11 is mostly off, while the p-channel MOS transistor P12 is on. It becomes a state. Therefore, since no current flows through the n-channel MOS transistors N7 and N8 constituting the current mirror stage, the signal / SA2 is driven to the power supply voltage Vcc level by the p-channel MOS transistor P12. As a result, the complementary signals SA2 and / SA at the CMOS level can be generated.

Complementary signals SA2 and / SA2 of this CMOS level are replaced with complementary signals SA1 and / SA1 of an intermediate voltage level.

In this way, data can be stably read.

Subsequently, when a predetermined period elapses, the sense amplifier activation signal SE1 drops to the L level, and the sense amplifier activation signal SE1 becomes the H level to complete the sense operation, and the signals SA1 and / SA1 return to the power supply voltage Vcc level. The signals SA2 and / SA2 also return to the high impedance state.

[Configuration of Reading Circuit 3]

Fig. 21 is a diagram showing a third configuration of the reading circuit. 21 shows the configuration of the cross-coupled sense amplifier 8c included in the read circuit. The cross-coupled sense amplifier 8c shown in FIG. 21 is provided with an n-channel MOS transistor N9 for equalizing the cross-coupled sense amplifier 8c shown in FIG. 16 and the output nodes NDa and NDb for a predetermined period at the start of the sense operation. The point is different. Other configurations are the same, and corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

Next, the operation of the read circuit shown in FIG. 21 will be described with reference to the signal waveform diagram shown in FIG. When data is read, the address signal Ad changes, the word line activation signal WLE is activated for a predetermined period, and the data of the selected memory cell is transferred to the internal data bus lines 8aa and 8ab. These operations are the same as those of the read circuit shown in FIG. When the sense amplifier activation signal SE1 becomes active, the precharge to the power supply voltage Vcc level of the output nodes NDa and NDb is completed, while the n-channel MOS transistors N3 and N4 are turned on, so that the cross-coupled sense amplifier 8c is turned on. Starts the sense operation. In response to the activation of the sense amplifier activation signal SE1, the equalizing instruction signal SEQ is set to the H level for a predetermined period, and the n-channel MOS transistor N9 is turned on to electrically short the output nodes NDa and NDb. In accordance with the signals transmitted on the internal data bus lines 8aa and 8ab, the conductances of the n-channel MOS transistors N1 and N2 increase rapidly, and the signals SA1 and / SA1 from the output nodes NDa and NDb once drop to a low level. Subsequently, the equalization operation causes the voltage levels of the output nodes NDa and NDb to slowly decrease by one of the p-channel MOS transistors P1 and P2. When the sense amplifier equalization instruction signal SEQ is inactivated at the L level, the output nodes NDa and NDb are electrically separated. In this state, the voltage difference between the internal data bus lines 8aa and 8ab is sufficiently enlarged, and the cross-coupled sense amplifier 8c accurately senses the signal voltage level on the internal data bus lines 8aa and 8ab, and the signals SA1 and / SA1 are used. Drive to H level and L level.

That is, when the sense amplifier activation signal SE1 is active, the MOS transistors N1 and N2 receive a signal of a relatively high voltage level at their gates, and the conductance greatly and rapidly lowers the voltage levels of the output nodes NDa and NDb. At this time, when the voltage difference between the internal data bus lines 8aa and 8ab is small, there is a possibility that reverse data is output. This inverse data is generated by fluctuations in the threshold voltages of the MOS transistors P1 and P2, and N1 and N2, and also by a sudden discharge operation. Once the normal data is output after the reverse data is output, it takes time until the normal data is output and high-speed reading cannot be performed. In particular, since the inverse data is further amplified by the current mirror differential amplifier provided at the next stage, the time for which the inverse data is output before the current mirror differential amplifier is output is long, and high speed reading cannot be performed.

However, at the start of the sense operation, the n-channel MOS transistor N9 for equalization is turned on so that the voltage levels of the output nodes NDa and NDb are the same to prevent reverse data from being output, and the internal data bus lines 8aa and 8ab By starting the sense operation in a state where the voltage difference between the internal read signals I / O and I / OZ is sufficiently large, the internal read data signals SA1 and / SA1 can be generated accurately without generating reverse data.

Fig. 23 is a diagram showing the configuration of the sense equalization instruction signal generator. This sense equalization instruction signal generator is included in the main control circuit 10 shown in FIG. In Fig. 23, the sense equalization instruction signal generation section includes a one-shot pulse generation circuit 10i for generating one-shot pulses that become active at a predetermined H level in response to the rise of the sense amplifier activation signal SE. This one short pulse generation circuit 10i is realized using a known configuration including a delay circuit and a logic gate. By using this one-shot pulse generation circuit 10i, the sense equalization instruction signal SEQ can be driven in the active state of the H level for a predetermined period when the sense amplifier is activated.

As described above, since the output node is electrically shorted at the start of the sense operation of the cross-coupled sense amplifier for a predetermined period of time, reverse data can be prevented from being output at the start of the sense operation, and data can be read accurately at high speed. Can be done.

[Configuration of Reading Circuit 4]

Fig. 24 is a diagram showing the fourth configuration of the reading circuit. In the configuration shown in Fig. 24, n-channel MOS transistors N10 and N11 which drive the output nodes of the current mirror type differential amplifiers 8d and 8e to the ground voltage level when the sense amplifier activation signal / SE1 is inactive (H level), and the sense amplifier An equalizing element CQ is provided for electrically shorting the output nodes of the current mirror type differential amplifiers 8d and 8e in response to the equalizing indication signals SEQ and / SEQ. Other configurations are the same as those shown in Figs. 19 and 21 above, corresponding parts are designated by the same reference numerals and detailed description thereof will be omitted.

The equalizing element CQ is an n-channel MOS transistor which is turned on in response to the activation of the sense amplifier equalization indication signal SEQ and a p-channel which is turned on in response to the activation (L level) of the sense amplifier equalization instruction signal / SEQ. MOS transistors. Next, the operation of the read circuit shown in FIG. 24 will be described with reference to the operation waveform diagram shown in FIG.

The address signal Ad changes so that the word line activation signal WLE becomes active for a predetermined period of time, and then the column selection signal Yi is driven in an active state, and the memory cell data of the column selection is driven through the bit lines BL and / BL through the internal data bus line. Delivered in 8aa and 8ab. This operation is the same as that of the read circuit shown in FIG. In the cross-coupled sense amplifier 8c, in response to the activation of the sense amplifier activation signal SE1, after the output node is equalized for a predetermined period, a sense operation is started to prevent reverse data generation.

On the other hand, in the current mirror differential amplifiers 8d and 8e, when the sense amplifier activation signal / SE1 is at the H level, the output signals SA2 and / SA2 of the current mirror differential amplifiers 8d and 8e are maintained at the ground voltage level.

Therefore, in the output signals SA2 and / SA2 of the current mirror differential amplifiers 8d and 8e, the ground voltage level becomes the voltage level at the start of operation. Subsequently, when the sense amplifier activation signal SE1 is activated, the MOS transistors N10 and N11 are turned off. On the other hand, the equalizing element CQ maintains the output signals SA2 and / SA2 at the same voltage level for a predetermined period when the current mirror type differential amplifiers 8d and 8e start operating by the equalizing instruction signals SEQ and / SEQ. In this state, the output signal of the cross-coupled sense amplifier 8c simultaneously drops to the low level, and the voltage levels of the output signals SA2 and / SA2 of the current mirror differential amplifiers 8d and 8e slowly rise.

After a predetermined period has elapsed, when the sense equalization instruction signals SEQ and / SEQ become inactive, the output signals SA1 and / SA1 of this cross-coupled sense amplifier 8c are driven at high voltage levels at high and low levels. . Therefore, the current mirror differential amplifiers 8d and 8e also differentially amplify these signals SA1 and / SA1, and drive the signals SA2 and / SA2 at the power supply voltage Vcc level and ground voltage Vss level at high speed.

The pull-down n-channel MOS transistors N10 and N11 are installed on the output mirror 8d and 8e output nodes, and the output mirror 8d and 8e output nodes are switched when the sense amplifier activation signal / SE1 is at the H level. Maintain the ground voltage level. As a result, the output nodes of the current mirror type differential amplifiers 8d and 8e are in a high impedance state, and the data level can be read accurately without changing the voltage level at the start of operation.

The equalizing element CQ equalizes the output signals SA2 and / SA2 for a predetermined period at the start of the sense operation, thereby preventing reverse data from being output when the voltage levels of the output signals SA1 and / SA1 of the cross-coupled sense amplifier 8c are the same. In addition, accurate data reading becomes possible.

By using the reading circuit shown in FIG. 24, even when the voltage difference between the signals rising to the internal data bus lines 8aa and 8ab is small even under low voltage, accurate and high speed data can be read.

In the configuration shown in Fig. 24, one n-channel MOS transistor H9 is used for equalizing the output node of the cross-coupled sense amplifier 8c, while equalizing the output nodes of the current mirror differential amplifiers 8d and 8e. CMOS transmission gates are used. This is because the layout area for installing equalization elements for one cross-coupled sense amplifier is small, while for the current mirror differential amplifier, one equalization element is installed for two current mirror differential amplifiers. This is because there is room in the layout area. Therefore, when there is a margin of area, the CMOS transmission gate may also be used as the output node equalizing element in the cross-coupled sense amplifier 8c. The conductance can be made larger than when using a CMOS transmission gate, and accurate equalization can be realized.

As described above, by precharging the output nodes of the cross-coupled sense amplifier and the current mirror differential amplifier to the power supply voltage Vcc level and the ground voltage Vss level, respectively, the voltage level at the start of operation can be kept constant. The sense operation can be performed. By equalizing the output node for a predetermined time at the start of the sense operation, reverse data can be prevented from being output and data can be read at high speed.

[Configuration of input / output circuit]

FIG. 26 is a diagram illustrating a configuration of the input / output circuit 9 shown in FIG. 6. In Fig. 26, the output circuit includes a NAND circuit 9a receiving the sense amplifier activation signal SE1 and the output signals SA2 and / SA2 from the current mirror differential amplifier 8e, and the output signal SA2 of the sense amplifier activation signal SE1 and the current mirror differential amplifier 8d. A NAND circuit 9b, an inverter 9c receiving an output signal of the NAND circuit 9b, and a p-channel MOS transistor 9d and an n-channel MOS transistor 9e connected in series between the power supply node and the ground node. The output signal of the NAND circuit 9a is given to the gate of the p-channel MOS transistor 9d, and the output signal of the inverter 9c is given to the gate of the n-channel MOS transistor 9e.

In the configuration of the output circuit shown in Fig. 26, the output signals SA2 and / SA2 from the current mirror differential amplifiers 8d and 8e are at the CMOS level. When the sense amplifier activation signal SE1 is in an inactive state at the L level, the output signal of the NAND circuit 9a is at the H level, and the output signal of the inverter 9c is at the L level, and the MOS transistors 9d and 9e are turned off at the same time. It remains high impedance.

When the sense operation is started and the sense amplifier activation signal SE1 is driven in the active state, the output data Dout (or DQ) is generated in accordance with the signals SA2 and / SA2. When signal SA2 is at H level, output signal of inverter 9c is at H level, while output signal of NAND circuit 9a is at H level, MOS transistor 9d is off, MOS transistor 9e is on, and output data Dout Becomes L level. In contrast, when the signal SA2 is at L level, the output signal of the inverter 9c is at L level, while the output signal of the NAND circuit 9a is at L level, and the output data Dout is at H level of the power supply voltage Vcc level.

Even when the sense amplifier activation signal SE1 is applied to the data output circuit, while the output node of the current mirror differential amplifier is equalized, the signals SA2 and / SA2 are both at the L level and both the MOS transistors 9d and 9e are in the off state. During this time, output high impedance is maintained to prevent reverse data output. The data output circuit may be given a signal which becomes active after the sense amplifier equalization is completed.

27 is a diagram illustrating a configuration of a data recording unit. In Fig. 27, this recording path is activated in response to the activation of the internal write instruction signal / WEi, and activated for a predetermined period in response to the activation of the input buffer 9f for buffering the input data Din from the outside and the data change detection signal DTD. And a write driver 8w for generating complementary data D and / D according to the data write from the input buffer 9f in response to the write pulse signal WB from the write pulse generator 11a. The input buffer 9f is included in the input / output circuit 9, and the write driver 8w is included in the write / read circuit 8 (see Fig. 6). The recording pulse generator 11a is included in the recording / reading control circuit 11 shown in FIG.

In the configuration shown in Fig. 27, a change in data recording from the input buffer 9f is detected, the write driver pulse WD from the write pulse generator 11a is driven to the H level for a predetermined period, and the write drive circuit 8w is used to view the complementary data D and / D. Create As a result, the reverse data can be prevented from being transferred to the internal data bus, and the internal data bus and the bit line pair can be reliably driven in accordance with the write data from the outside.

[Other applications]

In the above-described semiconductor memory device, one cross-coupled sense amplifier is provided for the memory cell array 1. The memory cell array 1 may be divided into column blocks in a plurality of column units, a cross-coupled sense amplifier may be provided in each column block, and a current mirror differential amplifier may be provided in common in the plurality of cross-coupled sense amplifiers. In this case, only the cross-coupled sense amplifier provided for the column selection block is activated in accordance with the column block designation signal and the sense amplifier activation signal.

In addition, input / output of data may be performed not in 1 bit but in multiple bits in parallel. For each bit, the write / read circuit described so far is provided, and a plurality of bit line pairs are simultaneously selected.

As described above, according to the present invention, since the load element of the CMOS configuration in which the current driving force is adjusted in the operation mode is used as the load element of each bit line, a sufficient bit line amplitude is formed even under a low power supply voltage, so that accurate data reading is possible. In addition, it is possible to prevent the generation of a direct current during data recording, and to realize a low current consumption.

Further, by using the data read sense amplifier as a cross-coupled sense amplifier, it is possible to amplify the minute potential at high speed to generate a complementary signal pair. By amplifying the output signal of the cross-coupled sense amplifier again with a current mirror differential amplifier, it is possible to accurately generate a CMOS level signal pair.

In addition, by the equalization of the output nodes of the differential amplifiers by the sense amplifiers for a predetermined period of time during the start of the sense operation, reverse data can be prevented from being output and data can be read stably and at high speed.

In addition, by precharging the output nodes of the sense amplifier and the differential amplifier to a predetermined voltage level, accurate data sense operation can be performed without performing a sense operation at an unstable voltage level at all times having the same voltage level at the start of operation.

Claims (3)

A plurality of memory cells arranged in a row; A plurality of word lines arranged in correspondence with each said row, and to which memory cells of the corresponding row are connected; A plurality of pairs of bit lines arranged corresponding to each of the above columns and to which memory cells of the corresponding columns are connected; A plurality of bit line load elements provided corresponding to each bit line, and respectively connected between the corresponding bit line and the power source node, and each of the plurality of bit line load elements is connected in parallel to each other between the corresponding bit line and the power node. A first conductivity type insulated gate field effect transistor, a second conductivity type insulated gate field effect transistor, A control circuit for adjusting a load on each corresponding bit line of the plurality of bit line load elements in response to a data write instruction signal and a word line activation instruction signal, the control circuit comprising a data write instruction signal and the word line activation signal At the time of activation, the first and second conductivity type insulated gate transistors are turned off, and in response to the activation of the word line activation signal, the insulation gate type field effect transistors of the first conductivity type are applied. Means for turning off, And a read circuit for reading data of the addressed memory cell in the data read mode. The method of claim 1, The read circuit, An internal lead data line pair to which data of the addressed memory cell is transferred when reading data A cross-coupled sense amplifier coupled to the internal lead data line pair, the differentially amplifying the potential of the internal lead data line pair to generate a complementary signal at a corresponding output node in response to a sense amplifier activation signal; And the cross-coupled sense amplifier comprises a pair of insulated gate field effect transistors of the first conductive type which are cross-coupled. The method of claim 2, The read circuit, A pair of current mirror differential amplifiers are provided corresponding to the output node pairs of the cross-coupled sense amplifiers and differentially amplify the potentials of the output node pairs. The pair of current mirror differential amplifiers includes: And differentially amplifying a potential of an output node pair of the cross-coupled sense amplifier complementarily with each other in response to the activation of the sense amplifier activation signal.