KR19990075869A - Key signal processing circuit and method - Google Patents

Abstract

In the key data processing between the microprocessor and the remote control device, a key signal processing circuit and method for converting a serial key signal output from a remote controller into parallel in parallel so that the microprocessor can easily recognize and process the same. The present invention relates to verifying whether an input signal is key data output from a remote controller, and in the case of an intermittent key as key data, counting a high section of the inverted input key data to obtain key data of "0" and "1", respectively. Detects and shifts the detected 32-bit key data of "0" and "1" into four D-flip flops, and then latches the four D-flip flops by an interrupt signal in a microprocessor. Accesses the key data and processes 32 bits of key data in parallel by 8 bits for access. By re-processing one key data, this simple interface circuit converts serial data into parallel data, which reduces the load on the microprocessor and eliminates the need for separate microcomputers and external devices. In addition to eliminating the need for signal processing, the logic can be EPLDed to reduce costs.

Description

Key signal processing circuit and method

In the present invention, in the key data processing between the microprocessor and the remote control unit (hereinafter referred to as a remote controller), the microprocessor easily converts the serial key signals output from the remote controller in parallel. The present invention relates to a key signal processing circuit and a method for recognizing and processing a key signal.

In a conventional microprocessor, a key signal output from a remote controller is input and recognized using a specific microcomputer and an external device.

That is, a 4-bit or 8-bit microcomputer receives a serial key signal output from a remote controller, converts it into parallel data, and outputs it to a microprocessor.

However, as described above, as the microprocessor additionally includes a separate dedicated microcomputer and a peripheral external device for recognizing the key signal of the remote controller, the key signal interface circuit is complicated, thereby increasing the load of the microcomputer, and of course, high cost. There is a problem that the cost is consumed because of using the circuit element.

The present invention has been made to solve the above problems, the object of which is to implement an interface circuit consisting of logic (Logic) to easily convert the serial key signal output from the remote controller in parallel to facilitate this easy It is an object of the present invention to provide a key signal processing circuit and method which can recognize and process the same.

The key signal processing circuit and method of the present invention for achieving the above object, to determine whether the input signal is the key data output from the remote control, and counts the high period of the inverted input key data if the key data is an intermittent key To detect key data of "0" and "1", shift the latched key data of "0" and "1" of the detected 32 bits to four D-flip flops, and then By accessing the key data latched in the four D-flip flops by the interrupt signal, a total of 32 bits of key data are accessed in parallel by 8 bits, and in the case of a continuous key, the previously accessed key data is again restored. Characterized in that the processing.

1 is a block diagram of a key signal processing circuit according to the present invention;

2 is a detailed configuration diagram of a key signal processing circuit according to the present invention;

3 is a flow chart showing a key signal processing method according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: data recognition unit 20: data detection unit

30: continuous key recognition unit 40: parallel processing unit

50: output request unit 60: microprocessor

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the key signal processing circuit according to the present invention.

1 is a block diagram of a key signal processing circuit according to an embodiment of the present invention. The data recognition unit 10 determines whether an input key signal is key data output from a remote controller, and the data recognition unit 10 of the remote controller. If it is determined that the key data is being input, the data detection unit 20 which detects key data of "0" and "1" by inverting the key data and counting the high section of the inverted key data is output from the remote controller. A continuous key recognition unit 30 that determines whether the key data is continuous key data, and a total of 32 bits of key data detected by the data detector 20 include three 8-bit D-flip flops and one 9-bit D-. The parallel processing unit 40 shifts and latches the flip-flop, and the key data input from the continuous key recognition unit 30 is determined to be continuous key data, or the key data is stored in the D-flip flop of the parallel processing unit 40.In the case of two latches, the output request unit 50 outputs an interrupt signal so that the microprocessor can access the key data, and outputs an address signal according to the interrupt signal output from the output request unit 50, thereby outputting the parallel processing unit ( The microprocessor 60 accesses a total of 32 bits of key data latched in the D-flip-flop in parallel by 8 bits and then determines whether the key data is an intermittent key or a continuous key, and performs the corresponding key data processing. It is composed.

2 is a detailed circuit diagram of the key signal processing circuit of the present invention configured as described above, wherein the data recognizing unit 10 includes a dual counter 11 for dividing a reference clock of 1 MHz by 100 and a dual counter ( In step 11), the 100-divided clock is further divided by 4 to output a 400-kHz divided 2.5KHz clock, and according to the 2.5-KHz clock of the D-flip-flop 12. When the key data of the remote controller is input, the counter 13 counts the reader code time of the key data which is a high section, and the counter code of the key data of the remote controller is counted by counting the reader code time of the key data of 9 ms. When recognizing, the D-flip-flop 14 which inverts the preset low output to high and the dual clock which supplies a 3.072 KHz clock to the counter 22 in the data detector 20 by dispensing a reference clock of 6.144 MHz in 2000. According to the output signal of the counter (15, 16) and the continuous key recognition unit 30 It consists of a dual counter 17 which supplies the clock of the D-flip flop 12.

When the high signal is output from the inverter 21 for inverting and inputting key data output from the remote controller and the D-flip flop 14 of the data recognition unit 10, the data detector 20 The counter 22 is configured to count a high section of the key data inverted and input by the inverter 21 and detect key data of "0" or "1", respectively.

When the high signal is output from the D-flip flop 14 of the data recognizing unit 10, the continuous key recognizing unit 30 counts a high section of the key data inverted and input by the inverter 21 to 40 ms. In case of abnormality, the counter 31 which inverts the preset low output to high, and the high signal output from the counter 31 and the key data of the remote controller are input, and when the next key data is not a continuous key, the data recognition unit ( It consists of a continuous key discriminating unit 32 for clearing the dual counter 17 of 10) and stopping the operation of the counter 31.

The parallel processor 40 sequentially shifts and latches the serial key data detected by the counter 22 of the data detector 20 based on the input 32-bit key data. 9-bit D-flip flops 44 for shifting the flops 41 to 43 and the first detected high key data to the last, inverting the low preset output to high and outputting the output to the output request unit 50. It consists of.

Finally, the output request unit 50 is a high signal output from the counter 31 of the continuous key recognition unit 30 or a high signal output from the 9-bit D-flip flop 44 of the parallel processor 40. An interrupt signal is output to the microprocessor 60 in accordance with the signal so that the microprocessor 60 can access the total 32 bits of key data latched in the D-flip flops 41 to 44 four times by eight bits. It is comprised by the generating part 51.

The operation of the key signal processing circuit configured as described above will be described with reference to the flowchart of FIG. 3.

First, the counter 13 of the data recognition unit 10 inputs key data (S1), and the key data is received from the remote controller according to the 2.5KHz clock supplied by the dual counter 11 and the D-flip-flop 12. It is determined whether the key data is output (S2).

Here, the key data output from the remote controller is a code for notifying that the key data is being output, a leader code which always maintains a high section of 9 ms, and a 16-bit custom code that is key data specified by the user. (Custom Code), a 16-bit Data Code that is key data according to the corresponding instruction, and a 1-bit Stop bit that informs the end of one key data. The high interval of the reader code of the key data is counted to determine whether the currently input key data is the key data of the remote controller.

That is, since the reader code always maintains a high section of 9 ms, the counter 13 counts the high section of the reader code to recognize that the key data is output from the remote controller when the reader code is at least 6 ms and 9 ms. If the counted high interval is less than 6 ms, the signal is determined to be a noise signal so that subsequent key data detection is not performed.

At this time, the counter 13 of the data recognizing unit 10, that is, the general-purpose chip 74161 according to the clock of 2.5KHz supplied from the dual counter 11 and the D-flip-flop 12 that divide the 400-MHz clock of 1 MHz. At the rising edge, the leader code starts to count and the high section of the reader code is counted.

As described above, when it is confirmed that the key data input through the data recognition unit 10 is the key data output from the remote controller, through the counter 31 and the continuous key determination unit 32 of the continuous key recognition unit 30. It is determined whether the key data of the remote controller is a continuous key (S3).

When it is determined in step S2 and S3 that the key data of the remote controller is an intermittent key instead of a continuous key, a clock is output from the RCO terminal of the counter 13 of the data recognition unit 10 that has counted a 9 ms reader code. The output of the D-flip-flop 14 whose initial output value is set low by the output clock is inverted to high, and the counter 22 of the data detector 20 is operated by the high signal. The key value of the key data inverted and input through 21 is discriminated.

In this case, the intermittent key refers to a key signal when the key is pressed once, and the continuous key refers to a key signal generated when the key is continuously pressed, such as a scroll key.

That is, when the key data input through the inverter 21 of the data detector 20 is inverted, the high period of the inverted key data is counted through the counter 22 so as to count the key data of "0" and "1". Key data is detected (S4).

In this case, when the key data is "0", one pulse is 1.125 ms, and when the key data is "1", one pulse is 2.25 ms and the high period is 0.56 ms, while the low period is 0.565. ms and 1.96ms have different values.

Accordingly, in the present invention, the high interval of the inverted key data is counted to determine the key data value. In particular, if the high interval of the key data is 1.8 ms or less, it is recognized as "0". Will be recognized.

Subsequently, the key data output from the counter 22 of the data detector 20 is input to the D-flip-flop 41 of the parallel processor 40, and the parallel processor 40 according to the input 32-bit key data. D-flip flops 41 to 44 perform a shift operation to latch the 32-bit " 0 " and " 1 " key data output from the counter 22 of the data detector 20 by 8 bits, respectively. (S5).

Then, in step S3, the key data inputted through the counter 31 and the continuous key discriminating unit 32 of the continuous key recognition unit 30 is confirmed as the continuous key or 32-bit is transmitted to the parallel processing unit 40. When all the data is latched, the interrupt generator 51 of the output request unit 50 outputs an interrupt signal to the microprocessor 60 informing that the data is latched to the parallel processor 40 (S6).

That is, after recognizing the reader code of the key data inputted from the counter 31 of the continuous key recognizing unit 30 and counting the case where the high section of the inverted input key data lasts 40 ms or more, it sets to low. When the output of the counter 31 is reversed to high, the continuous key discriminating unit 32 determines whether the continuous key continues through the inverted high signal and the input key data, and when the next key data is not the continuous key, The dual counter 17 of the data recognition unit 10 is cleared to stop the operation of the counter 31.

Subsequently, the high signal output from the output terminal preset to the high signal of the counter 31 or the low of the 9-bit D-flip-flop 44 of the parallel processor 40 is outputted as the continuous key is recognized. The interrupt generator 51 generates an interrupt signal and outputs the interrupt signal to the microprocessor 60 according to the high signal of the 9-bit D-flip-flop 44 that is detected by shifting the high key data to the last.

Accordingly, the microprocessor 60 accesses the 32-bit data latched in the D-flip flops 41 to 44 of the parallel processing unit 40 four times by eight bits to access all the 32-bit key data (S7). In this case, the key value of the key data is checked to determine whether the key data is an intermittent key or a continuous key (S8). If the intermittent key is performed, the corresponding signal processing is performed (S9). The signal processing by the key data is repeatedly performed as it is (S10).

As described above, the present invention can reduce the load of the microprocessor by converting serial data into parallel data through a simple interface circuit, and requires a complicated signal processing process because no separate microcomputer and external device are required. Of course, there is a cost reduction effect by EPLDing logic.

Claims (7)

In the key data processing circuit between the microprocessor and the remote control, The data recognizing unit 10 determines whether the input key signal is the key data output from the remote controller, and when the data recognizing unit 10 determines that the key data of the remote controller is input, the key data is inverted and inverted. A data detection unit 20 for detecting key data of "0" and "1" by counting the high section of the key data, and a continuous key recognition unit 30 for determining whether the key data output from the remote controller is continuous key data; And a parallel processor 40 for shifting and latching a total of 32 bits of key data detected by the data detector 20 into three 8-bit D-flip flops and one 9-bit D-flip flop, and the continuous key. The microprocessor accesses the key data when it is determined that the key data input from the recognition unit 30 is continuous key data, or when all of the key data is latched in the D-flip flop of the parallel processor 40. An output request unit 50 for outputting an interrupt signal, and an address signal according to the interrupt signal output from the output request unit 50, and the total latch latched to the D-flip-flop of the parallel processor 40; And a microprocessor (60) for accessing 32-bit key data in parallel by 8 bits and determining whether the key data is an intermittent key or a continuous key to perform corresponding key data processing. The method of claim 1, wherein the data recognition unit 10 is divided into a dual counter 11 for dividing a reference clock of 1 MHz 100 and the clock divided by 100 from the dual counter 11 again divided by 400 2.5KHz A D-flip-flop 12 for outputting a clock of the counter, a counter 13 for counting the reader code time of key data of the remote controller according to the 2.5-KHz clock of the D-flip-flop 12, and the counter 13 In the case of recognizing that the key data of the remote controller is counted as the reader code time of the key data, the D-flip-flop 14 which inverts the preset low output to high and divides the reference clock of 6.144 MHz into 2000 and detects the data. Dual counters 15 and 16 for supplying a clock of 3.072 KHz to the counter 22 in (20), and for supplying the clock of the D-flip flop 12 according to the output signal of the continuous key recognition unit 30. Key signal processing circuit, characterized in that consisting of a dual counter (17). 2. The data detection unit 20 of claim 1, wherein the data detector 20 outputs a high signal from the inverter 21 for inverting and inputting key data output from the remote controller and the D-flip flop 14 of the data recognition unit 10. And a counter (22) for counting a high section of the key data inverted and input by the inverter (21) and detecting key data of "0" or "1", respectively. According to claim 1, wherein the continuous key recognition unit 30 of the key data is inverted by the inverter 21 when the high signal is output from the D-flip flop 14 of the data recognition unit 10 When the high period is counted and is 40 ms or more, the counter 31 for inverting the preset low output to high and the high signal output from the counter 31 and the key data of the remote controller are input so that the next key data is not a continuous key. And a continuous key discriminating unit (32) for clearing the dual counter (17) of the data recognizing unit (10) to stop the operation of the counter (31). The serial connection unit 3 of claim 1, wherein the parallel processor 40 sequentially shifts and latches serial key data detected by the counter 22 of the data detector 20 by 32-bit key data input. 8-bit D-flip-flops 41 to 43, and a 9-bit D for shifting the first detected high key data to the last to invert the output set to low to the output request unit 50. A key signal processing circuit comprising: a flip-flop (44). The high-output signal output from the counter 31 of the continuous key recognition unit 30 or the 9-bit D-flip flop 44 of the parallel processing unit 40. An interrupt signal is output to the microprocessor 60 according to the high signal output so that the microprocessor 60 accesses a total of 32 bits of key data latched in the D-flip flops 41 to 44 four times by eight bits. A key signal processing circuit comprising an interrupt generating unit (51). In the key data processing method between the microprocessor and the remote control, A first step of checking whether the input key data is the key data output from the remote controller; and a second step of determining whether the key data is the intermittent key or the continuous key when the first step is to confirm that the key data is output from the remote controller. And a third step of detecting key data of "0" and key data of "1" by counting a high section of the inverted input key data if the key data is an intermittent key in the second step; A fourth step of latching the detected key data of " 0 " and " 1 " in a 32-bit D-flip-flop; and in the second step, the key data is identified as a continuous key or the key data is latched in the fourth step. In this case, accessing the 32-bit key data is performed by accessing the key data latched in the fourth step four times by eight bits four times according to the fifth step of generating an interrupt signal and the interrupt signal generated in the fifth step. And a fifth step of performing signal processing, and a sixth step of repeatedly performing signal processing based on previously accessed key data when the key data accessed in the fifth step is a continuous key. Treatment method.