KR19990074739A - I / O structure of semiconductor device - Google Patents

Abstract

The present invention discloses an input / output structure of a semiconductor device. The structure includes a ground voltage layer formed of silicide poly, an oxide formed to form parasitic capacitance between power supplies on the ground voltage layer, and a power supply voltage layer formed of metal on the oxide near the input / output of the semiconductor device. . Therefore, EMI can be reduced by reducing the instantaneous current loop by forming a power supply voltage layer and a ground voltage layer near the input / output of the semiconductor device and forming parasitic capacitance therebetween.

Description

I / O structure of semiconductor device

The present invention relates to a semiconductor device, and more particularly, to an input / output structure of a semiconductor device capable of reducing electromagnetic interference (EMI).

EMI problems, which were seriously dealt with on boards and sets, have recently become an important factor in determining the demand for integrated circuits down to the chip level. The main reasons for this change are the price competition of modules or set makers, EMI evaluation due to chip functionality, and enhanced application of standards (CISPR, FCC, etc.). As semiconductor integrated circuits are generally high frequency, high density, and high noise, chip-level EMI cannot be ignored. Thus, many efforts have been made to reduce such chip level EMI levels.

Radiation from digital electronics can occur as either differential mode or common mode radiation. Differential mode radiation appears as a result of the current flowing around the loops formed by the conductors of the circuit. These loops act as small antennas that emit magnetic fields.

For a small loop of the area A generating the current I, the electric field E measured in the free space separated by the distance r can be represented by the following equation.

Equation 1

Where E is volts / meter, f is hertz, A is the square meter (m ² ), I is the amperage, and r is the meter.

From the above equation, it can be seen that in differential mode radiation the electric field can be reduced by reducing the current loop area (A).

FIG. 1A shows the instantaneous power supply current when there is no decoupling capacitor, and FIG. 1B shows the instantaneous power supply current when there is a decoupling capacitor, and the power supply voltage Vcc and ground applied through the inductor Lp. The NAND gate 10 is connected between the voltage GND. Here, the NAND gate is shown as an example, but other elements may be used. In FIG. 1A, there is no decoupling capacitor Cd. In FIG. 1B, the decoupling capacitor Cd is connected between a power supply voltage and a ground voltage.

A general digital device is connected between a power supply voltage and a ground voltage to perform some circuit operation. By connecting a decoupling capacitor between the power supply voltage and the ground voltage of such a device, the current loop area is reduced to reduce the electric field (E). .

That is, when the decoupling capacitor is connected as shown in FIG. 1B, the current loop area A is reduced as compared with the case where the decoupling capacitor is not connected as shown in FIG. 1A, and as a result, the value of the electric field E is reduced.

An object of the present invention is to provide an input / output structure of a semiconductor device that can reduce EMI by reducing the current loop area between the power supply voltage and the ground voltage.

The input / output structure of the semiconductor device of the present invention for achieving the above object is a ground voltage layer formed of silicide poly, an oxide formed to form parasitic capacitance between the power source on the ground voltage layer, and a power source formed of metal on the oxide A voltage layer is provided near the input / output of the semiconductor device.

In addition, a ground voltage layer formed of a metal, an oxide formed to form a parasitic capacitance between power supplies on the ground voltage layer, and a power supply voltage layer formed of a metal on the oxide is characterized in that it is provided near the input / output of the semiconductor device. .

1A and 1B show instantaneous power supply currents with and without a decoupling capacitor.

2 is a cross-sectional view of an input / output structure of a conventional semiconductor device.

3 is a plan view of the input / output structure of the semiconductor device of the present invention.

4 is a cross-sectional view taken along the line AA ′ of the structure shown in FIG. 3.

Hereinafter, the input / output structure of a conventional semiconductor device will be described with reference to the accompanying drawings before explaining the input / output structure of the semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of an input / output structure of a conventional semiconductor device, wherein a field oxide 20, a buffer oxide 22 over a field oxide 20, and a buffer oxide 22 over a field oxide 20 are shown. N metal layer 24, intermediate oxide 26 on n metal layer 24, n + 1 metal layer (pad metal) 28 on intermediate oxide 26, And a via contact (VIA contact) 30 for connecting the n metal layer 24 and the n + 1 metal layer 28.

That is, in the input / output structure of the conventional semiconductor element shown in Fig. 1, the power supply voltage and the ground voltage line are not formed under the pad.

3 is a plan view of an input / output structure of a semiconductor device of the present invention, wherein the ground voltage layer 50 formed of metal or silicide poly, the power supply voltage layer 52 formed of metal on the ground voltage layer 50, and the power supply voltage layer A pad window 54 and a pad 56 formed of metal on the 52 are formed.

That is, as shown in FIG. 3, the input / output structure of the semiconductor device is characterized in that the power supply voltage layer 52 and the ground voltage layer 50 are formed under the pad 56. The layers thus formed are used as positive electrodes of parasitic capacitances that can minimize the loop area of instantaneous currents formed by digital switching of other circuits, including input / output buffers.

4 is a cross-sectional view of the input / output structure of the semiconductor device of the present invention, which is a cross-sectional view taken along the line AA ′ of FIG. 3.

Referring to FIG. 4, the structure of the present invention is a field oxide 60, a buffer oxide 62 formed on the field oxide 60, a ground voltage layer 64 formed on the buffer oxide 62, and a ground voltage layer 64 formed on the ground oxide layer 64. A pad formed on the intermediate oxide 66, the power supply voltage layer 68 formed on the intermediate oxide 66, the intermediate oxide 70 formed on the power supply voltage layer 68, and the intermediate oxide 70. It consists of 72 pieces.

In the above-described structure, the ground voltage layer 64, the power supply voltage layer 68, and the pad 72 may each be formed of silicide poly, metal, metal, or all metal.

4, a parasitic capacitance between power supplies is formed in the intermediate oxide 66. As shown in FIG. This is shown in the drawing.

As described above, by forming a parasitic decoupling capacitance between the power supply voltage and the ground voltage near the input / output under the pad (or periphery), the instantaneous current loop area at the input / output during digital switching inside the semiconductor device is reduced. It can be minimized. Therefore, EMI can be reduced.

In addition, the ground voltage layer may be formed of silicide poly or metal as described above. The formation of the silicide poly may increase the capacitance of the parasitic capacitance, thereby improving the EMI reduction effect.

Therefore, the input / output structure of the semiconductor device of the present invention can reduce EMI by reducing the instantaneous current loop by forming a power supply voltage layer and a ground voltage layer near the input / output of the semiconductor device and forming parasitic capacitance therebetween. .

Claims (4)

A ground voltage layer formed of silicide poly; An oxide formed to form parasitic capacitance between power supplies on the ground voltage layer; And And a power supply layer formed of a metal on the oxide near the input / output of the semiconductor device. The input / output structure of a semiconductor device according to claim 1, wherein the ground voltage layer, the oxide, and the power supply voltage layer are provided under a pad. A ground voltage layer formed of a metal; An oxide formed to form parasitic capacitance between power supplies on the ground voltage layer; And And a power supply layer formed of a metal on the oxide near the input / output of the semiconductor device. 4. The input / output structure of a semiconductor device according to claim 3, wherein the ground voltage layer, the oxide, and the power supply voltage layer are provided under a pad.