KR19990074482A - Semiconductor devices - Google Patents

Abstract

A semiconductor device having a plurality of input / output interface modes is disclosed, which includes a mode setting unit, a plurality of memory cell arrays, a data output buffer, and a clock buffer circuit. The mode setting unit generates a plurality of interface mode control signals for controlling to set a corresponding input / output interface mode among the plurality of input / output interface modes according to a user's needs. Each of the plurality of memory cell arrays includes a plurality of memory cells. The data output buffer is for transferring data read out from the memory cells to the outside. The clock buffer circuit is controlled by a plurality of interface mode control signals, thereby generating and outputting an internal clock through a corresponding path among a plurality of paths set for the plurality of interface modes. According to the present invention, since the interface mode control signal is set according to the user's needs, an internal clock having an appropriate period is generated accordingly to control the data output buffer. The data driving delay time is variable.

Description

Semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device configured to control clock access time according to an input / output interface method.

1 shows a timing chart with respect to clock access time in a semiconductor device. Here, reference numeral tSAC denotes an output data delay time with respect to a system clock (hereinafter, referred to as a clock), and reference numeral tOH denotes an output data holding time with respect to a clock CLK. Reference numeral PCLK denotes an internal clock signal synchronized with the clock CLK, and reference numeral DOUT denotes an output data signal.

Referring to FIG. 1, requirements of delay times tSAC and tOH in a synchronous semiconductor memory device will be described below.

In a synchronous semiconductor memory device which inputs and outputs data at high speed in synchronization with the clock CLK, a main constraint in increasing the operating frequency is the output data DOUT delay time tSAC with respect to the clock CLK. That is, in order for the synchronous semiconductor memory device to fetch the output data DOUT at the clock CLK rising edge, the data buffer is output at the previous clock CLK edge. ) Should be driven. At this time, a malfunction occurs when the delay time tSAC until the data buffer drives the output data DOUT is too long to prepare the output data DOUT until the rising edge of the next clock CLK. In addition, even if the delay time (tSAC) before the data buffer drives the output data (DOUT) is appropriate, even if the output data (DOUT) is prepared to the rising edge of the next clock (CLK), the patch section of the safe output data (DOUT) In order to ensure the delay time (tOH) required to hold the output data (DOUT) from the clock (CLK) rising edge must be sufficiently ensured. This means the output data holding time for the next output data DOUT output by the next clock CLK after the level of the output data DOUT generated during the delay time tSAC is maintained for a predetermined time, and the delay time tOH The longer the), the more stable the data patch.

The synchronous semiconductor memory device is divided into a low voltage transistor transistor (LVTTL) mode and a stub series terminated transceiver logic (SSTL) mode according to an input / output interface method. LVTTL has been used for existing dynamic random access memory devices, and SSTL is available only for synchronous dynamic random access memory devices. The differences are shown in Table 1 below.

LVTTL SSTL Vih / Vil of input level 2.0V / 0.8V VREF + 0.2 / VREF-0.2 Output data level VOH / VOL 2.4V / 0.4V Vtt + 0.8V / Vtt-0.8V AC measuring point 1.4 V Vtt VREF Not authorized by the system Is authorized in the system

As shown in Table 1 above, in the first SSTL, externally applied signals, that is, a clock signal CLK, an address signal ADDRESS, a low address strobe signal RABB, and a column address strobe signal CASB ), The internal reference voltage (VREF) used in the input buffer inside the chip connected to) must be applied from the external system. Second, LVTTL and SSTL have different swing widths, that is, input levels, of input signals. For example, LVTTL has a swing width of Vih / Vil of VREF + 0.2 / VREF-0.2 based on the level of the reference voltage (VREF) of the input buffer for Vih / Vil of 2.0V / 0.8V or SSTL. Is narrow. Third, when outputting the information input to the memory device, the voltage level of the output data, that is, the levels of the VOH / VOL that can be detected by the external system whether the output information is data "1" or data "0" different. For example, for LVTTL, VOH / VOL is 2.4V / 0.4V at the DC voltage level and the Measure Point of the AC voltage level is 1.4V. However, in case of SSTL, when VOH / VOL is DC voltage level, Vtt + 0.8V / Vtt-0.8 based on terminal voltage (Vtt) and measurement point of AC voltage level is terminal voltage level.

As such, SSTL is configured differently from LVTTL in order to improve performance when applied to a synchronous semiconductor memory device. Thus, synchronous dynamic random access memory devices, when used in a system, require some internal circuitry to behave differently depending on the interface.

In general, in designing a synchronous semiconductor memory device, the LVTTL mode and the SSTL mode are implemented as an option on the same chip, and the mode is changed as needed. The mode switching method includes a mask option that takes a mask separately, a fuse option that sets a mode by shorting a specific mode fuse in case of a defective cell repair, and a specific pad when a package is assembled. A bonding option for bonding and setting a mode, or a pin bias option for setting a mode by applying a predetermined bias to a specific pin of a package.

The LVTTL mode and SSTL mode require different delay times (tSAC) due to differences in performance and performance. In general, the delay time tSAC required for SSTL mode is reduced. For example, if 6 ns is required as the delay time (tSAC) in the LVTTL mode operating at 100 MHz, a delay time (tSAC) of 5 ns or less is required while operating at 143 MHz or 200 MHz in the SSTL mode. Thus, in order to be able to easily switch between free modes to meet the needs of the user, two modes must be prepared as options on the same chip, and the delay time (tSAC) must be variable according to the selected mode. When the mode is switched by the mask option, it is easy to adjust the delay time tSAC according to this mode. However, when the mode switching is performed by the fuse option, the bonding option, and the pin bias option, in the conventional synchronous semiconductor memory device having a single delay path, the delay time tSAC cannot be adjusted. There is a problem that causes malfunction.

2 shows a circuit diagram of a clock buffer circuit for generating an internal clock PCLK for controlling the delay time tSAC in a conventional synchronous semiconductor memory device.

2, in a conventional synchronous semiconductor memory device, a clock buffer circuit for generating an internal clock PCLK for controlling a delay time tSAC may include a controller 210, a driver 220, and a delay 230. It is provided.

The controller 210 controls the operation of the clock buffer circuit according to the buffer control signal CON.

The control unit 210 is configured as transistors QP1 and QN1.

The transistor QP1 is a PMOS transistor connected between the power supply terminal VDD and the driver 220 and gated by the buffer control signal CON.

The transistor QN1 is an NMOS transistor connected between the driver 220 and the ground terminal GND and gated by the buffer control signal CON.

The driver 220 inputs a clock signal CLK to detect and drive a rising edge thereof.

The driver 220 includes transistors QP2, QP3, QN2 and QN3 and a resistor 222.

The transistor QP2 is a PMOS transistor whose source terminal is connected to the drain terminal of the transistor QP1 constituting the control unit 210 and is gated by the drain terminal.

The transistor QP3 is a PMOS transistor whose source terminal is connected to the drain terminal of the transistor QP1 constituting the control unit 210 and is gated by the drain terminal of the transistor QP2.

The transistor QN2 is an NMOS transistor connected between the drain terminal of the transistor QP2 and one terminal of the resistor portion 222 and gated by the reference voltage VREF.

The transistor QN3 is an NMOS transistor connected between the drain terminal of the transistor QP3 and one terminal of the resistor portion 222 and gated by the clock signal CLK.

The resistor unit 222 is connected between the source terminals of the transistors QN2 and QN3 and the ground terminal GND.

The delay unit 230 inputs a signal output from the drain terminal of the transistor QP3, delays the signal for a predetermined period, and outputs the signal as the internal clock PCLK.

As shown in FIG. 2, a clock buffer circuit for generating an internal clock PCLK for controlling a conventional delay time tSAC inputs a clock signal CLK from an external source to control a data input of an output data buffer and a clock. At the rising edge of the internal clock signal, which is delayed by the rising edge of the signal for a predetermined period, the output data buffer inputs data of a new address, and the output data by data of the previous address disappears as new output data is generated.

As such, the conventional clock buffer circuit has a constant delay time tSAC without considering speed control according to the switching of the input / output interface mode. That is, it is impossible to change the delay time tSAC according to the switching of the input / output interface mode. Therefore, when the delay time (tSAC) in the LVTTL mode is used in the SSTL mode as it is, the margin of the short delay time (tSAC) cannot be secured, so the decrease in productivity must be reduced. In addition, when the delay time tSAC is set based on the SSTL mode, the condition for sufficient output data holding time tOH is not satisfied in the LVTTL mode. Therefore, it is difficult to set a suitable delay time (tSAC) in consideration of mode conversion.

Accordingly, an object of the present invention is to provide a semiconductor device configured to be able to switch an input / output interface mode without using a mask option. The semiconductor device is configured such that an output data driving delay time for a clock signal varies according to the input / output interface mode. To provide.

1 is a timing diagram of various signals for describing a clock access time.

2 is a detailed circuit diagram of a clock buffer circuit in a conventional semiconductor device.

3 is a block diagram of a semiconductor device according to an embodiment of the present invention.

4 is a block diagram of a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of a circuit according to a specific embodiment of the clock buffer circuit in FIG. 4.

FIG. 6 is a circuit diagram of a circuit according to another specific embodiment of the clock buffer circuit in FIG. 4.

* Detailed description of the signs in the drawings

VDD: power supply terminal, GND: ground terminal,

NOUT1, NOUT2: output terminals of the current mirror circuit, CLK: external clock signal,

PCLK: internal clock signal, CON: clock buffer control signal,

CONINT: Interface mode control signal.

In order to achieve the above object, the semiconductor memory device according to the present invention includes a mode setting unit for generating a plurality of interface mode control signals for controlling to set a corresponding input / output interface mode among the plurality of input / output interface modes according to a user's needs. ; A plurality of memory cell arrays each having a plurality of memory cells; A data output buffer controlled by an internal clock to transfer data read from the memory cell to the outside; And a clock buffer circuit which is controlled by the plurality of interface mode control signals and accordingly generates and outputs the internal clock through a corresponding path among a plurality of paths set for the plurality of interface modes. Characterized in that.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a block diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, a semiconductor device according to an embodiment of the present invention includes a mode setting unit 310, memory cell arrays 322 to 340, a data output buffer 350, and a clock buffer circuit 360. .

The mode setting unit 310 generates interface mode control signals PINT1 to PINTn for controlling to set a corresponding input / output interface mode among the input / output interface modes MINT1 to MINTn according to a user's need.

The memory cell arrays 322 to 340 each include a plurality of memory cells.

The data output buffer 350 is controlled by the internal clock PCLK to transfer data read from the corresponding memory cell array among the memory cell arrays 322 to 340 to the outside.

The clock buffer circuit 360 is controlled by the interface mode control signals PINT1 to PINTn, and inputs an external clock CLK to input a corresponding path among the paths set for the interface modes MINT1 to MINTn. Internal clock PCLK is generated and output.

As described above, the semiconductor device according to the exemplary embodiment of the present invention generates the internal clock PCLK having an appropriate period according to the interface modes MINT1 to MINTn to control the data output buffer 350. Therefore, the output data driving delay time for the clock signal varies according to the interface modes MINT1 to MINTn.

4 is a block diagram of a semiconductor device having an LVTTL mode and an SSTL mode as input / output interface modes according to another embodiment of the present invention.

Referring to FIG. 4, a semiconductor device including LVTTL mode and SSTL mode as input / output interface modes according to another embodiment of the present invention may include a mode setting unit 410, memory cell arrays 422 to 440, and data output. A buffer 450 and a clock buffer circuit 460.

The mode setting unit 410 generates an interface mode control signal CONINT for controlling to set a corresponding input / output interface mode among the input / output interface modes LVTTL and SSTL according to a user's need.

Here, before using the semiconductor device, the mode setting unit 410 generates and outputs an interface mode control signal CONINT in which logic levels are divided according to an operation mode determined by a combination of external addresses by a user.

The memory cell arrays 422 to 440 each include a plurality of memory cells.

The data output buffer 450 is controlled by the internal clock PCLK to transfer data read from the corresponding memory cell array among the memory cell arrays 422 to 440 to the outside.

The clock buffer circuit 460 is controlled by the interface mode control signal CONINT, and inputs an external clock CLK to input an internal clock through a corresponding path among the paths set for the interface modes LVTTL and SSTL. Generate and output (PCLK).

FIG. 5 illustrates a circuit diagram of a circuit according to a specific embodiment of the clock buffer circuit 460 in FIG. 4.

Referring to FIG. 5, a circuit according to a specific embodiment of the clock buffer circuit 460 in FIG. 4 includes a controller 520, a driver 540, and a delay unit 560.

The controller 520 enables the clock buffer circuit 460 according to the buffer control signal CON.

The controller 520 is configured as transistors 522 and 524.

The transistor 522 is connected between the power supply terminal VDD and the driver 540 and is gated by the buffer control signal CON. That is, the transistor 522 is a PMOS transistor having a source terminal connected to the power supply terminal VDD, a drain terminal connected to the driving unit 540, and gated by the buffer control signal CON.

The transistor 524 is connected between the driver 540 and the ground terminal GND and is gated by the buffer control signal CON. That is, the transistor 524 is an NMOS transistor having a drain terminal connected to the driver 540, a source terminal connected to the ground terminal GND, and gated by the buffer control signal CON.

The driver 540 inputs an external clock CLK and senses and drives a rising edge thereof.

The driver 540 includes a current mirror circuit 542, transistors 546 and 548, and a resistor 549.

In the current mirror circuit 542, an input terminal is connected to a drain terminal of the transistor 522 constituting the control unit 520.

The current mirror circuit 542 is composed of transistors 543 and 544.

The transistor 543 is connected between the drain terminal of the transistor 522 constituting the control unit 520 and the output terminal NOUT1 of the current mirror circuit 542, and is gated by the output terminal NOUT1. The transistor 543 has a source terminal connected to the drain terminal of the transistor 522 constituting the control unit 520, a drain terminal connected to the output terminal NOUT1 of the current mirror circuit 542, and a current mirror. It is a PMOS transistor gated by the output terminal NOUT1 of the circuit 542.

The transistor 544 is connected between the drain terminal of the transistor 522 constituting the control unit 520 and the output terminal NOUT2 of the current mirror circuit 542, and is gated by the output terminal NOUT1. The transistor 544 has a source terminal connected to a drain terminal of the transistor 522 constituting the control unit 520, a drain terminal connected to an output terminal NOUT2 of the current mirror circuit 542, and a current mirror. It is a PMOS transistor gated by the output terminal NOUT1 of the circuit 542.

One end of the resistor portion 549 is connected to the ground terminal GND.

The transistor 546 is connected between the output terminal NOUT1 of the current mirror circuit 542 and the other terminal of the resistor portion 549 and is gated by the reference voltage VREF. The transistor 546 has a drain terminal connected to the output terminal NOUT1 of the current mirror circuit 542, a source terminal connected to the other terminal of the resistor unit 549, and is gated by the reference voltage VREF. Is an NMOS transistor.

The transistor 548 is connected between the output terminal NOUT2 of the current mirror circuit 542 and the other terminal of the resistor portion 549 and is gated by an external clock CLK. The transistor 548 has a drain terminal connected to the output terminal NOUT2 of the current mirror circuit 542, a source terminal connected to the other terminal of the resistor unit 549, and is gated by an external clock CLK. Is an NMOS transistor. .

The delay unit 560 delays a signal output from the driver 540 for a predetermined period according to the interface mode control signal CONINT and outputs it as an internal clock signal PCLK for controlling the data output buffer 450.

The delay unit 560 is composed of delay paths 570 and 580, and an output driver 590.

The delay path 570 is enabled by the interface mode control signal CONINT and inputs a signal output from the driver 540 to delay and output a predetermined delay period DLY1.

Delay path 570 is composed of delay means 572, inverter 574, and NAND gate 576.

The delay unit 572 inputs a signal output from the driver 540 and delays the delay period DLY1 to output the signal.

The inverter 574 receives the interface mode control signal CONINT and inverts it to output it.

The NAND gate 576 inputs a signal output from the delay means 572 and a signal output from the inverter 574, and multiplies and inverts them. The NAND gate 576 inputs a signal output from the delay means 572 and a signal output from the inverter 574 to output a signal that becomes a low ('L') level only when both are high ('H') levels. Output

The delay path 580 inputs a signal output from the driver 540 to delay and output a delay period DLY2.

The delay path 580 is configured as delay means 582 which inputs a signal output from the driver 540, delays the delay period DLY2, and outputs the delayed signal.

The output driver 590 inputs signals output from the delay paths 570 and 580, drives a corresponding signal among them, and outputs them as an internal clock signal PCLK that controls the data output buffer 550.

The output driver 590 is composed of a NAND gate 592 and an inverter 594.

The NAND gate 592 inputs signals output from the delay paths 572 and 582, and multiplies and inverts them. The NAND gate 592 inputs signals output from the delay paths 572 and 582 and outputs a signal that becomes a low ('L') level only when both are high ('H') levels.

The inverter 594 receives a signal output from the NAND gate 592, inverts the signal from the NAND gate 592, and outputs the internal clock signal PCLK that controls the data output buffer 450.

As described above, the semiconductor device according to another exemplary embodiment sets a circuit for the interface mode LVTTL, and sets the interface mode SSTL by the interface mode control signal CONINT according to the user's needs. Accordingly, an internal clock PCLK having an appropriate period is generated to control the data output buffer 450. Therefore, the output data driving delay time for the clock signal varies according to the interface modes LVTTL and SSTL.

6 is a circuit diagram of a circuit in accordance with another specific embodiment of a clock buffer circuit in a semiconductor memory device according to still another embodiment of the present invention.

Referring to FIG. 6, a circuit in accordance with another specific embodiment of a clock buffer circuit in a semiconductor device according to another exemplary embodiment includes a controller 620, a driver 640, and a delay unit 660. do.

Since the controller 620 and the driver 640 are configured in the same manner as the controller 520 and the driver 540 of FIG. 5, detailed descriptions thereof will be omitted.

The delay unit 660 is composed of delay paths 670 and 680 and an output driver 690.

The delay path 670 is configured as a delay means 672 for inputting a signal output from the driver 640 to delay and output a delay period DLY1.

Delay path 680 is composed of delay means 682, inverter 684, and NAND gate 686.

The delay means 682 inputs a signal output from the driver 640 and delays the delay period DLY2 to output the signal.

The inverter 684 receives the interface mode control signal CONINT and inverts it to output it.

The NAND gate 686 inputs a signal output from the delay means 682 and a signal output from the inverter 684, and logically multiplies and inverts them. The NAND gate 686 inputs a signal output from the delay means 682 and a signal output from the inverter 684 to output a signal that becomes a low ('L') level only when they are both high ('H') levels. Output

Since the output driver 690 has the same configuration as the output driver 590 of FIG. 5, a detailed description thereof will be omitted.

As described above, the semiconductor device according to another exemplary embodiment sets a circuit for the interface mode SSTL, and sets the interface mode LVTTL by the interface mode control signal CONINT according to the user's needs. Accordingly, an internal clock PCLK having an appropriate period is generated to control the data output buffer. Therefore, the output data driving delay time for the clock signal varies according to the interface modes LVTTL and SSTL.

In addition, the mode setting unit 310 of FIG. 3 outputs interface mode control signals PINT1 to PINTn in which logic levels are divided according to an operation mode determined by a bonding option in an assembly step of a semiconductor device. Circuits for the embodiments to the other embodiments can be constructed.

Similarly, the mode setting unit 310 of FIG. 3 outputs the interface mode control signals PINT1 to PINTn whose logic levels are divided according to an operation mode determined according to an external bias application condition for a specific pin of a semiconductor device. As a result, it is possible to construct a circuit for an embodiment of the present invention to another embodiment.

According to the present invention, since the interface mode control signal is set according to the user's needs, an internal clock having an appropriate period is generated accordingly to control the data output buffer. The data driving delay time is variable.

Claims (23)

In a semiconductor memory device having a plurality of input and output interface modes, A mode setting unit generating a plurality of interface mode control signals for controlling to set a corresponding input / output interface mode among the plurality of input / output interface modes according to a user's need; A plurality of memory cell arrays each having a plurality of memory cells; A data output buffer for transferring data read from the memory cells to the outside; And And a clock buffer circuit which is controlled by the plurality of interface mode control signals and accordingly generates and outputs the internal clock through a corresponding path among a plurality of paths set for the plurality of interface modes. A semiconductor device, characterized in that. A semiconductor memory device having an LVTTL mode and an SSTL mode as input / output interface modes, A mode setting unit for generating an interface mode control signal for controlling to set a corresponding input / output interface mode among the LVTTL mode and the SSTL mode according to a user's need; A plurality of memory cell arrays each having a plurality of memory cells; A data output buffer for transferring data read from the memory cell to the outside; And And a clock buffer circuit controlled by the interface mode control signal to input an external clock to control the data output buffer through a corresponding path. 3. The clock buffer circuit of claim 2, wherein the clock buffer circuit is A controller configured to enable the clock buffer circuit according to a buffer control signal; A driver configured to input the external clock and sense and drive the rising edge thereof; And a delay unit for delaying a signal output from the driver according to the interface mode control signal for a predetermined period and outputting the signal as an internal clock signal for controlling the data output buffer. The method of claim 3, wherein the control unit A first transistor connected between a power supply terminal and the driver and gated by the buffer control signal; And And a second transistor connected between the driver and the ground terminal and gated by the buffer control signal. The method of claim 4, wherein the first transistor And a source terminal connected to the power supply terminal, a drain terminal connected to the drive section, and a PMOS transistor gated by the buffer control signal. The method of claim 5, wherein the second transistor A semiconductor memory device comprising: a source terminal connected to the ground terminal, a drain terminal connected to the driving unit, and an NMOS transistor gated by the buffer control signal. The method of claim 6, wherein the driving unit A current mirror circuit having an input terminal connected to the drain terminal of the first transistor; A resistor unit having one terminal connected to the ground terminal; A third transistor connected between the first output terminal of the current mirror circuit and the other terminal of the resistor section and gated by a reference voltage; And And a fourth transistor connected between the second output terminal of the current mirror circuit and the other terminal of the resistor section and gated by the external clock. 8. The circuit of claim 7, wherein the current mirror circuit A fifth PMOS transistor having one terminal connected to a drain terminal of the first transistor, another terminal connected to the first output terminal, and gated by the other terminal; And And a sixth PMOS transistor connected to a drain terminal of the first transistor, another terminal connected to the second output terminal, and gated by another terminal of the fifth transistor. A semiconductor memory device. 10. The semiconductor memory device of claim 8, wherein the third transistor is an NMOS transistor. 10. The semiconductor memory device of claim 8, wherein the fourth transistor is an NMOS transistor. 12. The semiconductor memory device according to claim 10, wherein the delay unit is configured with a circuit for the LVTTL mode, and the circuit setting is changed for the SSTL mode by the interface mode control signal. The method of claim 11, wherein the delay unit A first delay path enabled by the interface mode control signal and configured to input a signal output from the driver to delay and output a predetermined first delay period; A second delay path configured to input a signal output from the driver and delay a predetermined second delay period for output; And And an output driver configured to input signals output from the first delay path and the second delay path, drive a corresponding signal among them, and output the signal as an internal clock signal for controlling the data output buffer. Memory device. 13. The method of claim 12, wherein the first delay path is First delay means for inputting a signal output from the driver and delaying the first delay period for outputting the signal; A first inverter for inputting the interface mode control signal and inverting the same; And And a first NAND gate for inputting a signal output from the first delay means and a signal output from the first inverter, AND, and inverting and inverting them. 13. The semiconductor memory device according to claim 12, wherein the second delay path includes second delay means for delaying and outputting a signal output from the driver by the predetermined second delay period. The method of claim 14, wherein the output driver A second NAND gate configured to input signals output from the first delay path and the second delay path, AND to multiply them, and to invert and output the signals; And And an inverter which inputs a signal output from the second NAND gate, inverts the signal, and outputs the internal clock signal to control the data output buffer. 11. The semiconductor memory device according to claim 10, wherein the clock buffer circuit has a circuit set for the SSTL mode, and the circuit setting of the clock buffer circuit is varied with respect to the LVTTL mode by the interface mode control signal. The method of claim 16, wherein the delay unit A first delay path configured to input a signal output from the driver to delay a predetermined first delay period and output the delayed signal; A second delay path enabled by the interface mode control signal and inputting a signal output from the driver to delay and output a predetermined second delay period; And And an output driver configured to input signals output from the first delay path and the second delay path, drive a corresponding signal among them, and output the signal as an internal clock signal for controlling the data output buffer. Memory device. 18. The semiconductor memory device according to claim 17, wherein the first delay path includes first delay means for delaying and outputting the signal output from the driver by the predetermined first delay period. 18. The method of claim 17, wherein the second delay path is Second delay means for inputting a signal output from the driver and delaying the second delay period for outputting the signal; A first inverter for inputting the interface mode control signal and inverting the same; And And a first NAND gate for inputting a signal output from the first delay means and a signal output from the first inverter, AND, and inverting and inverting them. The method of claim 19, wherein the output driver A second NAND gate configured to input signals output from the first delay path and the second delay path, AND to multiply them, and to invert and output the signals; And And an inverter which inputs a signal output from the second NAND gate, inverts the signal, and outputs the internal clock signal to control the data output buffer. The method of claim 2, wherein the mode setting unit outputs the interface mode control signal in which logic levels are classified according to an operation mode determined by a combination of external addresses by a user before using the semiconductor memory device. Semiconductor memory device. The semiconductor memory device as claimed in claim 2, wherein the mode setting unit outputs the interface mode control signal whose logic level is divided according to an operation mode determined by a bonding option in the assembling step of the semiconductor memory device. The semiconductor memory of claim 2, wherein the mode setting unit outputs the interface mode control signal having a logic level classified according to an operation mode determined according to an external bias application condition for a specific pin of the semiconductor memory device. Device.