KR19990074276A - Serial Bus Line and Data Transmission Method Using the Same - Google Patents

Abstract

The present invention relates to a serial bus line suitable for minimizing an area occupied by a bus and a method of transmitting data using the same. And a bitstream structure consisting of a sync word, an address word, a data word, and an end word between the respective chips. A step of outputting serial data to the register section, a step of comparing its address with an address sent from the main chip when a synchronization word is detected from the serial register section of the peripheral chip; and if the address is the same, The serial register section after the address And storing the data stored in the parallel register unit in parallel, and outputting the data stored in the parallel register unit in parallel when an end word is detected from the serial register unit.

Description

Serial Bus Line and Data Transmission Method Using the Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus line. In particular, in the data transfer between chip and chip, a serial bus line suitable for converting parallel data into serial data and transmitting the same. And a data transmission method using the same.

Hereinafter, a conventional parallel global bus line will be described with reference to the accompanying drawings.

The conventional global bus line can transmit 8 bits of data, 8 bits of address, and 1 bit of acknowledgment signal.

1 is a block diagram of a parallel global bus line for data transmission between a main chip and a plurality of peripheral chips according to the prior art.

As shown in FIG. 1, a 17-bit global bus capable of transmitting 8-bit data, 8-bit addresses, and 1-bit acknowledgment signal (Ack) between the main chip 11 and the peripheral chips 12. The line is connected.

Each peripheral chip 12 has its own unique address. In addition, since the functions of the peripheral chips 12 are different from each other, different commands are received from the main chip 11 to operate independently.

The main chip 11 controls the signal flow of the entire chip and is responsible for the interface between the peripheral chips 12 to generate commands.

As such, a method of transmitting data using a conventional global bus line is as follows.

First, in order to send data to any of the plurality of peripheral chips 12, the unique address of the peripheral chip to receive the data is loaded on the global bus line.

Since the global bus line is connected to each peripheral chip, any peripheral chip having the same address as the address printed on the global bus line is activated.

Therefore, the main chip 11 loads data on an 8-bit data bus, and the peripheral chip prepares to receive a command.

When ready to receive data, the peripheral chip receives the data output from the main chip 11 by the 1-bit acknowledgment signal (Ack) to perform its function.

However, since the conventional parallel global bus lines have a total of 17 bits, the area occupied by the bus lines becomes excessively large in connecting the chips with the chips. Therefore, when implementing the multi-chip, there was a problem that the chip size increases.

The present invention has been made to solve the above problems, to provide a serial bus line and a data transmission method using a flexible layout configuration by reducing the interconnection route (chip) between chips using a serial bus line. Its purpose is to.

1 illustrates a parallel global line connected between conventional chips.

2 is a diagram showing the structure of a serial bus line of the present invention.

Figure 3 shows a serial busline connected between the chips of the present invention

4 is a detailed configuration diagram of a data conversion unit according to the present invention;

5 is a flowchart illustrating a data transmission method using a serial bus line of the present invention.

Explanation of symbols for main parts of the drawings

11: main chip 12: peripheral chip

31: serial bus line 32: data conversion unit

41: serial register section 42: sync word detection section

43: end word detection unit 44: address comparison unit

45: counter portion 46: parallel register portion

The serial busline of the present invention for achieving the above object has a bitstream structure consisting of a plurality of chips, a synchronization word, an address word, a data word, and an end word between the respective chips, the serial busline of the present invention The data transmission method using the step of the main chip outputs the serial data to the serial register of the peripheral chip through the serial bus line, and if a sync word is detected from the serial register of the peripheral chip, its own address and the address sent from the main chip Comparing the data with each other; if the addresses are the same, storing data stored in the serial register section in parallel with the address by a data transmission signal; and if an end word is detected from the serial register section. Stored in the parallel register It characterized by comprising the step of parallel and outputs the data.

Hereinafter, a serial bus line and a data transmission method using the same according to the present invention will be described with reference to the accompanying drawings.

2 illustrates a structure of a bitstream according to a serial bus line of the present invention.

The structure of the serial busline of the present invention is composed of a 32-bit sync word, an 8-bit address word, an 8-bit data word, and a 32-bit end word.

Here, the sync word is data indicating that the main chip is to output data, and the end word is data indicating that the transmission of data has been completed.

The synchronization word is first transmitted through the serial bus line as shown in FIG. 2, and then sequentially transmitted in the order of address, data, and end word.

Since the serial bus lines are connected to the peripheral chips, when the peripheral chip detects the synchronization word, it can be seen that the 8 bits following the synchronization word are the address word and the next 8 bits are the data word.

An 8-bit address word can have 256 (= 2 ⁸ ) different addresses. In some cases, if the number of peripheral chips is small or large, it can be changed to 256 or more.

The 8-bit data word may have a structure of a command and may provide header information to inform the contents of an operand.

If necessary, the dataword can be extended indefinitely and can be regarded as a dataword until immediately before the end word.

3 briefly illustrates a configuration between a main chip and a plurality of peripheral chips according to the present invention.

As shown in FIG. 3, a serial bus line 31 is connected between the plurality of peripheral chips 12 and the main chip 11.

Accordingly, when the serial bus line of the present invention is used as compared to the conventional 17-bit parallel bus line, the area occupied by the bus line in the chip can be minimized.

As shown in FIG. 3, a data converter 32 is configured at a signal input terminal of each peripheral chip 12.

Usually, the signal transmission in the peripheral chip 12 is made in parallel.

Therefore, the data converter 32 converts the data transmitted serially through the serial bus line 31 in parallel to perform a function of the peripheral chip 12.

4 is a detailed configuration diagram of a data conversion unit according to the present invention.

As shown in Fig. 4, a serial register 41 for storing data (including an address) serially input through the serial bus line 31 and a sync word from the serial register 41 are detected. A sync word detector 42, an end word detector 43 for detecting an end word from the serial register 41, and an address comparison unit for comparing an address input to the serial register 41 with its own address. (44), a counter unit (45) for outputting a data conversion signal to the serial register unit (41) in accordance with the control signal of the address comparison unit (44), and the serial in accordance with the control signal of the counter unit (45). It comprises a parallel register section 46 for parallel storage of serial data stored in the register section 41.

Here, the counter unit 45 is proportional to the number of bits of the data. In the embodiment of the present invention, since the bit assigned as the data bit is 8 bits, the counter unit 45 is composed of a 3 (8 = 2 ³ ) bit counter.

The sync word detector 42 outputs an instruction valid signal to the counter 45 and the parallel register 46 when a sync word is detected from the serial register 41.

The counter unit 45 and the pattern register unit 46 are activated by the instruction valid signal.

Referring to the operation of the data conversion unit as follows.

Serial bitstream data in sync word-address-data-endword order will always pass through the serial register 41.

The synchronizing word detector 42 detects whether the synchronizing word has been filled in the serial register 41 and transmits a command valid signal to the counter unit 45 and the parallel register unit 46.

The data coming after the sync word is an address, which is the address of the peripheral chip 12 to receive data from the main chip.

Therefore, the address comparison unit 44 of FIG. 4 compares its own address with the address coming through the serial bus line.

If they are the same, a control signal is given to the counter 45, and if it is not the same, the data to be sent from the main chip 11 is not the data to be received and the control signal is not given.

Subsequently, if the address comes in, then a data bit comes in. The data is also stored in the serial register section 41.

At this time, the counter 45 receiving the control signal from the address comparator 44 outputs the data conversion signal to the serial register 41.

Accordingly, data stored in the serial register section 41 is parallelly stored in the parallel register section 46 while the counter section 45 counts.

Thereafter, when the end word detector 43 detects the end word from the serial register unit 41, since the data transfer is completed to the parallel register unit 46, the control signal for outputting the stored data is output.

When the parallel register unit 46 receiving the control signal from the end word detector 43 outputs data, the peripheral chip 12 performs its function according to the data.

The data transmission method using the serial bus line will now be described with reference to a flowchart.

5 is a flowchart for explaining a data transmission method of the present invention.

As shown in FIG. 5, the main chip 11 outputs data in synchronous word-address-data-endword order through a serial bus line (501).

As described above, the main chip 11 and the peripheral chip 12 are connected by serial bus lines, and the peripheral chips 12 are also connected by serial bus lines.

The sync word detector 42 of the data converter 32 located at the signal input terminal of each peripheral chip 12 detects whether all the sync words are stored in the serial register 41 (502).

It is determined whether the sync word has been detected (503), and if detected, the sync word detector 42 outputs an instruction valid signal to each block in the chip (504).

The data input to the serial register section 41 after the sync word is an address.

When an address is input, the address comparison unit 44 compares its own address with the input address (505).

If it is determined whether the addresses are the same (506), and if they are the same, it is determined that the main chip 11 has sent data to itself and outputs a control signal to the counter unit 45 (507).

That is, since the main chip 11 and each peripheral chip 12 are all connected through the serial bus line, the main chip 11 outputs the address of the peripheral chip 12 to which data is to be sent to the serial bus line. .

Therefore, when each peripheral chip 12 compares its own address with the address input through the serial bus line, it can be known which chip receives data from the main chip 11.

Next, data input to the serial register section 41 after the address.

When the data is filled in the serial register section 41, the counter section 45 outputs a data transmission signal to the serial register section 41 (508).

Therefore, the data stored in the serial register section 41 is transferred to the parallel register section 46 and parallelly stored while the counter section 45 counts (509).

At this time, the end word detector 43 determines whether the end word is detected (510), and if the data continues to enter the serial register 41, the end word is not detected.

Thereafter, when all data enter the serial register unit 41, an end word is detected, and the end word detector 43 outputs a control signal informing that the data transfer is completed to the parallel register unit 46 (511). .

Here, unless the end word is detected, the input data is irrelevant as valid data.

The parallel register 46, which receives the control signal from the end word detector 43, transfers data to several blocks in the chip by the clock signal to perform its function (512).

As described above, the serial bus line and the data transmission method using the same have the following effects.

17-bit buslines are converted to 1-bit buslines to minimize the area occupied by buslines in the system and to reduce the busline connection route between each peripheral.

In addition, when used on a system board, the board area is reduced.

Claims (6)

A number of chips, And a bus line having a bitstream structure including a sync word, an address word, a data word, and an end word between the chips. The method of claim 1, Wherein the sync word, address word, data word, and end word are allotted the number of bits on condition to optimize data discrimination between the words. 3. The serial bus line of claim 2, wherein the number of bits allocated to the sync word, address word, data word, and end word is 32 bits, 8 bits, 8 bits, and 32 bits, respectively. A serial register unit for storing serial data input through a bus line at a signal input terminal of each chip; A sync word detector for detecting a sync word from the serial register section; An end word detector for detecting an end word from the serial register; An address comparison unit for comparing an address inputted to the serial register unit with its own address, A counter unit for outputting a data transmission signal to the serial register unit; And a data converter configured to parallelly store serial data stored in a serial register according to a signal of the counter. A step in which the main chip outputs serial data through the serial bus line to the serial register of the peripheral chip; Comparing the own address with the address sent from the main chip when a sync word is detected from the serial register of the peripheral chip; If the addresses are equal to each other, parallel storing the data stored in the serial register section next to the address by a data transmission signal in parallel; And outputting data stored in the parallel register unit in parallel when an end word is detected from the serial register unit. The method of claim 5, The data input to the serial register until the end word is detected, the data is transmitted using the serial bus line, characterized in that the irrelevant data.