KR19990073422A - A MOSFET with advantages of SOI MOSFET and its fabrication method - Google Patents

Abstract

The present invention relates to the structure and fabrication method of a MOSFET device, unlike the structure of a typical SOI MOSFET, it is possible to form an SOI device without using an expensive SOI wafer by forming an oxide film inside a single crystal semiconductor only at the place where the device is to be made. The proposed method can be fabricated and the floating body phenomenon can be eliminated because of the unique device structure, thereby improving device characteristics. The present invention inserts an oxygen ion implantation step at the beginning of the MOSFET manufacturing process so that a certain thickness of an oxide film exists only under the source, drain, and gate of the MOSFET, and has the same polarity as the substrate between the source and drain junctions and the oxide film. Impurities were additionally implanted to form a semiconductor region so that the bottom of the MOSFET's channel and the semiconductor substrate were electrically connected to eliminate the floating body effect.

Description

A MOSFET with advantages of SOI MOSFET and its fabrication method

The present invention relates to a MOSFET having a merit of SOI MOSFET and a method of manufacturing the same, and a floating voltage drop or threshold voltage change due to a parasitic transistor generated during operation of a general MOSFET device. It eliminates the floating body effect, and has the advantages of SOI MOSFETs in the manufacturing process without the use of expensive Silicon On Insulator (SOI) wafers. The present invention relates to a MOSFET and a method of manufacturing the same.

In general, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a structure consisting of metal, oxide film, and semiconductor formed by oxidizing a silicon semiconductor surface to form an insulating oxide film (SiO ₂ ). It has a basic structure as shown in Figs. 1A to 1B.

As shown in FIG. 1A, the p-channel MOSFET is made of an n-type silicon (Si) substrate that is lightly doped (adding impurities), and diffuses two regions to deeply dop the p-type impurities, thereby source. And drain.

At this time, a region between two p-type portions is a channel, and a gate is formed by applying an insulated dielectric such as silicon oxide to the channel.

Applying a negative voltage to the gate terminal (based on the substrate) generates an electric field induced in the channel to attract a p-type carrier from the substrate. If the negative voltage of the gate is larger than the threshold voltage, the channel region under the gate is inverted to generate a plurality of p-type carriers, which becomes a path for current conduction, and is formed between the source and the drain. If the voltage difference is maintained, current flows.

1B is an n-channel MOSFET, which is manufactured by doping n-type impurities to a p-type silicon (Si) substrate as opposed to FIG. 1A, and a detailed description thereof will be omitted since the manufacturing process is the same as the above-described p-channel MOSFET.

Silicon on Insulator Metal-Oxide-Semiconductor Field Effect Transistor (SOI MOSFET) is a type of device having a MOSFET structure and uses a semiconductor substrate having a very special structure as shown in FIG. 2.

SOI MOSFETs have a structural feature that is made on a silicon thin film existing on an insulator (mainly an oxide film), whereas a silicon element of a typical MOSFET is made on a silicon substrate, and a latch-up problem that is a problem in a general MOSFET structure is problematic. It does not occur and has device characteristics such as low parasitic capacitance (Parasitic Capacitance) to enable high-speed operation.

In FIG. 2, reference numeral 100 denotes a silicon oxide film layer, and 110 and 120 denote semiconductor layers such as silicon.

Such a substrate is made by using a bonded and etch-back method of bonding two semiconductor wafers on which an oxide film is formed on a surface thereof, and then polishing one side thereof, or injecting oxygen ions at a high density into a semiconductor wafer. There is a SIM0X method for forming an oxide layer by heat treatment, but this has been a problem in expanding its use range despite the advantages of a device having a difficult manufacturing method or a very expensive price. Even in the characteristics of electrical devices, SOI MOSFET devices manufactured in the area above the silicon oxide film are separated from the substrate and are in an electrically floating state, causing problems such as breakdown voltage and threshold voltage change due to floating body phenomenon. come.

The present invention has been made to improve the method of fabricating the SOI MOSFET as described above. In operation of the conventional SOI MOSFET device, a breakdown voltage or threshold voltage caused by a parasitic transistor is changed according to a previous operation state. Eliminates changing floating body effects, improves manufacturing processes, and benefits from SOI MOSFETs without the use of expensive Silicon on Insulator (SOI) wafers. It is an object of the present invention to provide a MOSFET having a merit and a method of manufacturing the same.

Figure 1a shows the structure of a typical P-channel MOSFET

Figure 1b shows the structure of a typical N-channel MOSFET

2 is a cross-sectional view of a commonly used silicon on insulator (SOI) semiconductor wafer

3 is a cross-sectional view of a typical single crystal semiconductor wafer

4 is a cross-sectional view of a silicon nitride film deposited on the single crystal semiconductor wafer of FIG. 3 and selectively removed through photolithography and chemical corrosion processes.

5 is a cross-sectional view of a state in which a thick oxide film is formed on a portion which is not covered with a silicon nitride film by applying a thermal oxidation process to the wafer of FIG. 4.

FIG. 6A illustrates a state after corrosion of a single crystal semiconductor not protected by a silicon nitride film by chemical corrosion instead of the thermal oxidation process of FIG. 5.

FIG. 6B is a state in which a groove is filled by depositing a silicon oxide film on a region where the single crystal semiconductor is selectively removed in FIG. 6A;

FIG. 7 is a cross-sectional view of a state in which an oxide film is formed inside a single crystal semiconductor only at a site where a device is fabricated by removing a silicon nitride film, implanting oxygen ions into the entire wafer, and performing a heat treatment.

FIG. 8 is a state in which a gate oxide film and a gate electrode material are deposited on the structure of FIG. 7.

FIG. 9 is a state in which the gate oxide film and the gate electrode material deposited in FIG. 8 are formed into a gate shape by using a photolithography technique and a chemical corrosion process.

10 is a cross-sectional view after ion implantation of ions having the same polarity as a substrate with high energy, and source / drain bonding is performed by ion implantation and heat treatment.

<Description of the symbols for the main parts of the drawings>

100: oxide film layer formed inside the single crystal semiconductor

110: single crystal semiconductor layer to be made MOSFET

120: single crystal semiconductor substrate

410: single crystal region of silicon or other semiconductor

420: silicon nitride film or anti-oxidation thin film

510: oxide film of silicon oxide film or other semiconductor

610: Trench obtained by photolithography and chemical corrosion process

620: oxide film

710: oxide film formed inside the single crystal region of silicon or other semiconductor

810 gate oxide film

820: Gate Electrode Material

910: source, drain junction

920: semiconductor region of the same polarity as the substrate

930: semiconductor substrate

940: region including the channel and depletion region of the MOSFET

Hereinafter, described in detail by the accompanying drawings as follows.

3 is a cross-sectional view of a silicon semiconductor wafer. To make an N-type MOSFET, the wafer must contain P-type impurities, and to make a P-type MOSFET, the wafer must be doped with N-type impurities.

FIG. 4 is a silicon nitride film or the like coated on the silicon semiconductor wafer of FIG. 3 using a patterning technique to form a MOSFET. Reference numeral 410 denotes a silicon wafer and 420 denotes a silicon nitride film.

FIG. 5 shows that a thick silicon oxide film is formed on a portion not covered by the silicon nitride film by applying a high temperature oxidation process to the wafer of FIG. Since the silicon nitride film does not react with oxygen, the silicon oxide film is not formed in the region coated with the silicon nitride film. Reference numeral 510 denotes a silicon oxide film formed through an oxidation process.

Meanwhile, the silicon oxide film may be implemented through a high temperature diffusion process in an oxygen atmosphere or may use a trench method. In the trench method, as shown in FIG. 6A, a groove is formed by removing silicon by chemical corrosion at a place where an oxide film is to be formed, and then, as shown in FIG. 6B, an oxide film is deposited to fill the groove with the oxide film. In FIG. 6, reference numeral 610 is a trench formed by a chemical corrosion process, and 620 is a silicon oxide film deposited on the trench.

FIG. 7 illustrates that after removing the silicon nitride film applied to FIG. 6, oxygen ions are ion-implanted at high density and heat treated at a high temperature to form a silicon oxide layer (reference numeral 710) in the wafer. The thickness of the oxide film produced in this process is determined by the amount and energy of oxygen ions to be injected. On the other hand, the thick silicon oxide film is amorphous by the high temperature oxidation process or the trench process, and oxygen ions do not pass and no additional oxide film is formed. When implanting oxygen ions, an amorphous silicon oxide film may be applied for several tens of nanometers to prevent ion reflection on the wafer surface.

Fig. 8 shows a state where a gate oxide film (reference numeral 810) of several nanometers of MOSFET is applied to the wafer surface, and a polycrystalline silicon thin film (reference numeral 820) or the like to be used as a gate electrode is applied thereon. Additional ion implantation may be performed to control the threshold voltage of the M0SFET prior to the silicon oxide coating process to achieve the desired device characteristics.

FIG. 9 is a view illustrating a gate electrode shape of the polycrystalline silicon thin film of FIG. 8 by using a semiconductor patterning technique, and the rest is removed. Where the polycrystalline silicon is removed, the source and drain will be fabricated so that the gate oxide film (810) is further removed.

FIG. 10 is a cross-sectional view of source / drain ion implantation and heat treatment on a wafer having the structure of FIG. 9 to implant group 5 impurities when fabricating an N-type MOSFET and to implant group 3 impurities when fabricating a P-type MOSFET. In other words, a source / drain is formed by doping an impurity having a polarity opposite to that of the doped substrate. On the other hand, just before the source / drain ion implantation, ion implantation of the same kind as the substrate is performed at a high implantation energy to prevent the source / drain from diffusing to the oxide film interface inside the wafer during the heat treatment process. Reference numeral 910 denotes an N + or P + region having a low resistance formed by source / drain ion implantation and heat treatment, and 920 denotes a region having a relatively high impurity concentration caused by ion implantation of the same kind as a substrate.

The device fabricated as described above has an oxide film having a thickness of several hundred nanometers under the source, gate, and drain constituting the MOSFET, and thus basically has the same structure as the SOI structure. No oxide film exists in the. As a result, the stress due to the difference in thermal expansion coefficient between silicon oxide film and silicon is reduced. In particular, instead of using a specially manufactured SOI wafer to fabricate a MOSFET, a silicon wafer is used, and the SOI structure is used only in the parts necessary for the process. By reducing the manufacturing cost can be reduced.

A feature of the present invention, in part making the SOI structure, is that it eliminates the floating body effect, which is a decisive disadvantage of conventional SOI MOSFET devices.

The floating body effect is that the silicon thin film on the wafer surface, which fabricates the device in a conventional SOI wafer, is electrically suspended from the substrate, thereby preventing efficient removal of the sender caused by the collision transition through the substrate. This is a phenomenon that the lowering or breakdown voltage of the device is abnormally low, making the operating range of the device very small.

The device structure of FIG. 10 proposed in the present invention has a region 920 under the source / drain region and includes impurities of the same kind as the substrate, and the channel region 940 of the device is electrically connected to the substrate 930 through the region 920. Ting body does not occur.

Another advantage of the present invention is that the substrate current due to the collision transition is smaller than that of a general MOSFET which is not an SOI structure. The collision transition occurs most in the vicinity of the drain junction where the electric field is strong. The device structure proposed in the present invention has a silicon oxide film as an insulator under the drain junction, so that the collision transition occurs only at the side of the drain junction. Since this area is only a part of the total drain area, there is less collision transition and thus the breakdown voltage of the device can be kept sufficiently high.

According to the present invention, a silicon oxide film is formed deep into a device generation region through oxygen implantation in a process using a general wafer without using an expensive SOI wafer, thereby reducing manufacturing costs and minimizing a silicon oxide formation area. This improves device characteristics by reducing stress between the oxide and silicon. In addition, unlike the conventional SOI MOSFET, the MOSFET fabricated on the oxide film of the present invention does not contact the oxide film with the bottom of the source and drain junctions so that the channel region of the device is electrically connected to the substrate, thereby eliminating the floating body effect. Breakdown voltage and threshold voltage drop can be prevented. For example, Figure 11 shows the current voltage characteristics of a device with a general SOI structure. Because of the floating body effect, the saturation current increases linearly with the drain voltage and lowers the breakdown voltage than the current voltage characteristics of the device proposed in Figure 12. Able to know

Claims (3)

In a MOSFET structure having a metal, an oxide film, and a semiconductor layer structure formed by oxidizing a semiconductor surface such as silicon to form an insulating oxide film, and providing a metal electrode on the surface, A single crystal semiconductor layer 410 such as silicon; A silicon oxide film 510 formed by heating while supplying oxygen over the remaining silicon nitride film 420 and the single crystal semiconductor layer 410 after selective removal; A silicon oxide film 710 formed in the single crystal semiconductor layer 410; A gate silicon oxide film 810 on the order of several nanometers and a polycrystalline silicon thin film 820 formed by a deposition method thereon; A gate electrode left after selectively removing the polycrystalline silicon film and the gate silicon oxide film by applying photolithography technique and chemical corrosion method; A source / drain junction 910 formed in the silicon single crystal region between the gate electrode and the silicon oxide film 510; MOSFETs having the advantages of SOI MOSFETs with a semiconductor single crystal layer 920 having the same polarity as the substrate under source / drain junction 910 and without floating body effects. The method of claim 1, Selectively forming an amorphous silicon oxide film 510 having a thickness through which accelerated oxygen ions cannot penetrate, ion implanting oxygen ions with high energy, and thermally treating the silicon oxide film 710 selectively in a single crystal semiconductor. Forming MOSFET manufacturing process. The method of claim 1, Prior to the source / drain ion implantation, the impurity ions having the same polarity as the substrate may be used at high energy to form the semiconductor region 920 having the same polarity as the substrate between the source / drain junction 910 and the silicon oxide film 710 inside the single crystal semiconductor. MOSFET implantation process.