KR19990071554A - Multi-port cache memory with address conflict detection - Google Patents

Abstract

A multiport cache memory is started. The multiport cache operates in a microsystem and includes multiple memory banks and multiple ports to allow access to that bank. The collision detection circuit detects simultaneous addressing of the first memory bank through the first port and the second port and stalls the operation of the microprocessor for a predetermined number of clock cycles in response to detection of concurrent addressing. The collision avoidance circuit allows access to the first bank through the first port during stall and allows access via the second port after the stall is completed. Generally, the collision avoidance circuit allows access through a port that attempts to access the first memory bank in order of increasing priority during successive clock cycles while the microprocessor is stalled. One or more ports attempting to access the first bank may be allowed access before and after the stall of the microprocessor. Each bank has a single port. The banks have non-overlapping address spaces and are addressed such that the words in the cache block are distributed among the multiple banks.

Description

Multi-port cache memory with address conflict detection

The present invention relates to cache memories, and more particularly to caches having multiple access ports.

Cache is a small, high-speed memory disposed between the processor and main memory to reduce the validity time required by the processor to access addresses, instructions, or data stored primarily in main memory. For example, when a processor reads a word from main memory, the word and the adjacent word are read as a block from main memory to cache. Typically, the processor is then likely to attempt to access one of the adjacent words in the block next. Due to the localization of these reference characteristics, the bus traffic in the main memory is reduced since the processor initiates the next direct data exchange with the cache. Cache access takes less time than main memory access. Thus, the use of a cache improves the throughput of the processor.

Many modem microprocessors execute multiple instructions within the same processor clock cycle. For example, the processor may execute memory operations simultaneously. In this case, the processor requires concurrent access to multiple words stored in the cache memory. Thus, the cache includes multiple ports each handling a separate data exchange.

The multiport cache may be implemented as a single multiport SRAM. However, such a configuration is very slow in operation and occupies a relatively large chip area. Alternatively, a dual port cache may be implemented by two single port memory arrays, each corresponding to one of the cache ports, as described in U.S. Patent No. 5,359,557 to Aipperspach et al. The two arrays have the same address space. This cumbersome device requires a complex data coherence circuit to ensure that the array stores the same data when the data is modified in one of the cache ports. In addition, using two arrays to store a redundant copy of the same data will inevitably take up a large chip area.

Therefore, it is desirable to find a more compact and more efficient means of implementing multiport cache memory.

The present invention provides multiport cache memory. The multiport cache memory operates in a microprocessor system and includes multiple memory banks and multiple ports to enable access to the banks. The collision detection circuit detects the simultaneous addressing of the first memory bank through the first port and the second port and stalls the microprocessor operation for a predetermined number of clock cycles in response to detection of concurrent addressing. The collision avoidance circuit allows access to the first bank through the first port during stall and allows access via the second port after the stall is completed. Generally, the collision avoidance circuit allows access through a port that attempts to access the first memory bank in an order of increasing priority during successive clock cycles while the microprocessor is stalled. Access to one or more ports attempting to access the first bank may be allowed before or after the stall of the microprocessor. Each bank has a single port. The banks have non-overlapping address spaces and are addressed such that the words in the cache block are distributed among the multiple banks.

The objects, features and advantages of the present invention will become apparent to those skilled in the art in view of the following detailed description, which provides examples of the structure and operation of the present invention.

1 is a diagram of a computer system having a multiport cache of the present invention.

2 is a block diagram illustrating a processor coupled to a multiport cache of the present invention.

3A is a timing chart showing cache timing when there is no bank conflict;

3B is a timing chart showing cache timing when there is a bank conflict;

The present invention provides multiport cache memory with multiple memory banks. In the following description, numerous details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that these specific details are not required. In addition, well-known elements, elements, processing steps and the like will not be described in detail so as not to obscure the present invention.

1 shows a computer system having a multiport CPU 100, a main memory 102, a main memory interface 104, and a multiport cache 106 of the present invention. The main memory interface 104 manages the exchange of information between the cache 106 and the main memory 102 to maintain cache coherence when CPU access misses the cache or when the CPU writes new data to the cache. Although the cache 106 is shown as having two ports, those skilled in the art will appreciate that the present invention can be easily extended to a cache having any number of ports.

Preferably, the processor is capable of executing multiple parallel operations and thus requires concurrent access to one or more words stored in the cache. In an arrangement (not shown), separate processors or other agents may each require access to the corresponding cache port.

2 is a detailed block diagram of a processor 100 coupled to an embodiment of the cache 106 of the present invention. In this example, the cache is a two-way set combination cache. Unlike the prior art, the cache of the present invention does not use dual port SRAMs or redundant single port arrays that store the same data. Instead, the present invention uses a number of single port memory banks, where each bank stores data in a non-overlapping address space. Preferably, each bank may be accessed by any port. All ports can perform concurrent access to the cache, unless both ports attempt to access the same bank. In the case of a bank collision, that is, when two ports attempt to access the same bank, the cache controls the timing of access as follows.

According to the present invention, the CPU 100 may cause multiple accesses to the cache 106, represented by a first address A0 and a second address A1. These addresses correspond to the two ports 201 and 203 of the cache of this example. In this example, the cache itself includes the first bank 200 (bank 0) and the second bank 202 (bank 1). Here, each bank holds 8 kilobytes (8 kilobytes) of data, and four bytes contain one 32 bit word. Thus, each bank stores 2K words. In addition, each cache block is two words long, and two blocks comprise a set of two-way set combination cache of the present example. It will be appreciated by those skilled in the art that the present invention may be applied to other memory configurations, and in particular, the number of banks need not necessarily be the same as the number of ports.

Each bank is coupled to a plurality of read buses 204 via a corresponding three-phase bus driver 206, and each read bus 204 corresponds to one of the ports. Each bank is also coupled to a plurality of write buses 208 via a write multiplexer 210, and each write bus 208 corresponds to one of the ports.

The read and write buses 204 and 208 are coupled to the input and output ports of the CPU 100 (the combination is not shown for simplicity of illustration).

The circuit for addressing the bank is divided into an address circuit dedicated to the corresponding port and an address circuit common to both ports. In this embodiment, each port is coupled to a dual tag RAM 212, where each tag array 214 corresponds to a one way set combination cache. The tag from each array is fed to a corresponding comparator 216, which compares the tag and the tag field of the corresponding port address. As a result, a hit signal is delivered to the corresponding port input of the heat multiplexer 218 for each bank. Where the hit signal is a two-bit " one hot " signal that takes a logic one value at the most significant bit. Each bank is also a row multiplexer 220 that receives the set index field of each port address. In addition, read / write control signals are transferred from each CPU port to the corresponding inputs of the read / write multiplexers (not shown) of each bank to indicate whether the read memory operation should be performed or the write memory operation should be performed. In one embodiment, a write enable signal from each port is passed to a corresponding input of the write multiplexer. Similarly, a read enable signal from each port is passed to the corresponding input of the read multiplexer. The output of the multiplexer is coupled to the write enable input and the read enable input of the corresponding bank, respectively. Here, read and write multiplexers are collectively referred to as " read / write multiplexers ".

The address circuit, which is common to both ports, includes a collision detection circuit 222 that receives the bank address portion of the port address. In this example, each bank address is passed through a 1: 2 bank decoder 224 which responsively generates a bank select signal. For example, if the zero bank address bit indicates the selection of bank 0, the bank decoder 224 will output 1 from its bank 0 output and 0 from the bank 1 output. The bank selection signal bd is supplied from the respective port decoders to the corresponding collision elimination circuit 226 for each bank. The output of the collision solving circuit 226 controls a row multiplexer 220, a heat multiplexer 218 and a read / write multiplexer (not shown) for each bank that determines which port should access that bank. The conflict resolution circuitry 226 also controls the three-phase driver 206 and the write bus multiplexer 210 for the read bus 204 (Figure 2 takes active high) Ensuring access to the bus.

In one example of the memory configuration of the cache of Figure 2, each bank stores 8 KB of data and each word contains 4 bytes. Each cache block contains two words. Since the cache is a two-way set associative cache, the memory contains a 1K set with two blocks per set. Bit 2 of the address selects the bank, and bits 3-12 select one of the sets. Bits 13-31 of the address are used for tag comparisons to indicate the presence of an address block in the cache.

The operation of the cache of the present invention will be described with reference to the timing diagrams of Figures 3A and 3B. FIG. 3A shows cache timing in which there is no bank conflict. Figure 3B shows cache timing with bank conflict. In either case, the CPU intends to perform simultaneous access of the cache by deriving address A0 from the first CPU port 228 and address A1 from the second CPU port 230. [ The address is received by the first cache port 201 and the second cache port 203 via the internal CPU bus 232. In this example, during cycle 0, the second bit of the address is supplied to the collision detection circuit 222 to determine if both ports are attempting to access the same memory bank. Here, it is assumed that A0 [2] = 0 and A1 [2] = 1. In this case, the bank address decoder 224 for port 0 will output the bank select signal bd [0] [0] = 1 to the conflict resolving circuit 226 for bank 0 200, And outputs the bank selection signal bd [0] [1] = 0 to the eliminating circuit 226. [ the bank address decoder 224 for port1 201 will output the bank select signal bd [1] [0] = 0 to the conflict resolver circuit 226 for bank0 200, And outputs the bank selection signal bank selection signal bd [1] [1] = 1 to the elimination circuit 226. At cycle 0, the collision resolution circuit 226 determines which port input is to be delivered to each bank by the row multiplexer 220, the heat multiplexer 218, and the read / write multiplexer, Selects an appropriate read or write bus to communicate with that bank (depending on whether the operation is being performed).

For this two-port example, the conflict resolution circuit 226 realizes the following logical expression.

sel [0] [i] = bd [0] [i] AND NOT (sel_ctrl [1])

1] [i] = NOT (bd [0] [i] AND bd [1] [i]) OR sel_ctrl [1]

Here, the port selection signal sel [j] [i] provides access to bank i at input port j if sel [j] [i] = 1. When a bank collision occurs, the collision resolution circuit first allows port0, the lower numbered port, to access the addressed bank. Sel_ctrl [1] = 0 in that clock cycle. In the next cycle, the override signal sel_ctrl [1] takes a value of 1 to provide priority of access to port 1. [

2, the two-bit signal sel0 represents two port selection signals for bank0 and the two-bit signal sel1 represents two port selection signals for bank1. These combined signals select the appropriate port input to the multiplexer. Alternatively, the conflict resolution logic may be implemented by any circuitry that realizes the logic of Table 1.

port1 port0 port1 port0 bank1bd [1] [1] bank0bd [1] [0] bank1bd [0] [1] bank0bd [0] [0] bank1SEL [1] [1] bank0SEL [1] [0] bank1SEL [0] [1] bank0SEL [0] [0] 0 One 0 One 0/0 0/1 0/0 1/0 0 One One 0 0/0 1/0 1/0 0/0 One 0 0 One 1/0 0/0 0/0 1/0 One 0 One 0 0/1 0/0 1/0 0/0

In Table 1, " x / y " indicates that the port selection signal takes the value of x in one clock cycle and takes the value of y in the next clock cycle.

In this example, bd [0] [0] = 1 and bd [1] [0] = 0, bd [0] [1] = 0, and bd [1] [1] = 1. Thus, in cycle 0 of FIG. 3A,

sel [0] [0] = 1

sel [0] [1] = 0

sel [1] [0] = 0

sel [1] [1] = 1

to be.

When there is no collision, the sel-ctrl invalidation signal is not activated. Thus, bank0 is accessible to port0, and bank1 is accessible to port1.

In short, the conflict resolution circuit 226 determines which port communicates with each bank. This selection is made based on the bank address field of the port address bit 2 in this example. The other bits are used to address the specific word in the bank. Bits 3-12 are the set indexes fed into the dual tag array for each port. In this example, one set includes two blocks, one block per each bank. Bits 13-31 include a tag address field that compares the tags from the dual tag array 212.

If the comparison results in a hit in one of the arrays, the hit signal selects the word in that block. If the cache misses a port, the miss is adjusted by loading the miss block into the cache. The action is retried as if the miss did not occur, resulting in a hit. For example, if one instruction attempts simultaneous access and one port is hit while another pod is missed, the miss is first adjusted. The command is then resumed, resulting in two bits, and the conflict resolution circuit operates as described herein.

The set index and hit signal are routed to the correct bank via the multiplexer controlled by the conflict resolution circuitry 226. [ Assume a hit for both port addresses. During cycle 0, the hit signal hit0 is routed from port0 201 to the hit input of bank0 220 via the heat multiplexer 218 and the hit signal hit1 is routed from port1 203 to bank1 202 via heat multiplexer 218 Lt; / RTI > Data read from port 0 (201) or written to port 0 is represented by X, and data read from port 1 (203) or written to port 1 is represented by Y. During cycle 1, these two ports communicate with one bank. Here, the X data from port0 (201) is read from bank0 (200) or written to bank0, and the Y data from port1 is read from bank1 (202) or written to bank1.

3B is a timing diagram illustrating the operation of the cache of the present invention in the event of a bank conflict. In this example, it is assumed that the second bit of both port addresses is zero, that is, both ports attempt to access bank0. In response, the collision detection circuit 222 will stall the operation of the CPU 100 in the next cycle, i.e., cycle 1. The mechanism used by the collision detection circuit 222 to stall the CPU may be implemented using circuitry similar to that used by the standard cache control logic to stall the CPU during a cache miss.

In this example, A0 [2] = A1 [2] = 0. Therefore, bd [0] [0] = 1 and bd [1] [0] = 1, bd [0] [1] = 0, and bd [1] [1] = 0. therefore,

sel [0] [0] = 1 AND NOT (sel_ctrl1)

sel [0] [1] = 0 AND NOT (sel_ctrl1)

sel [1] [0] = (NOT (1) AND 1) OR sel_ctrl1

sel [1] [1] = (NOT (1) AND 0) OR sel_ctrl1

The bank select signals for the respective banks are ORed together by the OR gate 250 having an output supplied to the bank enable signal. If there is no port attempting to access the bank, the bank is not enabled. Here, bank1 will not be accessed. Therefore, the signal sel [1] (i.e., sel [0] [1] and sel [1] [1]) for bank1 has no effect.

However, both ports will attempt to read from bank0. Assume a hit for both port addresses. During cycle 0, since the hit signal hit0 is routed from port0 via hit multiplexer 218 to the hit_bank0 input of bank0, the data word X can be output from port0 during cycle 1.

Then sel_ctrl is asserted during the stall (cycle 1) to force sel0 to select port1 during cycle 1. Thus, during the stall cycle 1, since the hit signal hit1 is routed from port1 via the hit multiplexer 218 to the hit_bank0 input of bank0, the data word Y may be output via port1 during cycle 2, which is the next cycle. Also, during the stall cycle, the result of the read operation on port 0 is latched on the read bus to port 0 by a latch circuit (not shown) on the bus. Thus, data X read from port 0 and data Y from port 1 appear simultaneously during cycle 2. Since the CPU operation is stalled for cycle 1, both port cache accesses to the CPU appear to occur simultaneously in the cycle immediately following cycle 0.

Note that, in the event of a conflict, the conflict resolution circuit 226 approves priority access to port0. Those skilled in the art will appreciate that the conflict resolution circuitry 226 may grant access to the colliding pods with any priority. In the example described herein, a port is numbered such that a lower numbered port corresponds to a port requiring higher priority access, and a higher numbered port can wait for more access.

Also, the collision avoidance circuit is not limited to solving only the collision between the two ports. For a cache with K ports, if the N port tries to access the same bank, access is first provided to the lowest numbered port, and the N- The CPU stalls for one cycle. For example, in the cache having three ports K = 3, the bank selection signals bd [0] [i], bd [1] [i], bd [2] i] exists. there are three port selection signals sel [0] [i], sel [1] [i], sel [2] [i] indicating that ports 0, 1 and 2 address the bank.

There are sel_ctrl1 and sel_ctrl2 as two selection control signals shared by all the banks in order to invalidate the priority of resolving the bank conflict. If sel_ctrl1 is asserted, port1 is selected. If sel_ctrl2 is asserted, port2 is selected. If neither sel_ctrl1 nor sel_ctrl2 is asserted, port0 takes precedence.

For each bank i,

sel [0] [i] = bd [i] AND NOT (sel_ctrl1 OR sel_ctrl2)

sel [1] [i] = (NOT (bd0 [i]) AND bd1 [i]) OR sel_ctrl1

(2) [i] = (NOT (bd0 [i] AND NOT (bd1 [i]) AND bd2 [i]) OR sel_ctrl2

Generally, in the K (K > 3) port,

For each bank i:

For each port j (0 <j <K):

For each bank selection signal bd [j] [i] of port j of bank i:

For each selection control signal sel_ctrl [m] (m = 1, ..., K-1):

The collision avoidance circuit generates the following output selection signal sel [j] [i].

sel [0] [i] = bd [0] [i] AND NOT (sel_ctrl [1] OR sel_ctrl [2] OR ... OR

sel_ctrl [K-1]

1] [i] = (NOT (bd [0] [i]) AND bd [1] [i]) OR sel_ctrl [1]

(2) [i] = (NOT (bd [0] [i] AND NOT bd [1] [i] AND bd [2] [i]) OR sel_ctrl [

sel [j] [i] = NOT (bd [0] [i])

AND NOT (bd [1] [i])

...

AND NOT (bd [j-1] [i])

AND (bd [j] [i])

OR sel_ctrl [j]

It can be seen that for many stall cycles a number of bank conflicts will occur which would impair overall performance. Therefore, it is advantageous to limit the number of bank conflicts within the same CPU cycle. According to one embodiment of the present invention, bank conflicts are prevented in the compiler and application software by assigning variables to instructions that are close to addresses of other banks. Therefore, it is very difficult for the same bank to be addressed in the same cycle. In addition, the configuration of the address space itself helps to reduce the possibility of bank conflict. By using the lower address bits, e.g. the second bit, for the selection of the bank, adjacent words of the cache block are evenly distributed among all the banks. In this way, the address of the adjacent word will result in the address of the other bank. Due to the localization of the reference characteristic, this configuration reduces the possibility of collision.

While the invention has been described in conjunction with specific embodiments, various modifications and changes may be made by those skilled in the art without departing from the spirit and scope of the invention. For example, the cache may consist of 8 banks of 8-way set associative caches. In such a configuration, address bits 6-11 act as a set index. Each set includes two rows of each bank. Bit 5 selects one of the two rows and bit 2-4 selects the bank. Address bits 11-31 are used for tag comparison. Bits 0-1 correspond to bytes in the word. Further, the present invention can be applied to pipeline caches.

Claims (9)

A plurality of memory banks; A plurality of ports capable of accessing the bank; And a collision detection circuit for detecting concurrent addressing of the first memory bank through the first port and the second port and stalling the processor operation for a predetermined time in response to detection of the concurrent addressing. 2. The system of claim 1, further comprising: means for enabling access to the first memory bank through the first port during the stall, and for enabling access to the first memory bank via the second port after the stall is completed Lt; RTI ID = 0.0 &gt; circuitry. &Lt; / RTI &gt; The microprocessor system of claim 1, wherein each bank has a single port. 2. The microprocessor system of claim 1, wherein the bank is addressed such that words in a cache block are distributed among a plurality of banks. 2. The microprocessor system of claim 1, wherein the bank has a non-overlapping address space. The method of any one of claims 1, 3, 4, or 5, further comprising: during a stall of the processor, through a port that attempts to access the first memory bank in an order of increasing priority during a continuous clock cycle, A microprocessor system comprising a conflict resolution circuit that allows access to a bank. A plurality of memory banks; A plurality of ports capable of accessing the bank; And a collision detection circuit for detecting concurrent addressing of the first memory bank through the first port and the second port and outputting a signal for stalling the processor operation for a predetermined time in response to detection of the concurrent addressing. 8. The method of claim 7, further comprising: allowing access to the first memory bank through the first port during the stall, and allowing access to the first memory bank via the second port after the stall is completed Lt; RTI ID = 0.0 &gt; circuitry. &Lt; / RTI &gt; 9. The system of claim 8 including collision avoidance circuitry that allows access to the memory bank through a port that attempts to access the first memory bank in an order of increasing priority during a continuous clock cycle while the processor stalls Multiport memory.