DE19809640A1 - Speed-optimized cache system - Google Patents

Abstract

Several cache memories are used instead of a continuously large cache memory. Each memory has a defined address range. A plurality of arithmetic units can access a plurality of cache memories due to the fact that the cache memory is selected on the basis of defined addresses. If several arithmetic units access the same cache memory, one of the arithmetic units undergoes arbitration per time unit and is granted the right of access. If the data is not available in the cache memory, bursting occurs when accessing the memory, that is, a plurality of data is written on a complete line of cache memories (CL) in the memory or read from the memory.

Description

1. Background of the Invention

Building blocks of the genus DFP (cf. DE 44 16 881 A1, P 196 51 075.9), RAW machines, digital signal processors, DPGA, as next-generation microprocessors also have several internal highly parallel arithmetic units. FPGAs are often called numerical coprocessors and are used with a Large number of arithmetic units working in parallel if possible programmed.

The above modules reach internal Data transfer rates of several gigabytes per second. A A large number of arithmetic units (CELs) require data at the same time from the cache.

1.1 State of the art

State-of-the-art cache systems only allow access from one arithmetic unit or a few arithmetic units per unit of time to. The data rates of the caches are as wide as possible Cache lines reached.

1.2 problems

State-of-the-art cache systems are unsuitable for  fast building blocks of the above-mentioned types, because parallel simultaneous accesses are only possible to a limited extent. By The high cache width is the effort and therefore the connected time delay for disassembling the cache data not insignificant in the requested data. The construction of Cache systems for fast bus systems such as B. is the RAMBUS extremely complicated and technically hardly, or only with considerable effort and costs can be realized because of this considerable transfer rates occur that are particularly fast Storage and controls need.

1.3 Improvement by the invention, task

The object of the invention is a highly parallel Cache system that optimizes a variety of speed allows simultaneous access and the data in the for provides the respective arithmetic units optimal width.

2. Description of the invention 2.1 Overview of the invention, abstract

Instead of having a continuous wide cache, uses multiple cache memories, each of the memories has a unique address space. A majority of Arithmetic units can have a plurality of caches access by caching based on unique Addresses is selected. Take up several arithmetic units the same cache memory, one of the Arithmetic units per clock unit arbitrate and receive the Access rights. If the data is not in the cache memory, is always bursted when the memory is accessed,  d. H. a lot of data is over a complete line written to or from cache memories (CL) read the memory. Especially through this property the construction of a cache system for modern bus systems such as B. the RAMBUS considerably simplified.

2.2 Detailed description of the invention

There are a number of cache memories, each with a unique address space. The address space of the individual CS is based on the low-order address bits A _n . . . A ₀ is determined in such a way that the CS form a linearly connected, uninterrupted address space. The number of cache memories must be 2 ⁿ for n = 0, 1, 2, 3,. . . amount, ie the address bits A _n . . . A ₀ are used to select the respective cache memory. The following table gives an overview of the number of cache memories and the decoding of the address bits. n is any integer (integer, see above); C # indicates the number of caches; ADR CACHE 2 ⁿ gives the binary value of A _n . . . A ₀ for selection of the corresponding cache memory; For larger n the table should be expanded accordingly in width and depth:

2.2.1 Connection to an arithmetic unit

To connect an arithmetic unit (CEL) to the CS, a decoder, the A _n . . . A _{0 is} encoded, the respective addressed CS (A _n × 2 ⁿ +... A ₁ × 2 ¹ + A ₀ × 2⁰) selected. The address, data and control lines of the CS are connected to the arithmetic unit via demultiplexers and multiplexers. Synchronization is also required, which signals to the CEL when the data from the cache has been accepted or is available in the cache.

2.2.2 Connection to the memory

A state machine takes over the management of the memory responded to a cache miss. A cache miss occurs when access to address areas that are not in the cache are located.  

The state machine first writes the new one Cacheline (CL) in memory. A CL are according to the state the technology all data that is on the same horizontal Storage level - i.e. have the same Y address -, like the requested. A CL extends over all of them CS, the exact definition follows in the next paragraph. The The state machine then reads the new data from the memory in the CL. When writing and reading the CL is preferably used Increase the bus speed a bus burst after which State of the art.

Since the CS, as already explained, is always arranged 2 ⁿ times, ib for a CL, the following: any address of the width g is divided into a part B of the width b which corresponds to the size of the cache and a remainder T of the width t = g - b disassembled. Address part B can be broken down into a more significant part M of width m = b-n and a less significant part N of width n, 2 ⁿ corresponding to the number of CS. For any value W, where the address W is in the values Wm = A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ of the address part M and the values Wn = A _m × 2 ^m + A _(m-1) × 2 ^(m-1) +. . . + A _{(n + 1)} × 2 ^{(n + 1)} + A _n × 2 ^{n of} the address part N is broken down (⇒ W = [Wm, Wn]), the following applies for Wn 0 ≦ Wn <2 ⁿ . The data of the address W = [Wm, Wn] are in CS (Wn); the data of the address W = [Wm, 0] are in CS (0); the data of the address W = [Wm, (2 ⁿ -1)] are in CS ((2 ⁿ -1)). In the simplest case, a CL extends over all Wn from 0 to (2 ⁿ -1). A burst begins at Wn = 0 (⇒ W = [Wm, 0]) and ends at Wn = (2 ⁿ -1) (⇒ W = [Wm, (2 ⁿ -1)]).

To perform longer bursts, W can be broken down into 3 address parts Wo, Wp, Wn of lengths o, p, n. Here, m = o + p, n is as usual ⇒ W = [Wo, Wp, Wn]. In this case, a burst runs via the memory words W = [Wo, 0, 0] to W = [Wo, (2 ^p -1), (2 ⁿ -1)], each CS being run through 2 ^p times CL extends over all Wp, Wn.

The part T is in a cache access according to the state of the Technology stored in the so-called TAG-RAM. The content of the TAG RAM (t_tag) is used for access with part T of Access address compared. If t_tag is not equal to T, they are data in question is not in the cache, a so-called cache miss is available. The data must be transferred from memory become. If t_tag is equal to T, the relevant data are in the Cache, a so-called cache hit. The cache hit / miss The method corresponds to the state of the art.

2.2.3 Several arithmetic units

The cache described has several CS, each of which has a unique address and therefore has a unique address space. A large number of arithmetic units can access the CS at the same time, provided that each arithmetic unit has a different address space A _n . . . A ₀ used. In order to circumvent this restriction, each CS is assigned a worker who, if several arithmetic units on the same address space A _n . . . Access A ₀ , one of the arithmetic units arbitrates per time unit. For this purpose, the buses of all arithmetic units are switched to a multiplexer / demultiplexer.

Each bus delivers one from A _n . . . A ₀ coded signal that selects exactly one of the CS. One of the buses is selected for access to the respective CS via the worker assigned to a CS. In the case of individual arithmetic units, the synchronization of the CEL with the CS must be generated individually by CS for each arithmetic unit in order to additionally indicate whether the respective arithmetic unit is the currently arbitrated.

2.2.4 Connection to fast bus systems according to the state of the technology

Fast bus systems (e.g. state-of-the-art RAMBUS) exchange the memory data via a large number of registers or ports (BR) into which the data is sequentially sorted in a kind Interleaving to lower the clock frequencies can be written (see RAMBUS-RAC). There is basically no cache between the BR and the CEL.

Because of the better data throughput, a method for caching data that is transmitted using such fast bus systems is described:
A CS is assigned to one or a set of registers, ie each BR or group of BRs is cached by a CS. Due to the uniqueness of the addresses A _n . . . A ₀ for each CS this assignment is possible, provided that the registers also clearly have the same A _n . . . A _{0 are} assigned. This is basically the case if a burst, as stated several times, always at A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 0 begins and always at A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 2n-1 ends.

The number of BR must be 2 ^r for r = 0, 1, 2, 3,. . . amount, which is usually the case. The ratio of CS to BR is 2 ^v = 2 ⁿ : 2 ^r .

• - If v = 0, 2 ^v = 1, a BR is assigned to each CS.
• - There are more BR than CS (v <0, 2 ^v <1):
  Basically, 2 ^-v cachelines are transferred for each read or write access. The address of the respective BR A _r . . . A ₀ = A _v . . . A _{n + 1} . . . A _n . . . A ₀ .
• - There are more CS than BR (v <0, 2 ^v <1):
  In order to transmit a read or write cache line, 2v accesses to the bus system take place. The address of the CS A _n . . . A ₀ = A _v . . . A _{r + i} . . . A _r . . . A ₀ .

3. Brief description of the diagrams

Fig. 1a, b shows the arrangement of caches

Fig. 2a shows a cache according to the prior art

FIG. 2b shows a cache according to the invention

Fig. 3 shows a cache according to the invention with simultaneous, arbitrated access possibility by several arithmetic units

Fig. 4 shows the internal structure of a cache

Fig. 5 illustrates the connection of a cache memory according to the invention to the

Fig. 6 shows the flow of the State Machine in the cache

Fig. 7 shows the connection of the cache system of the invention to a fast bus system using the example of a RAMBUS controller (RAC)

Fig. 8 shows the construction of a multiplexer / demultiplexer structure

3.1 Detailed description of the diagrams

A plurality (2 ⁿ ) of cache memories ( 0101 ) is shown in FIG. 1a. The addresses A _n . . . A ₀ are used to select one of the 2 ⁿ cache memories. A cacheline (CL) ranges from A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 0 to A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 2 ⁿ -1. The cache is 2 ^m entries deep, ie it ranges from A _{n + m} . . . A _{n + 1} . The area A _{n + m + t} . . . A _{n + m + 1} is entered in the TAG-RAM ( 0102 ) assigned to the cache memory.

The burst extends over a CL of

to

A plurality (2 ⁿ ) of cache memories ( 0101 ) is shown in FIG. 1b. The addresses A _n . . . A ₀ are used to select one of the 2 ⁿ cache memories. A cache line (CL) extends over several cache lines of A _n × 2 ⁿ +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 0 to A _{(n + p)} × 2 ^{(n + p)} +. . . + A ₁ × 2 ¹ + A ₀ × 2⁰ = 2 ^{n + p} -1. The cache is 2 ^m entries deep, ie it ranges from A _{n + m} . . . A _{n + 1} . A _{n + m} applies. . . A _{n + 1} = A _{n + m} . . . A _{n + p} . . . A _{n + 1} . The area A _{n + m + t} . . . A _{n + m + 1} is entered in the TAG-RAM ( 0102 ) assigned to the cache memory.

The burst extends over a CL of

to

A single cache ( 0201 ) according to the prior art is shown in FIG. 2a. The data width to the connected arithmetic unit can be many times larger (b ») than the data width of the memory connection ( 0202 ).

FIG. 2b shows a cache memory according to the invention, which consists of several individual memories (0203). Through the addresses A _n coming from the arithmetic units. . . A ₀ ( 0204 ) one of the cache memories is selected for access by the arithmetic unit ( 0211 ) via a multiplexer / demultiplexer ( 0205 ). A state machine (0206) described in more detail in Fig. 5 and Fig. 6 controls the access and the burst of the cache lines in the memory (0210). To do this, it selects one of the 0203 using the multiplexer / demultiplexer ( 0207 ) based on the addresses ( 0208 ) generated by 0206 during a burst. The address of the cache line (depending on the implementation A _{n + m} ... A _{n + 1} or A _{n + m} ... A _{n + p} ... A _{n + 1} ) is fed to 0203 via 0209 .

Fig. 2c shows the internal construction of a cache according to the state of the art (see. Fig. 2a). Several data words ( 0213 ) are combined in the memory ( 0212 ) in the horizontal direction, to which only common access is possible. A cacheline (CL) comprises several data words with the same Y address.

Fig. 3 shows a possible embodiment of the connection of the CS to several CELs. Each CS ( 0304 ) is assigned a multiplexer / demultiplexer ( 0301 ) to which the bus ( 0302 ) of each arithmetic unit is fed. The address lines are A _n . . . A _{0 is} encoded ( 0303 ) and serves as an access request to the respective CS arranged for the encoding. A worker ( 0305 ), preferably an SCRR-ARB (see PACT10) selects one of the access requests and controls 0301 accordingly.

Fig. 4 shows a possible structure of a 0304th The lines routed upwards in the drawing are used to connect the memory, the lines routed downwards are used for connection to the calculator (s) (CEL). The addresses A _{n + m} arrive via a multiplexer ( 0407 ). . . A _{n + 1} as CA _{n + m} . . . CA _{n + 1} ( 0404 ) to the address input of TAG-RAM 0401 . When accessed by the state machine ( 0206 ), the TAG-RAM stores the addresses A _{n + m + t} . . . A _{n + m + 1} . If the CEL accesses the cache, the addresses stored in 0401 are compared with the addresses requested by CEL using 0402 . If the addresses are "equal", the data are in the cache RAM ( 0403 ), which means a cache hit, otherwise the data are not in the cache RAM, correspondingly "unequal" means a cache miss is signaled.

0404 is routed to 0403 as an address input . The data is output for read accesses via the demultiplexer / multiplexer 0405 , or for write accesses via the multiplexer / demultiplexer 0405 .

The 1-bit memory 0406 is used to record whether the CEL changed the data at a specific address. If the CEL has write access to the data, "Dirty" in 0406 is written to the address ( 0404 ). With read access, 0406 remains unchanged. With write access to the data by the state machine 0206 , "clean" is written to the relevant address. On the basis of "dirty" and "clean", 0206 recognizes whether the celeline has been changed by the CEL ("dirty") and has to be written back into memory, or whether the unchanged cacheline can simply be overwritten. The sequence of the state machine 0206 is shown in FIG. 6.

The comparator 0409 determines whether the state machine 0206 accesses the same addresses (Same_Adr) as the CEL. This means that the 0206 changes the data to 0403 while the CEL requests access to precisely this data - or vice versa. Since either the CEL or 0206 is accessing the data at one point in time, there is no consistency problem. However, considerable speed is lost when data are required by the CEL are overwritten first of 0206 with other data to be rewritten for a fact inevitably resulting cache miss again from 0206 to become. If there is a cache hit AND ( 0410 ) a Same_Adr, 0206 is signaled (FreeReq) that the overwriting of the data in 0403 should be delayed until the CEL has read or written the data. For a better understanding, reference is made to FIG. 6.

A cache miss is forwarded to 0206 and causes the corresponding data to be loaded.

The CEL must be shown when access from the cache system was accepted. This can be done by a simple synchronization Acknowledgment signal to be sent to the CEL. E.g. can one Cache hit according to P 197 04 728-9 an ACK handshake signal generate to indicate that the current access is accepting has been.

The multiplexers 0407 , 0405 , 0408 are controlled by 0206 via a "LOCK" signal in such a way that either the CEL have access to the cache or 0206 accesses the cache.

In FIG. 5, the cache miss, signals (0504) to a worker (0501), preferably a SCRR-ARB according PACT10. The worker ( 0501 ) selects one of the cache memories sending a cache miss per time unit and switches its bus ( 0505 ) via the multiplexer / demultiplexer 0502 to the memory bus ( 0503 ). The valid signal of the worker ( 0506 , cf. prior art), which indicates that a cache memory signal has been selected for processing due to the occurrence of a cache miss signal, is sent to the state machine 0206 . The dirty signals ( 0508 ) of all CS are ORed ( 0509 ) and 0206 . The FreeReq signals ( 0510 ) of all CS are also ORed ( 0511 ) and 0206 .

Via 0512 (FreeAck), 0206 indicates to the CS that the pending FreeReq has been accepted and that the CS still have one clock cycle time to carry out the pending accesses. Via 0513 (Lock), 0206 indicates to the CS that it is taking control of the CS in order to change a CL. 0513 switches the multiplexers 0407 , 0405 , 0408 so that 0206 receives control.

0514 is the write-enable signal, which writes the data read from the memory to the CS and sets 0406 to "clean".

Depending on the connected RAM system (e.g. RAMBUS), the control signals are sent to the memory via bus 0507 .

Fig. 6 shows the sequence within the State Machine 0206th The basic state is IDLE. When a VALID signal ( 0506 ) occurs, the state machine generates the LOCK signal. LOCK remains set during all states, except for IDLE! If a FreeReq signal occurs immediately after "LOCK" has been set, the state machine jumps to the WAIT state and generates the FreeAck signal for one clock cycle in order to allow the CEL one last access to the CS; FreeAck has a higher priority in CS than LOCK.

Regardless of whether the state machine receives no FreeReq in the IDLE state or leaves the WAIT state, the following happens:

• a) A DIRTY signal is present. Ie the data in the current cache line has been changed. The state machine writes the basic address of the burst
  on the bus ( 0503 , 0507 ) and writes the data from the CL into the memory until the end of the cache line has been reached:
  Then the state machine jumps to point b)
• b) there is no DIRTY signal; or 0206 jumps from point a). Ie the data in the current cache line have not been changed. The state machine writes the basic address of the burst
  on the bus ( 0503 , 0507 ) and reads the data from the CL into the cache until the end of the cache line has been reached:
  The state machine then jumps to the IDLE state.

In Fig. 7 is as an implementation example, the compound of the cache structure of the invention with the RAMBUS system. Two 8-bit registers ( 0701 ) of the RAC ( 0702 ) are combined to form a 16-bit register (see state of the art / RAMBUS). The 8 8-bit registers of the RAC are therefore assigned to 4 16-bit CS ( 0703 ). The contents of the 8 registers can be written into the cache system of the 4 CS in one cycle, or in a plurality of cycles, with at least 2 0701 being transferred in one cycle. The following calculation using the example of the ConcurrentRDRAM data shows the technical advantage of the present invention, in terms of reducing the speed requirements for the cache memory: The ConcurrentRDRAM RAMBUS system offers a data transfer rate to the memory ( 0705 ) of a maximum of 633MB / s, ie each the 8 0701 (8-bit) is written with approx. 80 MHz. A moderate frequency of 40 MHz is sufficient for the transmission of the data (16-bit) from the 0701 to the 0703 , which enables the use of standard cache memories according to the prior art. The state machine 0704 controls the 0703 and 0702 , as already stated several times.

Figure 8 shows the implementation of a multiplexer / de multiplexer structure as used multiple times. A first group of buses ( 0801 ) is transmitted to a second group of buses ( 0803 ) via multiplexers ( 0802 ). The second group of buses is in turn transmitted to the first group of buses via the multiplexers 0804 . From the point of view of group 0801 , 0802 are the multiplexers and 0804 are the demultiplexers.

Claims (5)

1. cache system for the temporary storage of data and code for modules with two- or multi-dimensional arithmetic unit structure, including DFPs, RAW machines, FPGAs and DPGAs, as well as microprocessors and signal processors, characterized in that

• a) the cache system consists of a plurality of individual cache memories,
• b) all caches together result in a linear, uninterrupted address space over the low-order addresses.

2. Cache system according to claim 1, characterized in that to each cache memory individually and independently of one Calculator can be accessed. 3. Cache system according to claim 1-2, characterized in that to access multiple calculators on one and the same cache memory cher led several bus systems to the cache memory are, of which one each via a multiplexer with the Cache is connected. 4. Cache system according to claims 1-3, characterized in that when multiple arithmetic units access one and the same Cache memory one arithmetic unit per unit of time arbitrated and assigned.   5. Cache system according to claims 1-4, characterized in that one register each for connecting a fast bus system or port or a group of registers or ports one or is assigned to a group of cache memories, one fixed assignment of the addresses to the ports / registers and the Cache exists.