KR19990071031A - Memory switching device and control method for updating program memory - Google Patents

Abstract

The present invention relates to a microcomputer 80C517 MICOM, a CPU 10 for controlling the entire system, an internal program memory 20 installed in the CPU 10 and storing a program, and the CPU An external program memory 30 connected to the outside of the CPU 10 to receive a control signal output from the CPU 10 and to read a program stored therein, and to the external program memory 30. If you want to update the stored program (Up date) to the program memory control unit 40 to control the EA PIN of the CPU 10 to a high signal to store the updated program in the external program memory (30) By applying a high signal to the EA PIN of the CPU, especially when the CPU does not have an extra output port, by selecting the internal program memory inside the CPU, Jean invention is capable of emulation (Emulation) at a low cost when you update or modify the program in the process of developing an electronic system.

Description

Memory switching device and control method for updating program memory

The present invention relates to 80C517 MICOM, in particular, when the program data (Up date) in the engine electronic control system using the Siemens MICOM (Central Processing Unit) CPU (Central processing unit) program The present invention relates to a memory switching device and a control method for updating a program memory that can update the contents of a flash memory even while using the memory.

Conventionally, when a program is stored in a masked memory and used, and the program contents are to be changed during use, a new program is stored in another memory and used again. Therefore, when the program is changed during use, additional memory is used. Not only does it cost additional memory, but it also has the inconvenience of rewriting the program separately whenever the program changes.

An object of the present invention for solving the above problems, by controlling the EA PIN properly while the CPU is operating, switching the program memory to the data memory and then saving the program after the original program memory again if you want to update The present invention provides a memory switching device and a control method for updating a program memory that can easily update a changed program.

The memory switching device for updating the program memory of the present invention for achieving the above object includes a CPU for controlling the entire system, an internal program memory installed in the CPU and stored therein, An external program memory which is connected to an external device and receives a control signal output from the CPU to read a program stored therein, and an update program for updating the program stored in the external program memory. And a program memory controller for outputting a high signal to the EA PIN of the CPU to store the updated program in the external program memory.

The memory switching control method for updating the program memory of the present invention for achieving the above object, if you want to change the contents of the program stored in the external program memory, first the program stored in the external program memory The first step (S1) for requesting the change of the second and the first step (S1) in accordance with the program change request, the output terminal (Q) of the second flip-flop outputs a high signal to the EA PIN terminal of the CPU In the second step S2 and the CPU to which the high signal is applied in the second step S2, by selecting an internal program memory, the third step S3 is updated to new program data, and the third step ( In step S3), after newly updating the program stored in the external program memory, it is determined whether the changed program has been verified. If it is determined that the program stored in the external program memory is normally updated in the fourth step S4 and the fourth step S4, a low signal is output to the EA PIN at the output terminal of the second flip-flop. The CPU 10 selects an external memory by receiving the low signal of the EA PIN output in the fifth step S5 and the fifth step S5, so that the program stored in the external program memory is returned to normal. Toggle the error function indicator lamp when it is not changed normally by determining whether the program is normally changed in the sixth step (S6) and the fourth step (S4). Toggle a seventh step (S7) characterized in that consisting of.

1 is a block diagram schematically showing a memory switching device for updating a program memory of the present invention;

2 is a circuit diagram specifically illustrating a program memory controller of the present invention;

3 is a timing chart for a memory switching device for updating a program memory,

4 is a flowchart illustrating a memory switching control method for updating a program memory.

Explanation of symbols for main parts of the drawings

10: CPU 20: internal program memory

30: external program memory 40: program memory control unit

401, 403: NAND gate 405, 407: OA gate

409: first flip-flop 410: sickle gate

411: second flip-flop

A memory switching device and a control method for updating the program memory of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2, the CPU 10 of the Siemens 80C517 series that controls the entire system, and an internal program memory installed in the CPU 10 to store a program (Program) ( 20), an external program memory 30 connected to the outside of the CPU 10 to receive a control signal output from the CPU 10 and to read a program stored therein, and the external If you want to update the program stored in the program memory (30) (High date) to increase the EA PIN of the CPU 10 to store an externally stored updated program in the external program memory (30) It consists of the program memory control part 40 which controls by a signal.

As illustrated in FIG. 2, the program memory controller 40 receives an address signal A8-A11 output from the CPU 10 and outputs a low signal when all of the input signals are high. A NAND gate 401 that receives the NAND gate 403 and the address signals A12-A15 output from the CPU 10 and logically multiplies them and outputs a low signal when the input signals are all high. An OR gate 405 for receiving a signal output from the NAND gate 401 and the NAND gate 403 and performing a logical OR to output a high signal if any one of the input signals is high; An OR gate 407 for receiving the signal output from the 405 and the write signal WR output from the CPU and ORing the signals, and the signal output from the OR gate 407 are inputted from the clock terminal CLK. A first flip flop 409 which latches an input signal at an output terminal Q and outputs an output signal A by inputting data output from the CPU to the data input terminal D. And a NOT gate 410 for inverting and outputting a reset signal output from the CPU, and a reset signal inverted at the sick gate 410 is input to a clock terminal. The external program memory 30 receives an output signal A output from the output terminal of the flop 409 from the input terminal D, and outputs a high signal from the output terminal Q to the EA PIN of the CPU. It consists of a second flip-flop 411 for updating the program stored in.

That is, when updating a program of the external program memory 30 connected to the CPU 10, the external program memory 30 is applied by applying a reset signal output from the CPU 10. Can be operated in program mode.

The operation and effects of the present invention configured as described above will be described with reference to FIGS. 1 to 4.

When the user normally uses the program and the program is changed or upgraded due to various reasons and wants to change the program content stored in the external program memory 30, the user first stores the program in the external program memory 30. A first step S1 for requesting a change of a program, and a request for program change in the first step S1, a NAND gate (A8-A11) outputting an address signal A8-A11 output from the CPU 10. In operation 403, the result is logically multiplied and output, and the address signals A12-A15 output from the CPU 10 are received by the NAND gate 401 and output by AND.

The OR gate 405 receives and outputs the signals output from the NAND gate 401 and the NAND gate 403.

As described above, the OR signal received from the OR gate 405 and the write signal WR output from the CPU 10 are inputted from the OR gate 407, and then ORed, and then the first flip flop 409 is connected to the OR signal. The first flip flop 409 is output to the clock terminal CLK and the data signal DO output from the CPU 10 is input to the input terminal D of the first flip flop 409. In the output terminal Q, the same signal as in (d) shown in FIG.

When the output signal A is output from the output terminal Q of the first flip flop 409, the output signal A is input to the input terminal D of the second flip flop 411. When the reset signal RO output from the CPU 10, that is, the signal as shown in FIG. 3E is input to the clock terminal CLK, the output terminal Q of the second flip-flop 411 is input. ) In the second step (S2) and the high signal output in the second step (S2) as shown in Figure 3 (bar) is input to the EA PIN of the CPU 10, the CPU In (10), the internal program memory 20 inside the CPU 10 is selected.

As described above, when the internal program memory 20 is selected by the CPU 10, the external program memory 30 is written as a data memory, thereby updating with new program data. After updating the program stored in the external program memory 30 in the third step S3, the program writes 0 to the address FFXX and applies a reset signal. If it is determined that the program stored in the external program memory 30 is normally updated in the fourth step S4 for determining whether or not to verify, and the fourth step S4, the bar in FIG. As shown in FIG. 5, the fifth step S5 in which the signal of the EA PIN output from the output terminal of the second flip-flop 411 is output low, and the EA PIN output in the fifth step S5. Of The CPU 10 selects an external memory by receiving the right signal, so that the program stored in the external program memory 30 becomes a normal main program again to operate in a normal state before changing a program. Step S6 and the seventh step S7 of toggling the error function display lamp when the program is normally changed in the fourth step S4 and is not normally changed.

The memory switching device and the control method for updating the program memory of the present invention configured as described above, in particular when the user changes or updates the program stored in the external program memory, in particular an extra output port (port) to the CPU In the case of no), a high signal is applied to the EA PIN of the CPU to select an internal program memory inside the CPU, thereby emulating at a low cost when the program is modified or updated in the process of developing an engine electronic system. It is an invention that can emulate.

Claims (3)

A CPU that controls the entire system, an internal program memory installed inside the CPU and storing the program, and a control signal output from the CPU connected to the outside of the CPU to receive a program stored therein and outputs a high signal to the EA PIN of the CPU to store the updated program in the external program memory when an external program memory to read and a program stored in the external program memory are to be updated. A memory switching device for updating a program memory, characterized in that consisting of a program memory control unit. The NAND gate according to claim 1, wherein the program memory controller receives the address signals A8-A11 output from the CPU and logically multiplies them and outputs a low signal when all of the input signals are high; Receives and logically combines the NAND gate outputting as a low signal when the input signals A12 to A15 output from the CPU are logically multiplied and output as a low signal, and the signals output from the NAND gate and the NAND gate are input. An OR gate outputting high when any one of the signals is high, an OR gate receiving the signal output from the OR gate and the write signal WR output from the CPU, and ORing the signals together; The signal output from the OR gate is input from the clock terminal CLK, and the data output from the CPU is input to the data input terminal ( D) by latching the input signal at the output terminal Q and inverting the first flip flop for outputting the output signal A and the reset signal output from the CPU. A NOT gate to be output and a reset signal inverted by the sick gate are input to a clock terminal, and an output signal A output from an output terminal of the first flip flop is input to an input terminal D. And a second flip-flop for updating a program stored in the external program memory by outputting a high signal from the output terminal Q to the EA PIN of the CPU. Memory switching device. In the case where it is desired to change the program contents stored in the external program memory, a first step S1 for requesting a change of a program stored in the external program memory and a program change request in the first step S1 are performed. Accordingly, in the output terminal Q of the second flip-flop, the second step S2 of outputting a high signal to the EA PIN terminal of the CPU and the CPU receiving the high signal in the second step S2 are internal. By selecting the program memory, after updating the program stored in the external program memory in the third step (S3) and the third step (S3) to update the new program data, the changed program is changed to Verify ( The fourth step (S4) of determining whether to verify) and the program stored in the external program memory in the fourth step (S4) is normally updated. If it is determined that the drive signal has been turned on, a low signal is output from the output terminal of the second flip-flop to the EA PIN in step S5 and the low signal of the EA PIN output in the fifth step S5 is received. In step 10), by selecting an external memory, a program stored in the external program memory becomes a normal main program again to operate in a normal state before changing a program (S6) and the fourth step ( In step S4), if it is determined that the program is normally changed, and if it is not normally changed, the memory switching control method for updating the program memory, comprising the seventh step S7 of toggling the error function display lamp. .