KR19990070522A - DRAM and system including the same - Google Patents

Abstract

The semiconductor memory device disclosed herein includes a memory cell array including a plurality of memory cells arranged in a matrix form of a plurality of rows and columns; A refresh address generating circuit for generating a refresh address; A row selection circuit that selects an external row address during a write mode and controls the rows by selecting the refresh address during a refresh mode; And a refresh flag generation circuit for storing a flag indicating the presence or absence of write information during the write mode, and for generating the flag signal for controlling the output of the refresh address during the refresh mode.

Description

DRAM and SYSTEM WITH THE SAME

The present invention relates to a system, and more particularly, to a dynamic random access memory (DRAM) capable of reducing power consumption in a refresh mode and a system including the same.

Although DRAM is not shown, as is well known, DRAM is widely used as a semiconductor memory device suitable for increasing the integration density in a semiconductor substrate because one memory cell of the DRAM is composed of one selection transistor and one data storage capacitor. have. However, in the DRAM, since charge leaks through the storage capacitor and the select transistors, it is necessary to periodically perform a refresh to charge the DRAM cells. Thus, as shown in FIG. 1, DRAMs, unlike SRAMs and nonvolatile semiconductor memories, control the data signals stored in memory cells to be periodically amplified by the sense amplifier circuit so that they can be rewritten to the memory cells. Further refresh circuits are provided.

Such refresh consumes the same power as that consumed during the read and write operations of the DRAM. Although power consumption is unavoidable in the read and write operations of the memory device, unnecessary power is wasted because refresh is performed even in a row in which data is not stored in the refresh mode. And since unnecessary refreshes are performed, the amount of time the system can be used is reduced.

Accordingly, it is an object of the present invention to provide a system that can reduce the amount of power consumed during the refresh mode.

1 is a block diagram showing the configuration of a system:

2 is a flowchart sequentially showing a refresh operation:

3 is a block diagram illustrating a configuration of a semiconductor memory device for a CBR refresh mode:

4 is a block diagram showing the configuration of a system for the ROR mode:

* Explanation of symbols on main parts of the drawings

10: memory cell array 20, 130: refresh address generation circuit

40: control block 30, 140: refresh flag generating circuit

50: row select circuit 150: refresh address buffer

(Configuration)

According to one aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix form of a plurality of word lines and bit lines; A refresh address generating circuit for generating a refresh address; A word line selection circuit for controlling the word lines by selecting an external row address during a write mode and by selecting the refresh address during a refresh mode; And a refresh flag generation circuit for storing a flag indicating presence or absence of write information during the write mode and generating the flag signal for controlling the output of the refresh address during the refresh mode.

In a preferred embodiment of the present invention, the refresh mode is CBR ( before ) Refresh mode.

According to another aspect of the present invention, there is provided a system including a DRAM device, comprising: a refresh address generating circuit for generating a refresh address; A refresh flag generation circuit for storing a flag indicating presence or absence of write information during the write mode, and generating the flag for controlling the output of the refresh address during the refresh mode; And a refresh address buffer configured to output the refresh address to the DRAM in response to the flag signal.

In a preferred embodiment of the present invention, the refresh mode is ROR ( only refresh) mode.

By such an apparatus, refresh is not performed only for word lines for which data is not stored during the refresh mode.

(Example)

There are several well-known methods that are widely used to refresh DRAM cells. The following briefly describes the main refresh methods.

First, CBR, that is, cas nonporeless before There is a release method. When memory cells are accessed during normal operations, they are typically applied externally. Signals are also externally applied Activated prior to signals. However, in the CBR refresh method Signal It is activated before the signal. In other words, Before the signal is activated to a low level. The signal is first activated low.

In addition, most DRAMs currently provide a self refresh mode (or a hidden refresh mode) to reduce the amount of current consumed in the refresh operation as much as possible. The self refresh mode starts after a predetermined time has passed after entering the CBR refresh mode. Wow While the signals remain active for a certain time, a self refresh operation is performed in which data stored in all memory cells is read, amplified and stored again in a given refresh period. During this operation, normal operations (e.g., read and write operations) are interrupted. That is, bus masters such as CPUs and DMA controllers in the system must be idle because the bus and memory are unavailable.

1 is a block diagram showing the configuration of a system, in which the system is a central processing unit 102, a ROM 106, a peripheral interface 108, and a power supply source connected to an interface bus 114. 120, RAM 100, and RAM control block 200.

2 is a flowchart illustrating a sequence of refresh operations according to the present invention. The refresh operation for the CBR mode will be described in detail with reference to FIGS. 2 and 3 as follows.

CBR refresh mode

3 is a block diagram showing a configuration of a DRAM for the CBR refresh mode.

The DRAM includes a refresh flag generation circuit 30 having registers corresponding one-to-one with word lines. The refresh flag generation circuit 30 stores an address for a word line connected to memory cells in which data is stored during a write operation, and compares it with the refresh address to output a flag signal indicating whether or not the refresh operation is performed. This allows the refresh to be performed selectively, thereby preventing unnecessary waste of power.

Referring to FIG. 3, the semiconductor memory device for the CBR refresh mode includes a memory cell array 10, a refresh address generation circuit 20 for generating a refresh address, and a refresh flag generation circuit 30 for storing a flag indicating presence or absence of write information. ) Select a word line by selectively accepting the control block 40 for controlling the operation of the peripheral circuits of the memory cell array 10 and the external row address A0-Am-1 and the refresh address RFA. A word line selection circuit 50 for driving.

The refresh address generation circuit 20 includes a refresh timer circuit 21 for generating timing signals for performing periodic refresh and a refresh control circuit 22 for controlling operations related to refreshing a memory device according to the timing signals. ) And a refresh counter 23 for generating an internal refresh address by the refresh control circuit 22.

The word line selection circuit 50-i accepts an m-bit external row address A0-Am-1 during the write mode and selectively receives one of the refresh addresses RFA during the refresh mode. And a row decoder 50-2 receiving the output of the row address buffer 50-1 and selecting at least one of the plurality of word lines. Although not shown, the refresh flag generation circuit 30 includes a register array including registers corresponding to word lines one-to-one. In addition, the control block 40 performs a function of notifying that the write mode and the refresh mode.

First, it is determined whether it is in the write mode (S10), and in the write mode, the control block 40 controls a signal for controlling the row address buffer 50-1 to receive the external row addresses A0 to Am-1. Output The row decoder 50-2 selects a word line corresponding to the external row addresses A0 to Am-1, writes data into cells, and simultaneously stores a flag indicating that data has been written to the refresh flag generation circuit 30. (S15). Then, it is determined whether all data is written to the corresponding memory cells (S20), and when the write operation is completed, the control block 40 signals , It is determined whether or not to enter the refresh mode by receiving (S25). If it is not entered into the refresh mode after the write operation, it waits until the refresh mode is entered. When entering the refresh mode, the control block 40 transmits a signal indicating that the refresh mode to the refresh address generation circuit 20 to generate a refresh address (S30). The refresh address is transmitted to the refresh flag generation circuit 30 to determine whether the flag is set in a register corresponding thereto (S35). If a flag indicating the presence or absence of write information is stored in a register corresponding to the refresh address, a flag signal for controlling the output of the refresh address is transmitted to the word line selection circuit 50-i. For example, if a flag indicating that no data is stored in the register corresponding to the refresh address is stored, the refresh flag generation circuit 30 prevents the refresh address from being output from the word line selection circuit 50-1. . However, the refresh address also occurs at this time.

On the contrary, if a flag indicating that data is stored in the register corresponding to the refresh address is stored, the word line selection circuit 50-i accepts the refresh address in response to the flag signal. Therefore, the word line corresponding to the refresh address is selected to perform the refresh operation (S40). Then, it is determined whether all of the refreshes are performed on the word lines in which at least one data is stored (S45). Refresh is performed on word lines that are not made.

The self refresh mode also prevents the refresh operation from being performed only on word lines in which data is not stored as in the CBR mode described above. Since the configuration is also the same as that of FIG. 3, a detailed description of the self refresh mode will be omitted.

By configuring the DRAM as described above, only the word line in which data is stored may be selectively refreshed to reduce power consumption and to extend the battery life of the notebook.

Next, let's only refresh (the only Refresh), or ROR method while the column address strobe signal remains at the precharge level, The refresh is performed on the cells by activating only a row address strobe signal. In this ROR method, external refresh addresses must be provided to the memory device for each refresh operation, and address buffers connected with the memory device cannot be used for other purposes during each refresh operation. The system for the ROR mode with novelty according to the present invention will now be described in detail.

ROR refresh mode

4 is a block diagram showing the configuration of a RAM control block in the system for the ROR refresh mode.

The RAM control block 200 for the ROR mode includes a refresh flag circuit 140 having registers for storing information about word lines. The refresh flag generation circuit 140 outputs a flag signal that controls the output of the refresh address when data is not stored in the cells connected to the word line of the DRAM. That is, the word line connected to the cells in which data is not stored is deselected during the refresh mode, and refreshing is not performed.

Referring to FIG. 4, the RAM control block for the ROR refresh mode includes a refresh timer 110, a control block 120, a refresh address generating circuit 130, a refresh flag circuit 140, and a refresh address buffer 150. do. The refresh timer 110 generates timing signals (pulse signals) for performing periodic refresh. The control block 120 is a signal (CPU HRQ) requesting to stop using the bus of the CPU during the refresh mode, and a memory read signal used to generate the RAS signal during the refresh mode according to the timing signals. ), A signal indicating that a refresh is being performed (BREFRESH, In addition to the counter enable signal E_C and the clock signal CLK_C that enable the operation of the refresh address generation circuit 130, signals for controlling operations related to refresh are generated. The refresh address generation circuit 130 generates a refresh address outside the memory device. The refresh flag generation circuit 140 stores a flag indicating the presence or absence of write information in the write mode, and outputs a flag signal for controlling the output of the refresh address during the refresh mode. The refresh address buffer 150 supplies the refresh address into the DRAM in response to the flag signal.

The refresh operation of the system including the DRAM device will be described in detail with reference to FIGS. 2 and 4 as follows.

First, it is determined whether it is in the write mode (S10). In the case of the write mode, data is written by inputting an external row address to the memory device although not shown. At the same time, a flag indicating whether data has been written to the memory device is stored in the refresh flag generation circuit 140 outside the memory device (S15). When it is determined that the write operation is completed in the memory device (S20), it is determined whether or not the refresh mode has been entered (S25). When entering the refresh mode, a refresh address is generated from the refresh address generation circuit 130 (S30). The refresh address is transmitted to the refresh flag generation circuit 140, and a flag signal corresponding to the presence or absence of write information is output to a register corresponding to the refresh address. If a flag indicating that data has been written to the register corresponding to the refresh address is stored, the refresh address buffer outputs a flag signal that enables the refresh address to be output. When it is determined whether the flag corresponding to the refresh address is set as described above (S35), the refresh address buffer 150 transfers the refresh address to the word line selection circuit of the memory device so that the word line is selected to perform the refresh ( S40). Subsequently, if it is determined that the refresh operation is completed only for the word lines in the memory device, the refresh operation is terminated. If the refresh is not completed, a refresh address is generated and the corresponding word line is refreshed. As the refresh is selectively controlled outside the semiconductor memory device, the refresh is performed only for the word line in which data is stored, as in the CBR mode of FIG. 3.

Unless refresh is performed on word lines that do not store data, the system's CPU, DMA controllers, bus masters, buses, and memories can be accessed more often, improving system performance.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, it is possible to selectively refresh only the word lines corresponding to the cells in which data is stored according to the refresh mode. As a result, power consumption of the system and the semiconductor memory device can be further reduced.

Claims (3)

A memory cell array including a plurality of memory cells arranged in a matrix form of a plurality of rows and columns; A refresh address generating circuit for generating a refresh address; A row selection circuit that selects an external row address during a write mode and controls the rows by selecting the refresh address during a refresh mode; And a refresh flag generating circuit for storing a flag indicating the presence or absence of write information during the write mode, and generating the flag signal for controlling the output of the refresh address during the refresh mode. The method of claim 1, During the refresh mode, the row select circuit is inactivated in response to the flag signal. In a system comprising a DRAM device, A refresh address generating circuit for generating a refresh address; A release flag generating circuit for storing a flag indicating presence or absence of write information during the write mode, and generating the flag for controlling the output of the refresh address during the refresh mode; And a refresh address buffer outputting the refresh address to the DRAM in response to the flag signal.