KR19990069634A - Asynchronous Transfer Mode Centralization Device Using Cell Bus and Bus Clock Calculation Method in the Device - Google Patents

Abstract

The present invention requires a small capacity switching board to implement an ATM subscriber of a small Asynchronous Transfer Mode (ATM) concentrator, but requires a separate switching board by cell switching using a cell bus structure (ThroughPut), and a method for calculating a bus clock in the device.

When implementing small ATM convergence devices, it is important to be able to accommodate a large number of subscribers and various traffic to a self with low cost and high integration of the number of subscribers. At this time, when a small self-contained (19-inch rack) redundant small-sized switching module is inserted, the number of subscribers is reduced and the material cost per pod increases. In addition, conventionally, a separate switching board is required to transmit data to each destination by switching and routing data to be transmitted by each subscriber or to transmit data received by the edge switch to each subscriber. In this case, since the switching board must be mounted on the centralizing apparatus, the number of subscribers to be accommodated in the limited apparatus becomes small if the material cost and the subscriber mounting slot of the apparatus become large.

A preferred embodiment of the ATM concentrator using the cell bus without the ATM switching module according to the present invention is a cell bus for interconnecting all the subscribers to transmit cell data, a timing master for controlling timing when connecting to the bus, An arbiter block, an ATM subscriber block for transferring or switching data of an ATM subscriber on a bus, an uplink module for supplying a clock on the bus, transmitting cell data to an ATM edge exchanger, and a frame relay module And a frame relay subscriber block that includes a transmitting and a switching.

Description

Asynchronous Transfer Mode Centralization Device Using Cell Bus and Bus Clock Calculation Method in the Device

The present invention requires a small capacity switching board to implement an ATM subscriber of a small Asynchronous Transfer Mode (ATM) concentrator, but requires a separate switching board by cell switching using a cell bus structure (ThroughPut), and a method for calculating a bus clock in the device.

Conventionally, an ATM concentrator has been implemented to accommodate various types of traffic simultaneously such as ATM subscribers, PDH subscribers, and frame relay subscribers and to efficiently connect to ATM networks.

However, in order to do this, a separate switching board is needed to switch and route data transmitted from each subscriber to the destination.

When implementing small ATM convergence devices, it is important to be able to accommodate a large number of subscribers and various traffic to a self with low cost and high integration of the number of subscribers.

At this time, when a small self-contained (19-inch rack) redundant small-sized switching module is inserted, the number of subscribers is reduced and the material cost per pod increases.

In addition, conventionally, a separate switching board is required to transmit data to each destination by switching and routing data to be transmitted by each subscriber or to transmit data received by the edge switch to each subscriber. In this case, since the switching board must be mounted on the centralizing apparatus, the number of subscribers to be accommodated in the limited apparatus becomes small if the material cost and the subscriber mounting slot of the apparatus become large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a small ATM concentrating apparatus which requires a throughput of up to 800 Mbps in order to centralize various subscribers and to switch to an edge exchanger or subscribers in the apparatus, It is an object of the present invention to provide an asynchronous transfer mode centralizing apparatus using a cell bus structure without a switching module.

Another object of the present invention is to provide a method for selecting timing and optimum bus clock in consideration of the efficiency of the entire system in an ATM centralizing apparatus.

Other objects and advantages of the present invention will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings

FIG. 1 is a block diagram of a cell bus according to an embodiment of the present invention. In FIG. 1, each subscriber connected to a cell bus among the configurations of the centralizing apparatus and the uplink are actually connected.

2 is a configuration diagram of a centralizing apparatus according to an embodiment of the present invention.

3 is a block diagram illustrating an ATM subscriber module function of the convergence apparatus according to an embodiment of the present invention.

FIG. 4 is a cell bus clock timing chart showing a hold time and a setup time of a system clock in consideration of FIG.

Description of the Related Art

101: The physical signals of the cell bus carry out the cell routing between the modules and the basic ATM switching function through the bus in which 37 lines are interconnected to each subscriber module by a parallel bus.

102: Included in each cell bus interface block, when a subscriber module is connected to the bus as a frame pulse on the bus, access to the remaining modules is blocked.

103: An ATM subscriber block is connected to an interface block on a cell bus, and the block serving as an ATM subscriber is connected to an ATM subscriber so that data of an ATM subscriber can be transmitted and switched on a bus Fig.

104: A module serving as a trunk that feeds the clock on the bus as an uplink module, collects cell data coming from each subscriber on the bus, and transfers the collected cell data to the ATM edge exchange. It is a link of OC3c (155.52Mbps) class or DS3 (44.736Mbps) class link.

105: An interface block is connected on a cell bus as a frame relay subscriber block, and blocks for performing a function of a frame relay subscriber are connected to the block so that data of a frame relay subscriber can be transmitted and switched on a bus.

106: Transmission delay time from the clock source to the cell bus interface.

107: Transmission delay time from the clock source to the cell bus interface.

201: Centralized cells transmitted from various subscribers such as ATM, PDH, and frame relay are transmitted to a backbone ATM edge exchanger, or conversely, cells transmitted from an exchange are received and transmitted to each subscriber Link.

301 is a block that performs central processing unit (ATM) and ATM signaling functions, and transmits signaling cells to ATM cells with AAL5 SAR (Segmentation And Reassembly) function to handle ATM signaling.

302: frame termination and generation function of signals transmitted and received from line interface, HEC generation and inspection, cell matching function, ATM cell mapping, and the like, having framer and ATM user interface (UNI) And transfers it to a block having ATM cell muxing and UPC function through utopia 2 interface.

303: A block serving as a cell processor that performs main functions of cell traffic monitoring for ATM functions.

304: Block with cell switching and routing on the cell bus as the main function.

305: line interface block.

401: Data setup time for falling edge of CBRC- signal.

402: Time warp between CBWC- and CBRC- signals.

403: Data setup time for falling edge of CBWC- signal.

404: Cell Bus Read Clock (CBRC-).

405: 32-bit cell bus data signal (Cell Bus Data 32 Bit: CBD (31-0)).

406: Cell Bus Frame signal (CBF-).

407: Cell Bus Acknowledge (CBACK-).

408: Cell Bus Congestion (CBCONG-).

409: Cell bus write clock signal (CBWC-).

According to another aspect of the present invention, there is provided an ATM centralizing apparatus using a cell bus without an ATM switching module,

A cell bus interconnecting all of the subscribers to transmit cell data;

A timing master and a bus arbiter block for adjusting timing when connecting to a bus;

An ATM subscriber block for transmitting or switching data of an ATM subscriber on a bus;

An uplink module for supplying a clock on the bus and transmitting the cell data to an ATM edge exchange; And

And a frame relay subscriber block for transmitting and switching the data of the frame relay subscriber on the bus including the block.

In the present invention, the cell bus is preferably composed of 37 lines,

The cell bus is preferably configured to include 32 data lines, 2 clock lines, 1 frame line, 1 response line, 1 congestion indication line,

The processing capability of the cell bus is preferably determined by the clock of the bus,

The clock is preferably divided into a read clock and a write clock,

Preferably, the rate of the bus clock determines the rate at which cells are prevented from accumulating at the entrance queue of the cell bus interface block,

The speed of the bus is preferably such that the cell transmission rate on the cell bus net does not exceed the sum of the rates of entry of the line into the entrance,

f _c Quot; is < / RTI > the bus clock, f _c × 53/2, and it is preferable that the inter-module routing function is performed through the cell bus,

It is preferable to perform a basic ATM switching function through the cell bus.

The timing master and the bus arbitration block are preferably included in each cell bus interface block,

The block is preferably a frame pulse on the bus so that when a module to which the subscriber is connected is connected to the bus,

The coordinator connected to the bus arbiter block by the connection preferably receives a bus access request signal to prevent connection of the remaining buses,

Preferably, the request signal is transmitted from a module having all cell bus interface blocks,

In the ATM subscriber block, blocks for performing an ATM subscriber function are preferably connected.

In the uplink module, the cell data is preferably transmitted from various subscribers on the cell bus,

It is preferable that the link can be mounted in an OC3c class which is an optical cable,

It is preferable that the link can be mounted in a DS3 class coaxial cable,

The frame relay subscriber block preferably performs a function of transmitting and switching data of a frame subscriber on a bus.

A preferred embodiment of a method for calculating a bus clock to implement a timing of a clock of a best cell bus according to the present invention for achieving another object is, for reliable bus operation,

t _d Is the data delay time for the falling edge of CBWC, t _s Is the time warp between CBRC and CBWC, t _p Is the propagation delay time between the end and the end of the bus, t _cd Is the propagation delay time from the clock source to the cell bus interface, t _cr Is the propagation delay time from the clock source to the cell bus interface, t _cyc Is the cycle time of the cell bus, t _hold Is the hold time of the system clock, t _setup Is the set-up time of the system clock,

t _d ;

t _cd Wow t _cr ;

t _setup ≪ / RTI >

Know the backplane size and ensure that the clock source is at the midpoint on the bus t _p ;

t _cyc To be slightly larger than the MOF;

t _s ; And

Using all the above parameters t _hold And a step of setting the step.

In the present invention, it is preferable to set the intermediate point on the bus in consideration of clock twist,

The best t _setup Is preferably set to 0 ns in consideration of the minimum time,

remind t _hold The t _d + t _s + t _p + ( t _cd - t _cr ), ≪ / RTI >

t _s Is preferably determined in consideration of a small phase offset for reliable bus operation.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It is to be understood, however, that the invention is not to be limited to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Should be understood to include.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An ATM centralizing apparatus using a cell bus without an ATM switching module of the present invention will be described with reference to FIGS. 1 to 3 attached hereto.

FIG. 1 is a block diagram of a cell bus according to an embodiment of the present invention. FIG. 1 shows each subscriber connected on a cell bus and a device to which an uplink is actually connected, of the system of the centralizing apparatus.

The cell bus is a total of 37 lines consisting of 32 lines of data with a hardware configuration on the backplane (backplane), 2 clocks, 1 frame, 1 response and 1 congestion indication. The data bit is set to 32 so that the processing power of the cell bus is determined by the clock. The clock is divided into a read clock and a write clock.

Each cell bus interface block connected on the cell bus has a timing master and a bus arbitration function, so that when the bus is connected, this function adjusts the timing. And is included in each cell bus interface block, so that when one module of the subscriber as a frame pulse on the bus is connected to the bus, the remaining modules become inaccessible and the connected coordinator can not occupy the remaining buses from the module having all the cell bus interface blocks The blocking receives a bus access request signal.

The bus rate related to the performance of the cell bus is related to the clock of the bus. The rate of the bus clock is accumulated in an inlet queue of a cell interface block (cell interface block) You must determine the speed at which you are guaranteed. This should ensure that the Cell Transfer Rate on the cell bus net does not exceed the sum of the rate at which it enters the line's entrance.

The 53-byte ATM cell coming into the bus has a 16-bus clock cycle, and each cycle is 4 bytes, which is transferred to one cell bus during one cell bus frame.

Therefore, the net cell transfer rate (NTR) can be calculated by the following equation.

NTR = 32 x f _c × 53/64 = f _c × 53/2,

here f _c Is the bus clock, and 53/64 is a unit of 53 bytes of incoming cell length divided by 64 bytes, the size of the cell being transmitted on the bus per frame.

For example, when the bus clock is 25 MHz, the NTR becomes 662.5 Mbps, and the capacity processed on the bus per second is calculated. The above speeds have a bus capacity that can handle 155.52 Mbps one and 20 25 Mbps lines for subscribers who can connect on the bus in system configuration.

The higher the bus clock, the larger the processing capacity. However, there is no problem in predicting the processing capacity of the system due to problems such as the backplane length and noise, etc., and to use the bus tracing system.

Each module has SRAM, which enables basic switching functions such as translation, routing, and cell buffering.

An ATM subscriber block is connected to an interface block on a cell bus, and blocks for functioning as an ATM subscriber are connected to the block.

Thus, the ATM subscriber is configured to transmit and switch the data of the ATM subscriber on the bus.

The uplink module is a module for supplying the clock on the bus, collecting the cell data transmitted from each subscriber on the cell bus, and transmitting the collected cell data to the ATM edge exchange. This module can be implemented with OC3c (155.52Mbps) fiber optic cable or DS3 (44.736Mbps) coaxial cable link.

2 is a configuration diagram of a centralizing apparatus according to an embodiment of the present invention. The uplink transmits the cells transmitted from various subscribers such as ATM, PDH, and frame relay through the OC3c or DS3 link to the ATM edge exchanger, which is the backbone, or the cells received from the exchange side, to the subscribers It is a link that performs transmission and reception.

FIG. 3 is a block diagram illustrating an ATM subscriber module function of the convergence apparatus according to an embodiment of the present invention, and is an important component of the present invention. As the ATM subscriber is connected on the cell bus, the data cell is switched and routed by a certain path or function to know whether the data cell is transmitted to the uplink side or the other subscriber in the device.

The block making the line connection is only an interface block for connection of the T1 / E1 subscriber, and the ATM subscriber connected thereto tries to connect for data transmission.

In this case, the signaling cell for connection is a central processing unit and a block that functions as an ATM signaling function. It has the function of adjusting functions in the module and the SAR (Segmentation and Reassembly) function of AAL5 for handling ATM signaling. .

Framers and ATM Blocks with UNI (User to Network Interface) functions have the functions of frame termination and generation of signals transmitted and received from the line interface, HEC generation and inspection, cell matching function, and ATM cell mapping function. To a block having ATM cell muxing and UPC (Usage Parameter Control) functions.

The block that performs the main function of cell traffic monitoring for ATM function also functions as a cell processor. This block has the function of monitoring the data cell for each user connected to the data cell coming in from the ATM subscribers. Surpasses the bandwidth capacity allowed for the user, delays, maximum widths, and sizes of data cells, and sends them to the cell bus interface.

The cell bus interface block has a function of recognizing whether the cell is going to the edge switch or the subscriber in the centralized device, creating an arbitrary header in the cell, and attaching a destination address to the cell bus interface block.

The cell bus interface block is a block that has cell switching and routing on a cell bus as a main function, and is a block for explaining how a centralizing device can switch and route without a switching module in an operation of the invention.

On the contrary, the cell bus interface analyzes the header of the data cell coming into the corresponding subscriber through the cell bus coordinator, determines which port of the subscriber module the subscriber of the subscriber module should send the data cell, and sends the data through the opposite path.

A bus clock calculation method in the centralizing apparatus of the present invention will be described below with reference to FIG. 1 or FIG. 4 attached hereto.

The hold time and setup time of the system are calculated by the following equation.

t _hold = t _d + t _s + t _p + ( t _cd - t _cr ),

t _setup = t _cyc - t _d - t _s - t _p - ( t _cd - t _cr ).

The parameters to be defined are as follows.

t _d Is the data delay time for the falling edge of CBWC,

t _s Is the time warp between CBRC and CBWC,

t _p Is the propagation delay time between the end and the end of the bus,

t _cd Is the propagation delay time from the clock source to the cell bus interface,

t _cr Is the propagation delay time from the clock source to the cell bus interface,

t _cyc Is the cycle time (CBRC, CBWC) of the cell bus,

t _hold Is the hold time of the system clock,

t _setup Is the setup time of the system clock.

In the above equation t _cyc = t _setup + t _d + t _s + t _p + ( t _cd - t _cr ), t _d 23ns, t _cd = t _cr = 0.5 x t _p .

t _setup Is set to 0 ns in order to set the minimum setup time. therefore t _cyc 23.5 ns + t _s + t _p .

If the backplane size is 19 inches and the clock source is located midway on the bus t _p Is set to 5 ns, and at this time t _s = t _cyc - 23.5 ns - t _p .

therefore t _cyc Must be greater than 31.5 ns since the MOF (Max Operation Frequency) is approximately 31.7 MHz.

t _cyc Is 31.5 ns, t _p Is 5 ns, the read / write clock is the same clock, but a small phase offset is required for reliable bus operation t _s It can be seen that a time of about 3 ns is required by the above equation.

In order to select these timings and the optimum bus clock, it is necessary to sufficiently examine the above, and the ATM concentrating apparatus is designed with a clock of a system of 25 MHz in consideration of the efficiency of the entire system.

In the ATM concentrator according to the present invention, since the switching module is not required by considering the cell bus, and the switching function is realized by each module having the cell bus interface, the ATM, PDH, And the other subscribers are switched to a cell bus that guarantees a sufficient transmission efficiency through a single bus.

In this way, the switch module is replaced with a subscriber module, and it is possible to develop an efficient equipment at a low cost, thereby obtaining an advantage that an efficient ATM concentrator can be developed.

Claims (24)

A cell bus interconnecting all of the subscribers to transmit cell data; A timing master and a bus arbiter block for adjusting timing when connecting to a bus; An ATM subscriber block for transmitting or switching data of an ATM subscriber on a bus; An uplink module for supplying a clock on the bus and transmitting the cell data to an ATM edge exchange; And And a frame relay subscriber block for transmitting and switching data of a frame relay subscriber including a block on a bus, without using an ATM switching module. The ATM concentrator according to claim 1, wherein the cell bus comprises 37 lines. 3. The ATM concentrator according to claim 2, wherein the cell bus includes 32 data lines, 2 clock lines, 1 frame line, 1 response line, and 1 congestion indication line. The ATM concentrator according to claim 1, wherein the processing capability of the cell bus is determined by the clock of the bus, without the ATM switching module. 5. The ATM concentrator according to claim 4, wherein the clock is divided into a read clock and a write clock. 5. The ATM concentrator of claim 4, wherein the rate of the bus clock determines a rate at which cells are prevented from accumulating in an ingress queue of a cell bus interface block. 5. The ATM concentrator of claim 4, wherein the speed of the bus is such that the cell transfer rate on the cell bus net does not exceed the sum of the rate of entry into the line's entrance. 8. The method of claim 7, f _c When the bus is clocked, The cell transmission ratio f _c × 53/2, ATM concentrating device using cell bus without ATM switching module. 2. The ATM concentrator according to claim 1, wherein the ATM concentrator performs a routing function between the modules via the cell bus. The ATM concentrator according to claim 1, wherein the ATM switch module performs a basic ATM switching function through the cell bus. The ATM concentrator according to claim 1, wherein the timing master and the bus arbitration block are included in each cell bus interface block. 12. The ATM concentrator according to claim 11, wherein the block is a frame pulse on a bus, and when a subscriber module is connected to a bus, the remaining modules are not accessible. 13. The ATM concentrator according to claim 12, wherein the coordinator connected to the bus arbiter block by the connection receives a bus access request signal to prevent connection of the remaining buses. 14. The ATM concentrator according to claim 13, wherein the request signal is transmitted from a module having all cell bus interface blocks. The ATM concentrator according to claim 1, wherein the ATM subscriber block is connected to blocks for performing an ATM subscriber function. The ATM concentrator according to claim 1, wherein the cell data in the uplink module is transmitted from various subscribers on a cell bus. 2. The ATM concentrator according to claim 1, wherein the link can be implemented in OC3c class, which is an optical cable, without an ATM switching module. The ATM concentrator according to claim 1, wherein the link is a DS3 class coaxial cable. 2. The ATM concentrator according to claim 1, wherein the frame relay subscriber block performs a function of transmitting and switching data of a frame subscriber on a bus. For reliable bus operation, t _d Is the data delay time for the falling edge of CBWC, t _s Is the time warp between CBRC and CBWC, t _p Is the propagation delay time between the end and the end of the bus, t _cd Is the propagation delay time from the clock source to the cell bus interface, t _cr Is the propagation delay time from the clock source to the cell bus interface, t _cyc Is the cycle time of the cell bus, t _hold Is the hold time of the system clock, t _setup Is the set-up time of the system clock, t _d A first step of setting a first step; t _cd Wow t _cr A second step of setting a second step; t _setup The third step Know the backplane size and ensure that the clock source is at the midpoint on the bus t _p ; t _cyc A fifth step of setting a value slightly larger than the MOF; t _s A sixth step of setting up a second step; And Using all the above parameters t _hold And a seventh step of calculating a bus clock of the cell bus. 21. The method of claim 20, wherein in the second step, the intermediate point on the bus is set considering clock torsion, and the timing of the clock of the best cell bus is set. 21. The method of claim 20, wherein in the third step, t _setup Is set to 0 ns in consideration of a minimum time, and a bus clock is calculated to implement the timing of the clock of the cell bus. 21. The method of claim 20, wherein in the fifth step, t _hold The t _d + t _s + t _p + ( t _cd - t _cr ) To calculate the bus clock to realize the timing of the clock of the best cell bus. 21. The method of claim 20, wherein in the sixth step, t _s Wherein the timing of the clock of the best cell bus is determined in consideration of a small phase offset for reliable bus operation.