KR19990068872A - Data cache memory controller - Google Patents

Abstract

The present invention relates to a control device of a data cache memory, and includes an instruction prefetch buffer for extracting and storing instructions to be executed later from the main memory or the instruction cache memory, and a command to be executed next among instructions stored in the instruction prefetch buffer. The command fetcher that retrieves and outputs the command, the command executor that executes the command fetched by the command fetcher, determines whether the data necessary to execute the instructions stored in the command prefetch buffer exists in the data cache memory, If it does not exist in the data cache memory, it comprises a data cache memory control unit for controlling to retrieve the necessary data from the main memory to store in the data cache memory. In particular, the data cache memory controller according to the present invention analyzes all of the instructions waiting in the instruction prefetch buffer and the instructions to be executed immediately after being input to the instruction execution unit, and the data necessary to execute each instruction is present in the data cache memory. By determining and securing necessary data, the probability of occurrence of cache misses in the data cache memory is reduced. Therefore, the instruction waiting in the instruction prefetch buffer is passed to the instruction execution unit later to be executed immediately by using the data already secured in the data cache memory when it is actually executed, thereby reducing unnecessary waiting time of the instruction execution unit. It is to greatly improve the operation speed.

Description

Data cache memory controller

The present invention relates to an apparatus for controlling a data cache memory of a computer system. In particular, the present invention relates to an instruction cache memory and a data cache memory, and to determine whether or not data necessary for executing an instruction of a central processing unit exists in the data cache memory. The present invention relates to a control device of a data cache memory that retrieves necessary data from main memory and stores the data in a data cache memory.

Cache memory is a very important component that improves the performance of a computer system. Generally, computer systems have a memory as a basic component, which is divided into various levels according to its characteristics. The criteria for classifying these levels are data storage capacity and processing speed. The higher the speed, the higher the level. Higher levels of memory have relatively little storage capacity because the storage capacity is inversely proportional to the processing speed. In general personal computer or workstation class computer except large computer, use DRAM as main memory. DRAM is easier to manufacture and higher density than SRAM, so it is cheaper than capacity. This is the biggest reason for using DRAM as main memory. SRAM, on the other hand, is more expensive than DRAM because of its low density and relatively low fabrication. However, in terms of operation speed, it is much better than DRAM, so large computers use this SRAM as main memory.

However, computer systems equipped with DRAM as main memory use SRAM as memory, but cache memory is used instead of main memory. The cache memory is a memory provided between the CPU and the main memory to store some highly correlated data among the data stored in the main memory. When the CPU retrieves data, the CPU first checks the cache memory to determine whether the data to be retrieved exists in the cache memory, and then accesses the main memory when the CPU does not exist. Therefore, the central processing unit withdraws data to the cache memory made of SRAM relatively faster than the main memory made of DRAM, it is possible to process the data as fast.

As mentioned, cache memory has a feature of smaller data storage capacity than main memory. If you have a cache memory of almost the same storage capacity as the main memory, the main memory at this time is no longer meant to exist. Because the use of cache memory in addition to main memory uses fast operation speed and high price of SRAM as small capacity cache memory, and relatively slow operation speed and low price DRAM as large capacity main memory to complement each other. This is because it is intended. As such, the cache memory has a smaller capacity than the main memory so that only a part of the data of the main memory can be accommodated. Therefore, when the CPU accesses the cache memory to retrieve data, the data that the CPU intends to retrieve may not exist in the cache memory. A case in which the data to be fetched by the CPU exists in the cache memory is called a hit, and a case in which the CPU does not exist is called a miss.

When cache memory is classified based on a data recording method, there are a wright through and a wright back method. The write-through method writes data to cache memory and main memory at the same time, whereas the write-back method first writes to cache memory and then moves the existing data to main memory when it needs to replace the data in the corresponding block of cache memory. Replace the corresponding block in cache memory with new data.

If a cache hit occurs in the writeback cache memory, the data of the corresponding block of the cache memory can be fetched. However, if a cache miss occurs, the data of the corresponding block of the cache memory is replaced with the new data of the main memory. The device fetches replaced data in cache memory rather than main memory. Therefore, it takes much longer for the CPU to fetch the necessary data in case of cache miss than in case of cache hit. This loss of time when a cache miss occurs is called a miss penalty, plus the time it takes to replace data in main memory with cache memory plus the time it takes for the central processing unit to fetch the replaced data from cache memory. will be.

Since the purpose of using the cache memory is to compensate for the slow operation speed of the main memory, the cache miss rate must be reduced in order to fully achieve such a purpose of the cache memory. However, if the cache miss is inevitable due to the capacity limitation, There is. However, even if a cache miss occurs, reducing the miss penalty accordingly can compensate for the loss of operating speed due to the cache miss. Therefore, a means for reducing the miss penalty is urgently required.

1 is a block diagram illustrating a connection relationship between a central processing unit, an instruction cache memory, a data cache memory, and a main memory in a computer system. An instruction cache memory 2 and a data cache memory 3 are connected between the central processing unit 1 and the main memory 4. The instruction cache memory 2 performs the original function of the cache memory only between the central processing unit 1 and the main memory 4, and the data cache memory 3 also performs the central processing unit 1 main memory. The memory 4 performs the original function of the cache memory only for data. In this way, the instruction and data are handled separately to achieve a faster operation speed.

FIG. 2 is a block diagram showing an interconnection relationship between components related to control of the data cache memory of the central processing unit shown in FIG. 1 and the data cache memory. In the CPU 1, there is an instruction prefetch buffer 5, an instruction extractor 6, a decoder 7, an instruction execution unit 8, a write back controller 9, and a data cache memory controller 10. ) And the like. The command execution unit 8 is a part that actually executes the retrieved command. The data cache memory control unit 10 analyzes a command to be executed in the command execution unit 8, extracts necessary data from the data cache memory 3, and provides the data to the command execution unit 8.

However, if a cache miss occurs in the data cache memory 3, the write back control unit 9 performs a write back between the main memory and the data cache memory 3. Although data necessary for the operation of the instruction execution unit 8 is secured in the data cache memory 3 by the write back, the instruction execution is executed while the data cache memory 3 secures the data necessary, that is, while the write back operation is performed. The unit 8 is a large cause of slowing down the operation speed of the central processing unit 1 because it must wait without executing the next command.

Therefore, the present invention analyzes the instruction to be executed next in advance before the instruction is transferred to the instruction execution unit, and then checks whether the required data exists in the data cache memory according to the analysis result, and if not, in the main memory. By retrieving necessary data and securing it in the data cache memory in advance, the probability of occurrence of cache misses in the data cache memory is reduced, and the data cache reduces unnecessary waiting time by providing the necessary data immediately when the instruction is executed in the instruction execution unit. Its purpose is to provide a control device for a memory.

1 is a block diagram showing a connection relationship between a central processing unit, an instruction cache memory, a data cache memory, and a main memory;

FIG. 2 is a block diagram showing an interconnection relationship between components related to control of the data cache memory of the central processing unit shown in FIG. 1 and the data cache memory; FIG.

3 is a block diagram showing an interconnection relationship between a data cache memory control apparatus and a data cache memory according to the present invention;

Explanation of symbols on the main parts of the drawings

1, 11: central processing unit 2: instruction cache memory

3: data cache memory 4: main memory

5: instruction prefetch buffer 6: instruction fetch unit

7, 12: decoder 8: instruction execution unit

9: write back control unit 10, 13: data cache memory control unit

The present invention for this purpose is a command prefetch buffer for retrieving and storing instructions to be executed later in the main memory or the instruction cache memory, and instructions for retrieving and outputting the next instruction to be executed among the instructions stored in the instruction prefetch buffer. The fetcher, the instruction executor that executes the instructions fetched by the instruction fetcher, determines whether the data needed to execute the instructions stored in the instruction prefetch buffer exists in the data cache memory, and the necessary data does not exist in the data cache memory. If not, it comprises a data cache memory control unit for controlling to retrieve the necessary data from the main memory to store in the data cache memory.

3 is a view showing a preferred embodiment of the present invention, showing the interconnection relationship between the components related to the control of the data cache memory of the central processing unit and the data cache memory. In FIG. 3, the instruction prefetch buffer 5 retrieves and stores instructions to be executed next from the main memory or the instruction cache memory. In this case, the instruction prefetch buffer 5 retrieves and stores one or more related instructions necessary to perform a specific operation, which is a faster way to perform a series of operations by prefetching an instruction to perform a specific operation. It is for. The instruction fetcher 6 retrieves the instructions stored in the instruction prefetch buffer 5 in the order of execution and transfers the instructions to the decoder 7 of the next stage. The decoder 7 decodes the command output from the command extractor 6 and outputs the command to the next command execution unit 8 so that the command execution unit 8 can execute the decoded command.

In FIG. 3, the write back control unit 9, the data cache memory 3, and the data cache memory control unit 13 exchange data with the command execution unit 8 or control objects of the command execution unit 8. have. The writeback control unit 9 controls the writeback operation performed between the data cache memory 3 and the main memory when a cache miss occurs in the data cache memory 3. The data cache memory 3 provides data necessary for executing a predetermined instruction in the instruction execution section 8.

In particular, the data cache memory control unit 13 analyzes the commands input to the command execution unit 8, and determines whether the data necessary for the execution of the command exists in the data cache memory 3 to secure the necessary data. In addition, the data stored in the command prefetch buffer 5 is analyzed to analyze the commands stored in the command prefetch buffer 5 so as to secure data necessary for the execution of the instructions waiting in the data cache memory 3.

Since the instruction stored in the instruction prefetch buffer 5 is not an instruction to be executed immediately, it has some time to actually be executed by the instruction execution section 8. During this time margin, the data cache memory control unit 13 analyzes the instructions currently stored in the instruction prefetch buffer 5 to determine whether data necessary for the execution of the instructions exists in the data cache memory 3. At this time, the decoder 12 is used to analyze the instruction prefetch buffer 5. If the required data does not exist in the data cache memory 3 (cache miss), the required data is extracted from the main memory and stored in the data cache memory 3. In the meantime, if the instruction waiting in the instruction prefetch buffer 5 is in the order to be executed by the instruction execution section 8, the data execution memory 8 already secures the necessary data, so that the instruction execution section 8 immediately executes the instruction. You can run

If necessary data exists in the data cache memory 3 (cache hit), the data cache memory control unit 13 performs the same general operation as before. That is, the data cache memory control unit 13 analyzes the command input to the instruction execution unit 8 and determines whether necessary data exists in the data cache memory 3 according to the analysis result. If present, the instruction execution section 8 executes the instruction normally by retrieving the data and providing the data to the instruction execution section 8. However, if a cache miss occurs because data necessary for the data cache memory 3 does not exist, the necessary data is extracted from the main memory through the writeback control unit 9 and stored in the data cache memory 3. The instruction execution unit 8 executes a command using the data secured in the data cache memory 3.

As described above, the data cache memory controller 13 analyzes all of the instructions waiting in the instruction prefetch buffer 5 and the instructions inputted to the instruction execution unit 8 to be executed immediately and analyzes each instruction. By determining that the data required for execution exists in the data cache memory 3 and securing the necessary data, the data waiting when the instruction currently waiting in the instruction prefetch buffer 5 is subsequently transferred to the instruction execution section 8 and actually executed. The data secured in the memory 3 can be immediately executed.

The data cache memory controller according to the present invention analyzes all of the instructions waiting in the instruction prefetch buffer and instructions to be executed immediately after being input to the instruction execution unit, and determines whether data necessary to execute each instruction exists in the data cache memory. Therefore, the probability of occurrence of cache misses in the data cache memory is reduced by securing necessary data. Therefore, the instruction waiting in the instruction prefetch buffer is passed to the instruction execution unit later to be executed immediately by using the data already secured in the data cache memory when it is actually executed, thereby reducing unnecessary waiting time of the instruction execution unit. It is to greatly improve the operation speed.

Claims (5)

In the controller of the data cache memory, An instruction prefetch buffer that retrieves and stores instructions to be executed later in the main memory or the instruction cache memory; A command fetch unit for fetching and outputting a command to be executed next among the commands stored in the command prefetch buffer; A command execution unit for executing a command fetched by the command extracting unit; It is determined whether the data required to execute the command stored in the command prefetch buffer exists in the data cache memory. If the necessary data does not exist in the data cache memory, the required data is fetched from the main memory. And a data cache memory control unit for controlling the data cache memory to be stored in the data cache memory. The apparatus of claim 1, wherein the instructions stored in the instruction prefetch buffer are decoded and input to the data cache memory controller. The apparatus of claim 1, wherein the command output from the command extracting unit is decoded and input to the command executing unit. The data cache memory control unit of claim 1, wherein the data cache memory controller determines whether data necessary for executing the command input to the command execution unit exists in the data cache memory, and the data required to execute the command input to the command execution unit is determined. The controller of the cache memory which controls to retrieve necessary data from the main memory and to store it in the data cache memory when it does not exist in the data cache memory. The apparatus of claim 1, wherein the instruction prefetch buffer, the instruction extracting unit, the instruction execution unit, and the data cache memory control unit are components of a central processing unit.