KR19990066716A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device having a field effect transistor having different characteristics in the same substrate, and to a method for simultaneously fabricating a field effect transistor having different characteristics in the same substrate in an ion implantation process without using an impurity diffusion process. to provide.

First and second gate electrodes are formed in different directions on the substrate, and n-type ions are implanted in a direction having a predetermined inclination angle θ ° from the normal direction of the substrate to the gate formation direction of the first gate electrode.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a manufacturing method and a structure of a semiconductor device having a field effect transistor having different characteristics in the same substrate.

In a digital DCFL circuit or an SCFL circuit, it is necessary to form field effect transistors having different threshold voltages V _th on the same substrate. In addition, in order to integrate analog circuit elements such as HPA (high output amplifier) and LNA (low noise amplifier), it is also necessary to fabricate high-voltage field effect transistors or the like on the same substrate.

In such a case, the manufacturing process is complicated to manufacture the enhancement channel E-ch and the depletion channel D-ch by using different processes by changing the impurity implantation amount of the channel region for each transistor. .

For example, in Japanese Patent Laid-Open No. 61-189670, gate electrodes are formed in (11) and <11> directions orthogonal to the substrate, respectively, and these gate electrodes are used as masks from the normal direction of the substrate. after implanting ions, diffusing the implanted ions in the gate electrode lower in the annealing process, by using a difference of the ion diffusion rate of the by the crystal orientation, and the channel concentration of the gate electrode lower part to differ in accordance with the gate directions, V _th Is forming another transistor.

In the method of controlling V _th using the diffusion rate of the implanted ions, for example, thermal diffusion for 10 to 20 minutes is required at 850 ° C., and other impurities are also diffused during the diffusion of the implanted ions, thereby forming the shape and concentration of the impurity region. There was a problem that the characteristics of the device according to the design cannot be obtained due to the change of. In particular, in the recent annealing process, an RTA (Rapid Thermal Anneal) method, in which impurities are not diffused by annealing in a very short time (seconds), is used. As such an RTA method, as described above, the channel under the gate electrode is used. It was not possible to change the concentration.

Accordingly, an object of the present invention is to provide a manufacturing method and a structure of a semiconductor device for simultaneously fabricating field effect transistors having different characteristics in the same substrate in an ion implantation step without using an impurity diffusion step.

1 is a view showing a gate electrode forming direction according to a first embodiment of the present invention.

2 is a view showing an ion implantation process according to the first embodiment of the present invention.

3 illustrates a field effect transistor of an LDD structure according to a first embodiment of the present invention.

4 is a view showing an ion implantation process according to a second embodiment of the present invention.

5 is a view showing an ion implantation process according to a third embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1 GaAs (100) substrate 2 n-type channel layer

4: Channel area 5,5 ': n ⁺ area

6: implantation ion 7: SiO ₂ layer

11: first gate electrode 12: second gate electrode

Therefore, as a result of intensive research, the inventors have formed first and second gate electrodes in different directions on the GaAs substrate, and the gate width direction of the first gate electrode from the normal direction of the substrate (hereinafter referred to as "gate formation direction"). In the case of implanting n-type ions in two symmetrical directions having a predetermined inclination angle θ °, the characteristics of the first transistor are not different from those of implanting n-type ions from the normal direction, and the second gate. Only the channel region under the electrode can be shortened, and by using the short channel effect, a small current flows in the substrate region under the second channel region so that V _th of the second transistor can be shifted to the negative voltage side. The present invention was completed by finding out possible things.

That is, the present invention provides a method of manufacturing a semiconductor device in which two kinds of field effect transistors having different characteristics are formed on the same substrate, wherein the first and second gate formation directions are different on the n-type channel layer provided on the substrate. A gate electrode forming step of forming a second gate electrode, and n-type ions are implanted at an inclination angle θ ° from the normal direction of the substrate by using the first and second gate electrodes as masks, and the first and second gate electrodes are formed. And an ion implantation step in which n ⁺ regions are formed on both sides of and the n-type channel layer sandwiched between the n ⁺ regions is used as a channel region.

As described above, by inclining ion implantation using the first and second gate electrodes having different directions as masks, the positions and channel lengths of the first and second channel regions formed in the lower regions of the first and second gate electrodes are different. Can be formed. Therefore, it is possible to form the first transistor (transistor with first gate electrode) and the second transistor (transistor with second gate electrode) having different transistor characteristics using the same ion implantation process.

In addition, the present invention. The ion implantation process injects n-type ions in two symmetrical directions of the inclination angle θ ° from the normal direction of the substrate to the gate formation direction of the first gate electrode, and blocks the channel region under the second gate electrode. The semiconductor device manufacturing method is also a step of forming the n ⁺ region so that a minute current flows inside the substrate under the channel region even in the above state.

First, in the first transistor, when the first transistor is formed by ion implantation in two directions symmetrical with the inclination angle θ ° from the normal direction of the substrate to the gate width direction, n is formed as compared with the case of ion implantation in the normal direction of the substrate. The position of the ⁺ region does not change, and the transistor characteristics are also the same.

On the other hand, in the second transistor, since the n ⁺ region extends from both sides of the gate electrode to the lower portion of the gate electrode, even if the channel length is shortened and the channel region is blocked by the depletion layer by the short channel effect, the channel region is still present. Micro current flows in the lower part. For this reason, pinch-off will not be performed unless the gate voltage is negatively applied again to increase the depletion layer. That is, by using the short channel effect, it becomes possible to shift V _th to the negative voltage side.

As described above, according to the present invention, it is possible to simultaneously produce transistors having different Vth in the same ion implantation process, thereby simplifying the manufacturing process and reducing the cost.

In addition, in the present invention, the ion implantation process implants n-type ions in a direction in which the inclination angle is θ ° from the normal direction of the substrate to the gate formation direction of the first gate electrode, and the one side of the second gate electrode is also a method of manufacturing a semiconductor device, it characterized in that the step of forming the n ⁺ region of this claim above for the second gate electrode, to fall to the second gate electrode n + region asymmetrically.

In this way, by implanting n-type ions in one direction at an inclination angle θ °, the first transistor has the same transistor structure as when implanted from the normal direction of the substrate, while in the second transistor, the n ⁺ region and the gate electrode which are opposite to the gate electrode. The transistor structure has a larger interval. Therefore, by setting the n ⁺ region away from the gate electrode as a drain region, it is possible to form a transistor having a large gate breakdown voltage.

The gate electrode forming step, to a SiO ₂ layer formed on the gate electrode as a mask, by performing the side etching of the gate electrode, and a step of the SiO ₂ layer protruding in the gate length direction, the ion implantation process this may be the SiO ² layer to the step of performing the ion implantation by the mask.

By forming the SiO ₂ layer protruding in the gate longitudinal direction in this manner, it is possible to adjust the distance between the gate electrode and the n ⁺ region, and for example, to form a first transistor having a large gate breakdown voltage.

It is preferable that the said gate electrode formation process is a process which makes the direction which has an angle of 20-30 degrees from the <110> direction in the substrate plane which consists of GaAs (100) substrates into the gate formation direction of a said 1st gate electrode.

By making the direction the gate forming direction in this way, it is possible to suppress the occurrence of the channeling phenomenon when injecting the gate forming direction of the first gate electrode at a predetermined inclination angle θ °, and to obtain a desired concentration profile in ion implantation. Become.

It is preferable that the said inclination angle (theta) degrees is chosen in the range of 7-20 degrees.

By ion implantation at such an inclination angle θ °, occurrence of channeling phenomenon can be suppressed.

In addition, the present invention provides a semiconductor device having first and second field effect transistors having different gate forming directions formed on the same substrate, wherein the second field effect transistor is disposed below the gate electrode from both sides of the gate electrode. And an n ⁺ region formed by n-type ion implantation so as to extend to and an n-type channel region sandwiched between the n ⁺ regions, and inside the substrate under the n-type channel region even when the n-type channel region is blocked. It is also a semiconductor device characterized by having a characteristic that a small current flows.

This is because by using such a semiconductor device, a field effect transistor having a different V _th can be fabricated in the same substrate, and a DCFL circuit or the like can be easily formed.

In addition, the present invention is that the substrate is made of a GaAs (100) substrate, the gate forming direction of the first field effect transistor is a direction having an angle of 20 to 30 degrees from the <110> direction in the substrate plane. It is also a semiconductor device characterized by the above-mentioned.

By setting this direction as the gate forming direction of the first gate electrode, the occurrence of channeling phenomenon in the ion implantation process can be suppressed and the semiconductor device faithful to the device design can be formed.

EXAMPLE

(Example 1)

A first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

First, as shown in FIG. 1, a GaAs (100) substrate 1 having an n-type channel layer 2 is prepared, and a first gate electrode having a different gate formation direction on the n-type channel layer 2 is prepared. (11) and the second gate electrode 12 are formed (gate electrode forming step).

In the first embodiment, the first gate electrode 11 and the second gate electrode 12 are formed to be orthogonal to each other, but the gate formation direction is selected in accordance with the characteristics required for the transistor to be manufactured. In addition, the gate formation direction is preferably a direction having an angle of 20 to 30 ° from the <110> direction in the plane of the GaAs (100) substrate 1 in that the channeling phenomenon in the ion implantation process can be prevented. Do.

Next, as shown in FIG. 2, the inclination angle θ ° in the gate forming direction from the normal direction of the substrate 1 using the first gate electrode 11 and the second gate electrode 12 as a mask (see FIG. 1). The n-type ions 6 are implanted in the direction of (ion implantation step). In the first embodiment, n-type ions 6 such as Si ions are implanted, respectively, in two symmetrical directions along the normal line. Since the implantation step is performed by forming a mask (not shown) such as a resist in a region other than the regions on both sides of the gate electrodes 11 and 12, the first gate electrode 11 and the second gate electrode 12 are formed. N ⁺ region 5 is selectively formed only on both sides of the n, and the n-type channel layer 1 sandwiched in the n ⁺ region 5 becomes the channel region 4.

By performing such inclined ion implantation, in the first transistor shown in the left figure of FIG. 4) This structure has a structure substantially the same as that of the ion implantation in the normal direction of the substrate 1, and the transistor characteristics do not change.

On the other hand, in the second transistor shown in the right drawing of Fig. 2, since the ion implantation is performed on both sides of the gate electrode 12 at an inclination angle θ ° in the direction perpendicular to the gate formation direction, the n ⁺ region 5 is gated. The electrode 12 also extends to the lower side of the electrode.

As described above, in the second transistor, the channel length is shorter than that of the first transistor, whereby the short channel effect can be intentionally generated. That is, by shortening the channel region 4 of the second transistor to generate a short channel effect, even when the channel region 4 is blocked by a depletion layer extending from the gate electrode 12, the substrate under the channel region 4 is blocked. Microcurrent can flow in (1). In order to completely block the microcurrent and pinch off the channel, it is necessary to apply a negative voltage to the gate electrode 12 again to increase the depletion layer to the inside of the substrate 1 under the channel region 4. As a result, it becomes possible to shift V _th of the second transistor to the negative voltage side.

Thus, by using the method according to the present invention, it is possible to simultaneously fabricate the first and second transistors having different V _th in the same ion implantation process, thereby simplifying the manufacturing process and reducing the cost. For example, a depletion transistor and an enhancement transistor having different V _th are formed at the same time, so that a DCFL circuit or the like can be manufactured.

In the structure of the right figure of FIG. 2, since n-type ions 6 are implanted only in the implantation in one direction during the ion implantation in the two directions, the gate electrode 12 is in the vicinity of the gate electrode 12. The density | concentration of the ⁺ area | region 5 becomes comparatively low, and it becomes possible to prevent the fall of gate breakdown voltage.

In the first embodiment, the first gate electrode 11 and the second gate electrode 12 are formed to be orthogonal to each other, but the channel width of the second transistor is changed by changing the gate forming direction of the second gate electrode 12. Since the transistor characteristics can be controlled by changing (4), the gate formation direction may be selected according to the required device characteristics.

Further, by shifting the gate formation direction of the first gate electrode and the inclination angle θ ° direction of ion implantation, the length of the channel region 4 of the first transistor can be controlled at the same time. As shown in Fig. 3, n ⁺ regions 5 'are formed in advance on both sides of the first and second gate electrodes 11 and 12 at regular intervals by vertical ion implantation or the like, and then the injection amount is By reducing the ion implantation 6, it is possible to form a LDD (Lightly Doped Drain) structure.

(Example 2)

A second embodiment of the present invention will be described with reference to FIG.

The gate electrode forming step is performed in the same manner as in Example 1 by preparing the GaAs (100) substrate 1.

In this embodiment, the SiO ₂ layer 7 which covers the first and second gate electrodes 11 and 12 and protrudes in the gate longitudinal direction is formed.

Next, as shown in Figure 4, the gate is formed first by a gate electrode 11, the second gate SiO ₂ layer formed respectively on the electrode (12) (7) as a mask, in the normal direction of the substrate (1) Direction, n-type ions 6 such as Si ions are implanted at an inclination angle θ ° (see Fig. 1) (ion implantation step). In such an implantation step, since a mask (not shown) such as a resist is formed in regions other than the regions on both sides of the gate electrodes 11 and 12, the first gate electrode 11 and the second gate electrode 12 are formed. An n ⁺ region 5 is selectively formed only on both sides of the n ⁺ , and the n type channel layer 1 sandwiched in the n ⁺ region 5 becomes the channel region 4.

In Example 2, ion implantation is performed in only one direction as shown in FIG. By this ion implantation, in the first transistor shown in the left figure of FIG. 4, n ⁺ region 5 is formed at positions spaced symmetrically with the gate electrode 11 interposed therebetween. In such a structure, the structure becomes the same as in the case of ion implantation in the normal direction of the substrate 1, and the transistor characteristics do not change, but a gap can be provided between the gate electrode 11 and the n ⁺ region 5. Compared with the structure shown in the left figure, the gate breakdown voltage can be improved.

On the other hand, in the second transistor, since the distance between the gate electrode 12 and the drain region (n ⁺ region) can be further increased as compared with the diagram on the right side in FIG. 2, the gate withstand voltage can be made higher.

The first transistor fabricated by the method according to the second embodiment is applied to a device requiring a high mutual conductance (g _m ) although the breakdown voltage may be relatively low, such as a low noise amplifier, for example. Applied to devices requiring high gate breakdown voltage, such as devices.

(Example 3)

A third embodiment of the present invention will be described with reference to FIG.

In the third embodiment, the two-way implantation of the first embodiment is applied to a structure including the SiO ₂ film 7 of the _second embodiment.

The first transistor produced by the method according to the present embodiment is a transistor having a higher breakdown voltage than the second transistor, and the second transistor is a transistor having a low breakdown voltage but a low Rs and a high mutual conductance (g _m ). . Thus, for example, the first transistor is applied to a high output amplifier or the like, and the second transistor is applied to a low noise amplifier, a logic transistor or the like.

In Examples 1 to 3, the n-type channel layer 2 formed on the GaAs (100) substrate 1 may be produced by ion implantation or by crystal growth. It is also possible to use an off substrate of about 0 to 10 degrees for the GaAs 100 substrate 1.

Further, in Examples 1 to 3, it is preferable that the direction having an angle of 20 to 30 degrees from the in-plane <110> direction of the GaAs substrate 1 is the gate forming direction of the first gate electrode 11. Preferably, the inclination angle θ ° is selected in the range of 7-20 °.

By ion implantation under such conditions, the occurrence of channeling phenomenon can be prevented, and the device structure as designed can be obtained.

As is clear from the above description, by using the semiconductor device manufacturing method according to the present invention, transistors having different V _th can be simultaneously produced in the same ion implantation process, and the manufacturing process can be simplified and the cost can be reduced.

In addition, in the same ion implantation process, transistors having different gate breakdown voltages and mutual conductances can be manufactured at the same time, and it is possible to form transistors of different characteristics according to design in a simple process.

Claims (3)

In a method of manufacturing a semiconductor device, in which two kinds of field effect transistors having different characteristics are formed on the same substrate, A gate electrode forming step of forming first and second gate electrodes having different gate forming directions on an n-type channel layer provided on the substrate; Using the first and second gate electrodes as masks, n-type ions are implanted at an inclination angle θ ° from the normal direction of the substrate to form n ⁺ regions on both sides of the first and second gate electrodes. ^And an ion implantation step of using the n-type channel layer sandwiched between the ⁺ regions as a channel region. The method of claim 1, In the ion implantation process, n-type ions are respectively implanted in two symmetrical directions of an inclination angle θ ° from a normal direction of the substrate to a gate formation direction of the first gate electrode, And forming the n ⁺ region so that a current increases in a channel region under the second gate electrode. A semiconductor device comprising first and second field effect transistors having different gate formation directions formed on the same substrate, The second field effect transistor includes an n ⁺ region formed by n type ion implantation so as to extend from both sides of the gate electrode to the lower portion of the gate electrode, and an n type channel region sandwiched between the n ⁺ regions, And a small current flows into the substrate under the n-type channel region even when the n-type channel region is blocked.