KR19990066678A - Word line voltage generation circuit of semiconductor memory device for storing multi-bit data - Google Patents

Abstract

The semiconductor memory device of the present invention provides a word line voltage generation circuit, which automatically converts the changed word line voltage when the threshold voltage of the memory cell changes or the word line voltage changes due to a process change. Can be readjusted to the word line voltage of the desired level. Accordingly, the cell current may be prevented from changing as the threshold voltage of the memory cell changes due to the process change, thereby preventing the reliability of the read fail from deteriorating.

Description

WORD LINE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTI-BIT DATA in Semiconductor Memory Devices for Storing Multi-Bit Data

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a word line voltage generating circuit of a semiconductor memory device for storing multi-bit data.

Increasingly, as semiconductor memory devices become denser, semiconductor makers are working on semiconductor memory devices that can store multi-bit data representing at least two bits of information in a single memory cell. It is actively progressed by.

FIG. 1 shows the relationship between each multi-bit data state, the distribution of corresponding threshold voltages, and the word line voltage applied during a read operation when storing multi-bit data (for example, two bits) in one memory cell. Drawing. FIG. 2 is a diagram illustrating a level change of each word line voltage and each detection time point during a data read operation.

In FIG. 1, the threshold voltage Vth0 corresponds to the state of "0" of the 2-bit data, the threshold voltage Vth1 corresponds to the state of "1", and the threshold voltage Vth3 is "10". Corresponds to the state of and the threshold voltage Vth4 corresponds to the state of " 11 ". When reading data stored in any memory cell, as shown in FIG. 2, a word line connected to any memory cell is first driven with a first word line voltage WL0, and then a current is passed through any memory cell. Is passed by a sense amplifier circuit (not shown). Then, as described above, the second word line voltage WL1 and the third word line voltage WL3 are sequentially applied, and then whether the current flows through the arbitrary memory cell is read. Finally, the results read in three times are logically combined to read the multi-bit data stored in the arbitrary memory cell.

Accurately controlling the word line voltage to be changed at each sensing step to the required level is very important in a semiconductor memory device storing multi-bit data. For example, in a device operating at a low supply voltage, a high voltage generator circuit must be used internally to generate a desired level of word line voltage, and a technique for obtaining a desired level of word line voltage using a voltage source provided therefrom is provided. Required.

3 is a block diagram illustrating a word line voltage control structure of a semiconductor memory device capable of storing multi-bit data. The semiconductor memory device is connected to a memory cell array 10, one side thereof and includes a block decoder 11 and a word line pre-decoder 14 for decoding the memory cell array 10. Since the memory cell array 10 and the block decoder 11 are well known to those skilled in the art, the description thereof is omitted here. In addition, when the memory device operates at a low power supply voltage (low VCC), the word line voltage generator 13 receives a high voltage VPP or a lower level power supply voltage VCC provided from the word line voltage source 12. Generate a word line voltage (VP) at the required level.

Since a circuit that changes during a read operation in a memory device storing multi-level data, i.e., generates a voltage applied to a word line, is of interest in the present invention, a detailed circuit thereof is described below. 4 is a circuit diagram illustrating a word line voltage generation circuit according to the prior art. The conventional word line voltage generation circuit shown in FIG. 4 is published in USP No. 5,457,650, "APPARATUS AND METHOD FOR READING MULTI-LEVEL DATA STORED IN A SEMICONDUCTOR MEMORY."

Referring to FIG. 4, the word line voltage generation circuit controls the word line voltage VP to the voltages Vth1-Vth, Vth2-Vth and Vth3-Vth at each sensing step. Here, the voltages Vth1, Vth2, and Vth3 represent threshold voltages of the dummy cells M01, M10, and M11, respectively. And, the voltage Vth represents the threshold voltages of the NMOS transistors 41-43.

The above-mentioned conventional word line voltage generation circuit is designed to lower the word line voltage by a level higher by the resistor RM44 when the word line voltage VP which changes in each sensing step becomes high. However, when the word line voltage VP becomes lower than the desired level of voltage, the dropped word line voltage cannot be increased. That is, the dress voltages Vth1, Vth2 and Vth3 are the dress voltages corresponding to the possible data states of a memory cell capable of storing multi-bit data, respectively, and the voltage Vth is the NMOS transistors. This is because it is a fixed threshold voltage of (41)-(43). In addition, the word line voltage change can be further deepened if each of the threshold voltages of the NMOS transistors 41-43 is changed by a process change.

Also, when the source voltages of the NMOS transistors 41-43 are changed, for example, when the word line voltage VP is varied, each of its threshold voltages is changed due to a body effect. As a result, since the change amount of the threshold voltage of each of the transistors 41-43 is different due to the above effect, the difference between the threshold voltage of the memory cell and the word line voltage, that is, the gate-source voltage Vgs, It is different at the detection stage. Therefore, the cell current flowing through any memory cell is different in each sensing step, and serves as a cause of reducing the sensing margin during the read operation.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of preventing the cell current from being changed by the change in the threshold voltage of the memory cell, which stores the multi-bit data, which can be caused by the process change. .

Another object of the present invention is to provide a semiconductor memory device having a word line voltage generating circuit which accurately and consistently generates a word line voltage of a level required during reading of multi-bit data.

Another object of the present invention is to provide a semiconductor memory device capable of storing multi-bit data with improved reliability.

1 shows a threshold voltage distribution of a memory cell storing multi-bit data;

2 is a view illustrating a level change and a detection time point of a word line voltage during a data read operation;

3 is a block diagram showing a configuration of a semiconductor memory device capable of storing multi-bit data;

4 is a circuit diagram showing a word line voltage generation circuit according to the prior art;

5 is a circuit diagram showing a word line voltage generating circuit of a semiconductor memory device according to the present invention;

6 illustrates a read operation timing in accordance with the present invention;

7 is a circuit diagram illustrating a word line voltage generation circuit of a semiconductor memory device according to the present invention.

* Explanation of symbols for the main parts of the drawings

10 memory cell array 11 block decoder

12 word line voltage source 13 word line voltage generator

14: word line pre-decoder 55, 65, 66: voltage generation circuit

62: reference voltage generation circuit

(Configuration)

According to one aspect of the present invention proposed to achieve the above object, a plurality of memory cells each having a gate, arranged in rows and columns for storing multi-bit data; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A voltage coupled to the row decoder for sequentially generating a plurality of different voltages when data is read from the memory cells during a data read operation and for sequentially applying the other voltages to the word line selected by the row decoder Means for including; The voltage generating means may be configured when the plurality of different dress voltages corresponding to data states that can be stored by the memory cells are varied or when the other voltages deviate from levels corresponding to the plurality of different dress voltages. Allow voltages to automatically adjust to corresponding levels.

In this embodiment, the multi-bit data represents at least two bits of information.

In this embodiment, the levels corresponding to the different voltages respectively correspond to the levels between the different threshold voltages corresponding to the storeable data states.

In this embodiment, the voltage generating means comprises: a plurality of word line voltage generating circuits for generating the plurality of different voltages, respectively; A reference voltage generator circuit for providing a reference voltage of a constant level irrespective of a power supply voltage to the plurality of word line voltage generator circuits; Each word line voltage generation circuit comprises: a) the plurality of current paths and gates having one side connected to ground and the other side connected to the reference voltage generator circuit corresponding to a plurality of possible states representing multi-bit data; A reference cell set to one threshold voltage of one of the other threshold voltages; b) a voltage application circuit connected to the other side of the current path of the reference cell, for applying a corresponding one of the plurality of different voltages to the row decoder; c) an off-set voltage connected between the row decoder and the gate of the reference cell, which receives a voltage applied to the row decoder and corresponds to a difference between the threshold voltage of the reference cell and the voltage applied to the row decoder An off-set voltage application circuit for applying (Off-set voltage) to the gate of the reference cell; The voltage application circuit senses a state of the reference cell and applies or cuts a voltage to the row decoder according to the detected state.

In this embodiment, the voltage generating means is connected to a node to which each of the word line voltage generating circuits and the row decoder are connected, and initialization means for initializing a voltage applied to the row decoder before a read operation is performed. It additionally includes.

In this embodiment, the initialization means includes a switch for switching the connection node with the ground in response to a control signal activated during a read operation.

In this embodiment, the switch consists of an NMOS transistor having a current path formed between the connection node and the ground and a gate to which the control signal is applied.

In this embodiment, each word line voltage generation circuit additionally includes initialization means for initializing a gate voltage of the reference cell.

In this embodiment, the initialization means includes a switch for switching the gate of the reference cell with the ground in response to a control signal activated during a read operation.

In this embodiment, the switch is composed of an NMOS transistor having a current path formed between the gate of the reference cell and the ground and a gate to which the control signal STG is applied.

In this embodiment, the off-set voltage application circuit includes a capacitor having one terminal connected to the row decoder and the other terminal connected to the gate of the reference cell.

In this embodiment, each word line voltage generating circuit additionally includes a PMOS transistor having a gate connected to the ground and a current path formed between the reference voltage generating circuit and the other side of the reference cell; The current driving capability of the PMOS transistor is less than that of the reference cell.

According to another aspect of the invention, there is provided a memory device comprising: a plurality of memory cells each having a gate and arranged in rows and columns for storing multi-bit data representing at least two bits of information; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A plurality of reference cells connected to the row decoder and set to a plurality of different threshold voltages, corresponding to and corresponding to the threshold voltages of the reference cells when data is read from the memory cells during a data read operation; Voltage generating means for sequentially generating a plurality of different word line voltages having a higher level and sequentially applying the other word line voltages to the word line selected by the row decoder; The voltage generating means may be configured when the plurality of dress voltages corresponding to data states that can be stored by each of the memory cells are varied or the other word line voltages are out of levels corresponding to the plurality of other dress voltages. Allow other voltages to be automatically adjusted to corresponding levels.

In this embodiment, each memory cell has one of a plurality of different threshold voltages corresponding to a plurality of possible states representing multi-bit data, wherein the levels of each word line voltage are in the respective data states. Correspond to the levels between the corresponding threshold voltages.

According to still another aspect of the present invention, there is provided an apparatus, comprising: a plurality of memory cells each having a gate and arranged in rows and columns for storing multi-bit data representing at least two bits of information; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A plurality of word line voltage generation circuits connected to the row decoder for respectively generating the plurality of different voltages, and for providing a reference level of a constant level irrespective of a power supply voltage to the plurality of word line voltage generation circuits. A voltage generating means comprising a reference voltage generating circuit; Each word line voltage generation circuit comprises: a) the plurality of current paths and gates having one side connected to ground and the other side connected to the reference voltage generator circuit corresponding to a plurality of possible states representing multi-bit data; A reference cell set to one threshold voltage of one of the other threshold voltages; b) a voltage application circuit connected to the other side of the current path of the reference cell, for applying a voltage to the row decoder; c) a word line voltage connected between the row decoder and the gate of the reference cell and receiving a word line voltage applied to the row decoder to obtain an off-set voltage corresponding to the difference between the reference voltage of the reference cell and the word line voltage. An off-set voltage application circuit applied to the gate of the reference cell; The voltage application circuit senses a state of the reference cell and applies or cuts a voltage to the row decoder according to the detected state.

In this embodiment, the voltage generating means is connected to a node to which each word line voltage generating circuit and the row decoder are connected, and further includes initialization means for initializing a word line voltage supplied to the row decoder. do.

In this embodiment, the initialization means includes a switch for switching the connection node with the ground in response to a control signal activated during a read operation.

In this embodiment, the switch consists of an NMOS transistor having a current path formed between the connection node and the ground and a gate to which the control signal is applied.

In this embodiment, each word line voltage generation circuit additionally includes initialization means for initializing a gate voltage of the reference cell.

In this embodiment, the initialization means includes a switch for switching the gate of the reference cell with the ground in response to a control signal activated during a read operation.

In this embodiment, the switch is composed of an NMOS transistor having a current path formed between the gate of the reference cell and the ground and a gate to which the control signal is applied.

In this embodiment, each word line voltage generating circuit additionally includes a PMOS transistor having a gate connected to the ground and a current path formed between the reference voltage generating circuit and the other side of the reference cell; The current driving capability of the PMOS transistor is less than that of the reference cell.

In this embodiment, the voltage application circuit comprises: a first power supply terminal for receiving a power supply voltage or a higher voltage; A second power supply terminal for receiving a ground voltage; A current mirror connected to said first power supply terminal, said current mirror having a feedback terminal and an output terminal connected to said row decoder; A PMOS transistor having a current path formed between the first power supply terminal and the feedback terminal and a gate controlled by a read activation signal; A first NMOS transistor having a source, a drain and a gate, the drain connected to the feedback terminal, and a gate connected to one side of the reference cell; And a second NMOS transistor having a current path formed between the source of the first NMOS transistor and the second power supply terminal and a gate controlled by the read activation signal.

In this embodiment, the off-set voltage application circuit includes a capacitor having one terminal connected to the row decoder and the other terminal connected to the gate of the reference cell.

(Action)

According to such an apparatus, even when the threshold voltage of a memory cell is changed due to a process change, a word line voltage of a desired level can be automatically generated.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 5 and 6.

Referring to FIG. 5, the novel semiconductor memory device of the present invention provides a word line voltage generator circuit 13, wherein the word line voltage generator circuit 13 changes the threshold voltage of the memory cell due to process variations. When the word line voltage VP is changed, the changed word line voltage is automatically readjusted to the word line voltage VP of the desired level. Therefore, the cell current may be prevented from changing as the threshold voltage of the memory cell changes due to the process change, thereby preventing the reliability of the read fail from deteriorating.

Referring back to FIG. 5, the semiconductor memory device according to the present invention includes a word line voltage generator circuit 13. Although not shown, the semiconductor memory device of the present invention includes a row decoder including the memory cell array 10 shown in FIG. 3, a block decoder 11 for word line selection, and a word line pre-decoder 14. In addition, having is evident to those who have acquired common knowledge in this field.

The word line voltage generator circuit 13 according to the invention comprises three voltage generator circuits 50, 65 and 66 and one reference voltage generator circuit 62. The reference voltage generator circuit 62 generates the reference voltage Vivcc of a constant level (eg, 2V) regardless of the power supply voltage VCC and converts the reference voltage Vivcc into the three voltage generator circuits 50. ), 65 and 66, respectively. Each of the voltage generating circuits 50, 65, and 66 receives a power supply voltage VCC or a high voltage VPP from the word line voltage source 12 of Fig. 3 as a power supply voltage. Since the internal voltage generator circuit 62 is well known to those who have acquired the general knowledge in this field, the description thereof is omitted here.

Since the voltage generating circuits 50, 65, and 66 of the present invention have the same configuration and function, one voltage generating circuit 50 is described below, and other circuits 65 and 66 are described. In the drawings, the same reference numerals are given together for the components having the same function as the components of the voltage generating circuit 50.

In FIG. 5, voltage generation circuit 50 includes four PMOS transistors 51-54, three NMOS transistors 56-58, one capacitor 60, and one reference cell. cell) M00, wherein the PMOS transistors 52 and 53 are configured as current mirrors.

The signal NO_ACT1 is an active high pulse that informs the first sensing section during the read operation, and becomes a high level in the first sensing step. The signal STG is a signal informing of a read operation and is a signal transitioned to a low level during the read operation. And, the reference cell M00 is " 0 " out of the threshold voltages (e.g., four threshold voltages in the case of representing 2-bit information) corresponding to possible data states of a memory cell capable of storing multi-bit data. Has a threshold voltage Vth0 corresponding to the "state (see FIG. 1). On the other hand, the reference cells M01 and M10 provided to the voltage generating circuits 65 and 66 are respectively the threshold voltages Vth1 and Vth2 corresponding to the "1" and "10" states, respectively. Has

The source of the PMOS transistor 51 is connected to a power supply terminal 101 to which a power supply voltage VCC or a high voltage VP is applied and its gate is controlled to the signal NO_ACT1. The source of the PMOS transistor 52 is connected to the power supply terminal 101 and its drain is connected in common with the drain of the transistor 51. Current paths of the NMOS transistors 56 and 57 are formed in series at the ground terminal 102 for accepting the common drain connection point 5C and ground voltage VSS of the transistors 51 and 52. It is. The gates of the transistors 56 and 57 are respectively controlled to the reference voltage generator circuit 62 and the signal NO_ACT1 through the PMOS transistor 54 with the gate grounded.

The gate of the PMOS transistor 53 is connected in common 5D with the gate of the transistor 52, the source of which is connected to the power supply terminal 101 and its source to output the word line voltage VP. Is connected to the output terminal 103. In addition, the common gate connection point 5D is connected to the common drain connection point 5C. The current path of the reference cell M00 is formed between the gate of the NMOS transistor 56 and the PMOS transistor 54, that is, the connection point 5A and the ground terminal 102, the gate of which is It is connected to the output terminal 103 with a capacitor 60 inserted between it. The current path of the NMOS transistor 58 is formed between the gate of the reference cell M00 and the ground terminal 102, the gate of which is controlled to the signal STG.

In Fig. 5, the current path of the NMOS transistor 59 controlled by the signal STG is connected to the output terminal 103 and to initialize the output terminal 103 of the word line voltage VP after the read operation is completed. It is formed between the ground terminals 102.

6 is a view illustrating a read operation timing according to the present invention. Hereinafter, the operation according to the present invention will be described based on FIGS. 5 and 6.

First, when the word line voltage generation circuit 13 is deactivated, that is, the signals NO_ACT1, NO_ACT2 and NO_ACT3 and the signal STG are at the low level and the high level, respectively. When each of the voltage generating circuits 50, 65, and 66 transistors 51, 54, and 58 are conductive, the transistor 57 is nonconductive. Accordingly, the potential of the common gate connection point 5D, that is, the common drain connection point 5C, is charged to VCC or VPP through the transistor 51, as a result of the PMOS transistors 52 and ( 53) is not conductive. The gate of the reference cells M00 / M01 / M10 is initialized to the low level, that is, the ground voltage VSS by the conductive NMOS transistor 58. At this time, the NMOS transistor 57 is non-conductive in order to prevent the DC current of the ground terminal 102 from flowing from the common drain / gate connection point 5C / 5D.

Then, when the read operation is performed, the signal NO_ACT1 transitions from the low level to the high level and the signal STG transitions from the high level to the low level. In other words, the voltage generating circuit 50 is activated. At this time, as shown in FIG. 6, the signals NO_ACT2 and NO_ACT3 are maintained at a low level. Accordingly, voltage generation circuits 65 and 66 are deactivated and NMOS transistors 58 and 59 are nonconductive.

In the voltage generation circuit 50 of FIG. 5, because the signal NO_ACT1 is at a high level, the PMOS transistor 51 of the transistors 51 and 57 controlled thereto is non-conductive and the NMOS transistor 57 is The NMOS transistor 56 controlled by the reference voltage generator circuit 62 is also conducted. The PMOS transistor 53 is conductive because the potential of the common drain / gate junction 5C / 5D of the current mirror is discharged to ground potential VSS through the turned-on (conducted) transistors 56 and 57. do. As a result, the potential of the output terminal 103 becomes high to the word line voltage VP (W0 in FIG. 6) of a desired level.

Subsequently, while the word line voltage VP is boosted to the required level, the gate potential of the reference cell M00 is boosted by the capacitor 60. That is, the voltage according to the coupling ratio of the gate capacitor and the capacitor 60 of the reference cell M00 is applied to the gate of the reference cell M00. The voltage applied to the gate of the reference cell M00 may be represented by Equation 1 below.

[Equation 1]

In Equation 1, the symbol Ccap is the capacitor capacity of the capacitor 60, the symbol Ccel represents the gate capacitor capacity of the reference cell M00, and the symbol VP represents the word line voltage.

Then, when the word line voltage VP becomes the voltage WL0 of a desired level, the gate voltage Vg becomes its threshold voltage Vth0 by the capacitor coupling of the capacitor 60 and the reference cell M00. do. Due to the above operation, the reference cell M00 is gradually conducted, and the potential of the connection point 5A, that is, the gate of the NMOS transistor 56 is discharged to the ground terminal 102. Subsequently, the NMOS transistor 56 is non-conductive, and as a result, the potential of the connection point 5C / 5D is determined by the PMOS transistor 52 (VCC / VPP-Vtp) (where Vtp is the threshold voltage of the PMOS transistor. To rise). That is, the PMOS transistor 53 is nonconductive. Here, it should be noted that the current driving capability of the PMOS transistor 54 should be considerably less than that flowing through the reference cell M00.

By the above method, the word line voltage VP is maintained at the voltage Vth0 + Vg to which the gate voltage Vg is added to the threshold voltage Vth0 of the reference cell M00. Here, the voltage Vg represents the off-set voltage of the threshold voltage Vth0 of the reference cell M00 and the word line voltage VP, which is the gate-source voltage of the reference cell M00 ( Vgs). The threshold voltage Vth of the reference cell M00 is sensed by a current mirror, consisting of PMOS transistors 52 and 53, through the transistor 56, and the state of the reference cell M00 (eg, ON / OFF state) to supply or cut off the current to the output terminal (103).

Since the threshold voltage Vth0 of the reference cell M00 is set by the same process conditions as that of the memory cells of the memory cell array 10, if the threshold voltage of the corresponding memory cell is different from the process change, Is changed to that of the reference cell M00. Therefore, when the threshold voltage of the memory cell is changed by a process change, since the reference cell is also varied by the variable threshold voltage, the word line voltage VP is equal to the error voltage, that is, the gate voltage of the reference cell M00. Are readjusted automatically.

Therefore, the word line voltage generation circuit 13 of the present invention varies the word line voltage VP so that the gate-source voltage of the cell is kept constant even if the threshold voltage of the memory cell is changed by the process change. As a result, the read current can be prevented because the cell current remains constant even when the threshold voltage is changed due to a process change. Obviously, even if the word line voltage VP varies, it is obvious that the word line voltage generation circuit according to the present invention automatically readjusts to the original level. Thereafter, the word lines voltage VP may be generated in the second and third sensing sections in the same manner as the aforementioned first sensing section.

FIG. 7 is a circuit diagram showing the configuration of a word line voltage generation circuit of the semiconductor memory device according to the present invention. Since the word line voltage is generated in the same manner as the word line voltage generation circuit of FIG. 5, a detailed description thereof will be omitted.

As described above, in a semiconductor memory device storing multi-bit data, a change in the cell's dress voltage caused by a process change is caused, and a change in cell current and data caused by the change in the dress voltage is caused. Read fail can be prevented. In addition, even if the word line voltage changes, it is automatically readjusted to the original level.

Claims (24)

A plurality of memory cells each having a gate and arranged in rows and columns for storing multi-bit data; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A word line coupled to the row decoder for sequentially generating a plurality of different voltages when data is read from the memory cells during a data read operation and for sequentially applying the other voltages to the word line selected by the row decoder A voltage generating means; The word line voltage generating means is adapted when the plurality of different dress voltages corresponding to data states that can be stored by the respective memory cells are varied or the other voltages deviate from levels corresponding to the plurality of different dress voltages. And cause the other voltages to be automatically adjusted to corresponding levels. The method of claim 1, And the multi-bit data represents at least two bits of information. The method of claim 2, And levels corresponding to the different voltages respectively correspond to levels between the different threshold voltages corresponding to the storeable data states. The method of claim 1, The word line voltage generating means includes a plurality of voltage generating circuits for generating the plurality of different voltages, respectively; A reference voltage generator circuit for providing a reference voltage of a constant level irrespective of a power supply voltage to the plurality of voltage generator circuits; Each voltage generator circuit, a) one of said plurality of different threshold voltages corresponding to a plurality of possible states representing multi-bit data, one side having a current path and a gate connected to ground and the other connected to said reference voltage generating circuit; A reference cell set to the threshold voltage; b) a voltage application circuit connected to the other side of the current path of the reference cell, for applying a corresponding one of the plurality of different voltages to the row decoder; c) an off-set voltage connected between the row decoder and the gate of the reference cell, which receives a voltage applied to the row decoder and corresponds to a difference between the threshold voltage of the reference cell and the voltage applied to the row decoder An off-set voltage application circuit for applying (Off-set voltage) to the gate of the reference cell; And the voltage applying circuit senses a state of the reference cell and applies or cuts a voltage to the row decoder according to the detected state. The method of claim 4, wherein The word line voltage generating means is connected to a node to which each of the word line voltage generating circuits and the row decoder are connected, and further comprising initialization means for initializing a voltage applied to the row decoder before a read operation is performed. A semiconductor memory device comprising. The method of claim 5, And the initialization means includes a switch for switching the connection node with the ground in response to a control signal activated during a read operation. The method of claim 6, And the switch comprises an NMOS transistor having a current path formed between the connection node and the ground and a gate to which the control signal (STG) is applied. The method of claim 4, wherein Each voltage generating circuit further comprises initialization means for initializing a gate voltage of the reference cell. The method of claim 8, And the initialization means includes a switch for switching the gate of the reference cell with the ground in response to a control signal activated during a read operation. The method of claim 9, And the switch comprises an NMOS transistor having a current path formed between the gate of the reference cell and the ground and a gate to which the control signal (STG) is applied. The method of claim 4, wherein And the off-set voltage applying circuit includes a capacitor having one terminal connected to the row decoder and the other terminal connected to a gate of the reference cell. The method of claim 4, wherein Each voltage generation circuit additionally includes a PMOS transistor having a gate connected to the ground and a current path formed between the reference voltage generator circuit and the other side of the reference cell; And a current driving capability of the PMOS transistor is less than that of the reference cell. A plurality of memory cells each having a gate and arranged in rows and columns for storing multi-bit data representing at least two bits of information; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A plurality of reference cells connected to the row decoder and set to a plurality of different threshold voltages, corresponding to and corresponding to the threshold voltages of the reference cells when data is read from the memory cells during a data read operation; Word line voltage generating means for sequentially generating a plurality of different word line voltages having a higher level and sequentially applying the other word line voltages to the word line selected by the row decoder; The voltage generating means may be configured when the plurality of dress voltages corresponding to data states that can be stored by each of the memory cells are varied or the other word line voltages are out of levels corresponding to the plurality of other dress voltages. A semiconductor memory device, in which different voltages are automatically adjusted [voluntarily] to corresponding levels. The method of claim 13, Wherein each memory cell has one of a plurality of different threshold voltages corresponding to a plurality of possible states representing multi-bit data, wherein the levels of each word line voltage correspond to the threshold voltages corresponding to the respective data states. A semiconductor memory device corresponding to the levels between. A plurality of memory cells each having a gate and arranged in rows and columns for storing multi-bit data representing at least two bits of information; A plurality of word lines connected to gates of the memory cells; A row decoder connected to said word lines, for selecting one of said word lines in accordance with an address signal; A plurality of voltage generating circuits connected to said row decoder, respectively, for generating said plurality of different voltages and a reference voltage generating circuit for providing a reference voltage of a constant level irrespective of a power supply voltage to said plurality of voltage generating circuits; A word line voltage generating means comprising a; Each voltage generator circuit, a) one of said plurality of different threshold voltages corresponding to a plurality of possible states representing multi-bit data, one side having a current path and a gate connected to ground and the other connected to said reference voltage generating circuit; A reference cell set to the threshold voltage; b) a voltage application circuit connected to the other side of the current path of the reference cell, for applying a voltage to the row decoder; c) a word line voltage connected between the row decoder and the gate of the reference cell and receiving a word line voltage applied to the row decoder to obtain an off-set voltage corresponding to the difference between the reference voltage of the reference cell and the word line voltage. An off-set voltage application circuit applied to the gate of the reference cell; And the voltage applying circuit senses a state of the reference cell and applies or cuts a voltage to the row decoder according to the detected state. The method of claim 15, The word line voltage generating means is connected to a node to which each word line voltage generating circuit and the row decoder are connected, and further includes initialization means for initializing a word line voltage supplied to the row decoder. . The method of claim 16, And the initialization means includes a switch for switching the connection node with the ground in response to a control signal activated during a read operation. The method of claim 17, And the switch comprises an NMOS transistor having a current path formed between the connection node and the ground and a gate to which the control signal is applied. The method of claim 15, Each voltage generating circuit further comprises initialization means for initializing a gate voltage of the reference cell. The method of claim 19, And the initialization means includes a switch for switching the gate of the reference cell with the ground in response to a control signal activated during a read operation. The method of claim 20, And the switch comprises an NMOS transistor having a current path formed between the gate of the reference cell and the ground and a gate to which the control signal is applied. The method of claim 15, Each voltage generation circuit additionally includes a PMOS transistor having a gate connected to the ground and a current path formed between the reference voltage generator circuit and the other side of the reference cell; And a current driving capability of the PMOS transistor is less than that of the reference cell. The method of claim 15, The voltage application circuit includes a first power supply terminal for receiving a power supply voltage or a higher voltage; A second power supply terminal for receiving a ground voltage; A current mirror connected to said first power supply terminal, said current mirror having a feedback terminal and an output terminal connected to said row decoder; A PMOS transistor having a current path formed between the first power supply terminal and the feedback terminal and a gate controlled by a read activation signal; A first NMOS transistor having a source, a drain and a gate, the drain connected to the feedback terminal, and a gate connected to one side of the reference cell; And a second NMOS transistor having a current path formed between the source of the first NMOS transistor and the second power supply terminal and a gate controlled by the read activation signal. The method of claim 15, And the off-set voltage applying circuit includes a capacitor having one terminal connected to the row decoder and the other terminal connected to a gate of the reference cell.