KR19990066423A - Reflash Circuit of Semiconductor Memory Device - Google Patents

Abstract

The purpose of the present invention is to provide a refresh circuit of a semiconductor memory device for avoiding repeating a refresh operation at the same address. To achieve the above object, a refresh circuit of a semiconductor memory device may include an address combination generated by an internal address counter. A DRAM for selecting and refreshing a memory cell by using a clock generator, comprising: a clock generator configured to receive a low address detection signal (/ RAS) and generate a clock signal; A control unit, a refresh counter that receives an output signal of the refresh control unit, and gradually increases and outputs an address, and receives a clock signal of the clock generator and outputs an address from the refresh counter and reads and writes Compare the input address To be the address comparing unit, wherein the receiving the control signal of the Lee peuraeswi control unit is configured to include a selection address output for outputting the address stored in the re-peuraeswi counter for the re-transmission counter to peuraeswi.

Description

Reflash Circuit of Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a refresh circuit of a semiconductor memory device for avoiding repeating a refresh operation at the same address.

In general, Dynamic Random Access Memory (DRAM) is currently used in main memory of most computer systems. As the name of Dynamic suggests, DRAM memory cells consist of one capacitor, so if you do not continuously refresh them, the data in the cells will be destroyed.

And DRAM's refresh time is the maximum data holding time to endure without refreshing. For example, if the refresh time is 16ms, it guarantees that the memory cell can hold data for 16ms. In addition, the refresh cycle refers to the number of refresh operations to be performed within a given refresh time. If the refresh time is 16ms, a 4M DRAM that performs 1024 refresh cycles for 16ms means 4096 (for each refresh cycle). This means that 4k) memory cells must be refreshed before all cells are refreshed within the refresh time.

In addition, the refresh rate is divided by the number of refresh cycles. The refresh rate is a time interval between the refresh cycles when the refresh cycles are performed at regular intervals during the refresh time. If this time is reduced, the ratio of operation cycles for accessing the DRAM is reduced, that is, it is not preferable because the re-cycle cycles must be frequently performed.

A method for reducing the number of re-flash cycles during the predetermined re-flash time is under study.

In addition, the refresh operation may be referred to as the sensing operation itself. The reason for this is that as the sensing operation proceeds, the voltage of the bit line and the bit bar line node is amplified. This amplified voltage is rewritten to the storage node of the memory cell through an access transistor connected to the memory cell. At this time, sensing and outputting the amplified voltage to the outside of the DRAM or overwriting the data input from the outside to the bit line and the bit bar line are read and write operations, respectively. It is called a relash operation to perform the sensing operation only, take out, read, and rewrite the stored data before the data of the memory cell is completely destroyed. Therefore, the refresh operation itself may be referred to as the sensing operation itself.

Referring to the accompanying drawings, a reflash circuit of a conventional semiconductor memory device will be described.

1 illustrates a DRAM for selecting an arbitrary memory cell based on a combination of a conventional low address detection signal (RAS address) / column address detection signal (Column Address Strobe (/ CAS)) and an input address A0 to AN. Is a block diagram showing a circuit for reading, writing, and refreshing.

A conventional semiconductor memory device receives a column address detection signal (/ RAS) as shown in FIG. 1 and receives a clock signal for receiving a column address generation signal (/ Row) and a column clock generation unit (1) for generating a column operation clock signal. A column address buffer for generating a column address by combining the low clock generator 2 generating the signal S1 with the clock signal of the column clock generator 1 and receiving the signals of the input addresses A0 to AN. A low address buffer unit 4 which receives the signal of the unit 3, the low clock generator 2, and combines the signals of the input addresses A0 to AN to generate an output signal S2, and the column clock A column decoder 5 which receives a clock signal of the generator 1 and receives a signal of the column address buffer unit 3 and decodes an address in a column direction, and a column clock generator that operates by receiving a / RAS signal ( Low clock that receives clock signal and / CAS signal of 1) A relash control unit for detecting a reflash cycle according to the clock signal S1 of the clock generation unit 2 and outputting a signal S4 for controlling the operation of the low address selection output unit 6 and the retrace counter 8. (7) and the output counter S2 of the low address buffer unit 4 and the control counter S4 of the refresh control unit 7 for cutting off the external input address signal to the refresh counter 8; A low address selection output unit 6 for transmitting the address signal S3 received from the low decoder 9 to the low decoder 9 and a control signal S4 of the refresh control unit 7 to gradually increase the refresh address. A low decoder 9 which receives the flash counter 8 and the control signal S4 of the refresh control unit 7 and decodes the address S5 transmitted from the low address selection output unit 6; Transferring data of the memory cells selected by the row decoder 9 Outputting a signal sensed through one memory cell array unit 10, a sense amplifier 11 for sensing data of a selected memory cell in the selected memory cell array unit 10, and the sense amplifier 11 It is configured to include an output bus.

A reflash operation of the semiconductor memory device having the above-described structure will be described with reference to FIGS. 1 and 2 as follows.

First, the conventional semiconductor memory device first receives the / RAS signal, and the low clock generator 2 repeatedly generates the "high" and "low" signals of S1. As described above, when the refresh operation signal is transmitted to the refresh control unit 7 according to the S1 signal generated from the low clock generator 2, the refresh control unit 7 enters the refresh cycle. That is, the refresh control unit 7 outputs the "low" potential S4. Thereafter, the address of the address M-1 stored in the refresh counter 8 is transmitted to the low decoder 9 through the low address selection output unit 6 during the refresh cycle.

Next, when the refresh cycle ends, i.e., as soon as the refresh control 7 transitions to "high", the output address of the refresh counter 8 transitions to the address of the next M address.

After the read and write operation is continued, when the refresh cycle comes by the combination of / RAS and / CAS, the above operation is repeatedly performed and the low decoder 9 has the low value of the M address next to M-1. The address is output.

At this time, if the low address of M address is in progress during read and write operation, the low address of M address is already re-flashed, which causes the phenomenon of re-lashing.

Subsequently, an operation for resetting the low address of M + 1 address is repeatedly performed through the above process.

The refresh circuit of the semiconductor memory device as described above has the following problems.

The read and write operations of the DRAM have the same effect as the refresh operation. However, after the end of the refresh cycle, the read and write operation of the address of the address to be refreshed occurred in the next refresh cycle.If the refresh address of the next address that was refreshed before the next refresh cycle occurs, the same Since the address of the address of the address is re-twisted twice, the refresh cycle is increased, which reduces the power consumption of the DRAM.

The present invention has been made to solve the above problems, in particular, by preventing the lower address of the same address repeatedly in the read and write operation and the rewrite cycle to prevent the re-flash operation to reduce the number of relash cycles An object of the present invention is to provide a refresh circuit of a semiconductor memory device capable of reducing power consumption.

Another object is to provide a refresh circuit of a semiconductor memory device suitable for increasing the stability of data integrity of a memory cell by reducing the refresh cycle.

1 is a block diagram showing a circuit for reading, writing, and refreshing a conventional DRAM.

2 is a timing diagram of a relash operation of a reflash circuit of a conventional DRAM.

3 is a block diagram illustrating a circuit for reading, writing, and refreshing a DRAM of the present invention.

4 is a configuration diagram of a low address comparison unit of FIG. 3.

5 is a timing diagram of the relash operation of the reflash circuit of the DRAM of the present invention.

Explanation of symbols for the main parts of the drawings

21: column clock generator 22: low clock generator

23: column address buffer section 24: low address buffer section

25: column decoder 26: low address selection output

27: leaflash control unit 28: leaflash counter

29: low address comparison unit 30: low decoder

31: memory cell array unit 32: sense amplifier

In the DRAM of the semiconductor memory device of the present invention for achieving the above object, a low address detection signal (/ RAS) in a DRAM for selecting and refreshing a memory cell by an address combination generated by an internal address counter A clock generator for receiving a clock signal, a refresh controller for adjusting a refresh condition in response to the clock signal of the clock generator, and a refresh counter for incrementally increasing the address by receiving the output signal of the refresh controller and outputting the clock signal; An address comparison unit which receives a clock signal of the clock generation unit, compares an address outputted from the refresh counter with an address input for read and write operations, and transmits the result to the refresh counter; The leaflash counter receives the control signal from the leaflash control unit. It characterized in that the configuration comprises an address selection output for outputting the stored address.

The reflash circuit of the semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a circuit for reading, writing, and refreshing a DRAM of the present invention, FIG. 4 is a diagram illustrating a low address comparison unit of FIG. 3, and FIG. 5 is a refresh circuit of the DRAM of the present invention. Is a timing diagram of the refresh operation.

FIG. 3 illustrates a method of selecting an arbitrary memory cell by a combination of a low address detection signal (RAS address) / column address column detection signal (Column Address Strobe (/ CAS)) and an input address A0 to AN according to the present invention. This is a block diagram showing a circuit for reading, writing, and refreshing DRAM.

3 and 4, the column clock generator 21 receives the column address detection signal / RAS and generates a column operation clock signal, and receives the low address detection signal / Row. A column clock is generated by combining the low clock generator 22 generating the low operation clock signal S1 and the clock signals of the column clock generator 21 and the signals of the input addresses A0 to AN. A low address buffer unit 24 which receives the clock signal S1 of the column address buffer unit 23 and the low clock generation unit 22 and combines the signals of the input addresses A0 to AN to generate the S2 signal; The column decoder 25 receiving the clock signal of the column clock generator 21 and receiving the signal of the column address buffer unit 23 and decoding the address in the column direction, and the clock signal of the column clock generator 21. And a refresh cycle in response to the clock signal S1 of the low clock generator 22 The control unit 27 generates a control signal S4 for controlling the operation of the low address selection output unit 26 by detecting a signal, and an output signal S2 of the low address buffer unit 24 and the re-receiving unit. The low address selection output unit 26 receives the control signal S4 of the flash control unit 27 to block the external input address signal and transmits the address signal S3 received from the refresh counter 28 to the low decoder 30. ) And an address signal output by the external address S6 and the refresh counter 28 received through the low address selection output unit 26 after receiving the clock signal S1 of the low clock generation unit 22. A low address comparison unit 29 and an output signal S5 of the low address comparison unit 29 that adjust the operation of the leaf counter 28 by comparing (S3) are gradually increased. A refresh counter 28 and the row A row decoder 30 for decoding the address S6 transmitted from the dress selection output unit 26, a memory cell array unit 31 for transmitting data of the memory cell selected by the row decoder 30, and And a sense amplifier 32 for sensing data of the selected memory cell in the memory cell array unit 31 and an output bus for outputting a signal sensed through the sense amplifier 32.

At this time, the inside of the low address comparator 29 has an external address signal S6 of N + 1 bits output from the low address select output unit 26 and the address signal of the refresh counter 28 of N + 1 bits. Compares S3) bit by bit and reads and writes a plurality of exclusive-OR gates that output “high” when the two signals are different from each other, and compares and outputs signals through the plurality of beta-o gates. The operation control signal, that is, the non-gate is configured to output the OR of the signal (S1) output from the low clock generator 22.

The re-flash operation of the re-flash circuit of the semiconductor memory device of the present invention having the above configuration will be described below with reference to FIGS. 3, 4, and 5.

First, the re-flash circuit of the semiconductor memory device of the present invention first receives the / RAS signal, and the "high" and "low" signals of S1 are repeatedly generated from the low clock generator 22. At this time, a signal ("low signal") for the low clock generator 22 to refresh is generated. Upon receiving this signal, the refresh control unit 27 enters the refresh cycle. That is, when the reflash control unit 27 outputs the "low" potential to re-flash, it enters the re-flash cycle. When the leaf lash control unit 27 indicates the "low" potential, the low address selection output unit 26 transmits the M-1 address address stored in the leaf lash counter 28 to the low decoder 30. At this time, since the address S6 of the M-1 address transmitted to the low decoder 30 and the address S3 of the M-1 address generated from the refresh counter 28 are the same, the output signal of the low address comparison unit 29 is the same. S5 transitions to the "low" potential. After that, the low clock generation unit 22 transitions to a high potential, and thus the end of the refresh cycle is terminated. As a result, the control signal S4 of the refresh control unit 27 and the output signal S5 of the low address comparison unit 29 are terminated. Also transition to high potential.

As soon as the output signal S5 of the low address comparison unit 29 transitions to high potential, the output address S3 of the refresh counter 28 transitions to the address M, which is the next address.

Subsequently, the read and write operations are continuously performed, and the low address comparison unit 29 performs the address S3 of the shifted M address of the refresh counter 28 and the low address select output unit 26 selected during the read and write operations. After continuously comparing the output addresses S6, as shown in FIG. 5, when the address of the same M address is inputted, the state transitions to the "low" potential. As such, when the low address comparison unit 29 transitions to the "low" potential, and the S1 signal of the low clock generation unit 22 subsequently transitions to the "high" potential, the low-lash comparison unit 27 and the low address comparison unit ( 29) Transition to the "high" potential. As such, when the low address comparison section 29 transitions to the "high" potential, the output address S3 of the refresh counter 28 transitions to the next M + 1 address.

In this way, the address is not re-flashed at M address. If it enters the refresh cycle, it is re-flashed at M + 1 address. Thereafter, the same operation is repeated.

The reflash circuit of the semiconductor memory device of the present invention as described above has the following effects.

First, if the read and write operation is performed at address M during the read and write operation after the end of the refresh cycle at the address of address M-1, the address of address M + 1, which is the address after address M in the next refresh cycle, is performed. By proceeding with the refresh at, it is possible to prevent unnecessary repeated refresh operations from occurring at the same address. Therefore, the power consumption of the DRAM can be reduced.

Second, since the re-flash cycle is reduced for each memory cell by preventing the re-flash operation repeatedly occurring at the address of the same address, it is possible to increase the data storage safety of the memory cell.

Claims (3)

In a DRAM for selecting and refreshing a memory cell based on an address combination generated by an internal address counter, A clock generator for receiving a low address detection signal (/ RAS) and generating a clock signal; A refresh control unit for controlling a refresh condition based on the clock signal of the clock generation unit; A refresh counter unit for receiving an output signal from the refresh control unit and gradually increasing an address and outputting the address; An address comparison unit which receives a clock signal of the clock generation unit, compares an address output from the refresh counter with an address input for read and write operations, and transmits the result to the refresh counter; And an address select output unit configured to receive an adjustment signal of the refresh control unit and output an address stored in the refresh counter. The semiconductor memory device of claim 1, wherein the address comparison unit adjusts the operation of the refresh counter unit only when an address output for the read and write operations and an address stored in the refresh counter unit are the same. Reflash circuit. 2. The apparatus of claim 1, wherein the address comparison unit comprises a plurality of beta oragates having two inputs, an address output through the address selection output unit and an address stored in the refresh counter unit, for reading and writing operations; And an orifice configured to logically combine an output signal of the beta ora gate and a clock signal of the clock generation unit.