KR19990063935A - 라디오 수신기용 위상 지시형 제어 회로를 가진 혼합 발진기 - Google Patents
라디오 수신기용 위상 지시형 제어 회로를 가진 혼합 발진기 Download PDFInfo
- Publication number
- KR19990063935A KR19990063935A KR1019980702408A KR19980702408A KR19990063935A KR 19990063935 A KR19990063935 A KR 19990063935A KR 1019980702408 A KR1019980702408 A KR 1019980702408A KR 19980702408 A KR19980702408 A KR 19980702408A KR 19990063935 A KR19990063935 A KR 19990063935A
- Authority
- KR
- South Korea
- Prior art keywords
- oscillator
- integrator
- frequency
- circuit
- mixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000012360 testing method Methods 0.000 claims abstract description 9
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
- H03J1/0058—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor provided with channel identification means
- H03J1/0066—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor provided with channel identification means with means for analysing the received signal strength
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
Claims (9)
- 위상 지시형 제어 회로(PLL)를 가진 라디오 수신기용 혼합 발진기 회로에 있어서,위상 판별기(8)의 디지털 또는 디지털화 출력치를 저장하는 적분기(15)와, 적분기 내용을 제어 회로의 전압 제어 발진기(7)용 제어 전압으로 변환시키는 적분기(15)의 후단에 설치된 D/A변환기(16)를 갖는 것을 특징으로 하는 혼합 발진기 회로.
- 제 1 항에 있어서, 설정치를 제어 회로에 미리 부여하는 마이크로 프로세서를 가지며, 마이크로 프로세서(12)는 주파수 변화를 위해 혼합 주파수의 설정치에 할당된 수치를 적분기(15)에 공급하는 것을 특징으로 하는 혼합 발진기.
- 제 2 항에 있어서, 위상 판별기(8)의 디지털화 출력 신호의 수치를 위한 적분기(15)의 제 1 입구 및 혼합 주파수에 할당된 수치를 위한 제 2 입구를 특징으로 하는 혼합 발진기.
- 제 2 항 또는 제 3 항에 있어서, 두 시험 주파수간 교환을 위해 선택적으로 통전될 수 있는, 상이한 수치로 부하될 수 있는 적분기(15, 15a)를 특징으로 하는 혼합 발진기.
- 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 저분해된 위상 판별기의 디지털 출력치를 가지며, 혼합 발진 주파수를 설정치에 반복 접근시키기 위해 감소하는 크기의 수치 및 경우에 따라서는 교환하는 부호를 적분기(15)내에 공급하는 회로(19)가 적분기(15) 앞에 설치되는 것을 특징으로 하는 혼합 발진기 회로.
- 제 1 항 내지 제 5 항 중 어느 한 항에 있어서, 발진기 특성선의 비선형성을 보정하기 위해 전압 제어된 혼합 발진기(7)의 주파수 위치에 대응하여 위상 판별기(8)의 출력치를 변화시키는, 적분기(15) 앞에 설치된 회로(20)를 특징으로 하는 혼합 발진기.
- 제 1 항 내지 제 4 항 중 어느 한 항에 있어서, 적분기(15)의 출구와 D/A변환기(16)의 입구 사이에 있어 역 발진기 특성선의 다항식 계산을 위한 회로(21)를 갖는 것을 특징으로 하는 혼합 발진기.
- 제 1 항 내지 제 7 항 중 어느 한 항에 있어서, 출구가 경우에 따라서는 A/D변환기(23)를 통해서 적분기(15)를 위한 할당된 제어 입력과 연결되는, 라디오 수신기의 MPX 신호 내 등전압 부분을 위한 검출기(22)를 갖는 것을 특징으로 하는 혼합 발진기.
- 제 8 항에 있어서, 위상 판별기가 비교하려는 주파수와의 일치를 표시할 때 개방되는, 검출기(22)의 출구에 있는 게이트 회로(24)를 갖는 것을 특징으로 하는 혼합 발진기 회로.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19548539.4 | 1995-12-23 | ||
DE19548539A DE19548539A1 (de) | 1995-12-23 | 1995-12-23 | Mischoszillator mit einem phasengerasteten Regelkreis für einen Rundfunkempfänger |
PCT/DE1996/001818 WO1997023957A1 (de) | 1995-12-23 | 1996-09-26 | Mischoszillator mit einem phasengerasteten regelkreis für einen rundfunkempfänger |
Publications (1)
Publication Number | Publication Date |
---|---|
KR19990063935A true KR19990063935A (ko) | 1999-07-26 |
Family
ID=7781283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980702408A Abandoned KR19990063935A (ko) | 1995-12-23 | 1996-09-26 | 라디오 수신기용 위상 지시형 제어 회로를 가진 혼합 발진기 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6091943A (ko) |
EP (1) | EP0868784B1 (ko) |
JP (1) | JP2000502235A (ko) |
KR (1) | KR19990063935A (ko) |
DE (2) | DE19548539A1 (ko) |
ES (1) | ES2136446T3 (ko) |
WO (1) | WO1997023957A1 (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010012564A (ko) * | 1998-03-13 | 2001-02-15 | 요트.게.아. 롤페즈 | 다이오드 검파기를 사용한 튜닝 장치 |
US7133485B1 (en) * | 2001-06-25 | 2006-11-07 | Silicon Laboratories Inc. | Feedback system incorporating slow digital switching for glitch-free state changes |
US7436227B2 (en) * | 2003-05-02 | 2008-10-14 | Silicon Laboratories Inc. | Dual loop architecture useful for a programmable clock source and clock multiplier applications |
US7064617B2 (en) | 2003-05-02 | 2006-06-20 | Silicon Laboratories Inc. | Method and apparatus for temperature compensation |
US7288998B2 (en) * | 2003-05-02 | 2007-10-30 | Silicon Laboratories Inc. | Voltage controlled clock synthesizer |
US20050068118A1 (en) * | 2003-09-30 | 2005-03-31 | Silicon Laboratories, Inc. | Reconfigurable terminal |
US7187241B2 (en) * | 2003-05-02 | 2007-03-06 | Silicon Laboratories Inc. | Calibration of oscillator devices |
US7295077B2 (en) * | 2003-05-02 | 2007-11-13 | Silicon Laboratories Inc. | Multi-frequency clock synthesizer |
DE102005035093A1 (de) * | 2005-07-27 | 2007-02-01 | Robert Bosch Gmbh | Rundfunkempfangseinheit |
US7342460B2 (en) * | 2006-01-30 | 2008-03-11 | Silicon Laboratories Inc. | Expanded pull range for a voltage controlled clock synthesizer |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4211975A (en) * | 1978-04-04 | 1980-07-08 | Anritsu Electric Company, Limited | Local signal generation arrangement |
US4270206A (en) * | 1980-02-25 | 1981-05-26 | General Electric Company | Transceiver for phase-shift modulated carrier signals |
US4442412A (en) * | 1981-11-12 | 1984-04-10 | Rca Corporation | Phase locked-loop generator with closed-loop forcing function shaper |
US4628270A (en) * | 1985-04-10 | 1986-12-09 | Harris Corporation | Frequency-agile synchronous demodulator |
FR2596220A1 (fr) * | 1986-03-21 | 1987-09-25 | Portenseigne | Demodulateur de frequence |
DE58909454D1 (de) * | 1989-07-06 | 1995-11-02 | Itt Ind Gmbh Deutsche | Digitale Steuerschaltung für Abstimmsysteme. |
US5023572A (en) * | 1989-12-20 | 1991-06-11 | Westinghouse Electric Corp. | Voltage-controlled oscillator with rapid tuning loop and method for tuning same |
KR0162294B1 (ko) * | 1990-10-31 | 1998-12-01 | 구자홍 | 알디에스의 대체주파수 고속서치 방법 및 장치 |
US5207491A (en) * | 1991-01-31 | 1993-05-04 | Motorola Inc. | Fast-switching frequency synthesizer |
US5384551A (en) * | 1993-02-25 | 1995-01-24 | Delco Electronics Corporation | Fast locking phase locked loop frequency synthesizer |
CA2123477A1 (en) * | 1994-05-12 | 1995-11-13 | Thomas Atkin Denning Riley | Delta-sigma fractional-n frequency synthesizer and frequency discriminator suitable for use therein |
DE19510220A1 (de) * | 1995-03-21 | 1996-09-26 | Blaupunkt Werke Gmbh | Rundfunkempfänger |
US5949281A (en) * | 1996-12-19 | 1999-09-07 | Texas Instruments Incorporated | Self aligning PLL demodulator |
-
1995
- 1995-12-23 DE DE19548539A patent/DE19548539A1/de not_active Withdrawn
-
1996
- 1996-09-26 JP JP09523197A patent/JP2000502235A/ja not_active Abandoned
- 1996-09-26 WO PCT/DE1996/001818 patent/WO1997023957A1/de active IP Right Grant
- 1996-09-26 DE DE59602668T patent/DE59602668D1/de not_active Expired - Lifetime
- 1996-09-26 KR KR1019980702408A patent/KR19990063935A/ko not_active Abandoned
- 1996-09-26 EP EP96945340A patent/EP0868784B1/de not_active Expired - Lifetime
- 1996-09-26 ES ES96945340T patent/ES2136446T3/es not_active Expired - Lifetime
- 1996-12-09 US US09/091,372 patent/US6091943A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6091943A (en) | 2000-07-18 |
JP2000502235A (ja) | 2000-02-22 |
EP0868784A1 (de) | 1998-10-07 |
DE59602668D1 (de) | 1999-09-09 |
ES2136446T3 (es) | 1999-11-16 |
DE19548539A1 (de) | 1997-06-26 |
WO1997023957A1 (de) | 1997-07-03 |
EP0868784B1 (de) | 1999-08-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PA0105 | International application |
Patent event date: 19980402 Patent event code: PA01051R01D Comment text: International Patent Application |
|
PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20010926 Comment text: Request for Examination of Application |
|
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20030529 Patent event code: PE09021S01D |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20031218 |
|
NORF | Unpaid initial registration fee | ||
PC1904 | Unpaid initial registration fee |