KR19990061475A - Interrupt Bus Arbitration in Multiprocessor Systems - Google Patents

Abstract

The present invention relates to an interrupt bus arbitration method for fast arbitration of the use of an interrupt bus in a multiprocessor system of shared memory architecture.

This method of the present invention comprises an interrupt termination priority arbitration step of arranging, if an interrupt arbitration is required, to arbitrate with the highest priority to the interrupt termination message in order to mediate a bus right; A cyclic priority arbitration step of arbitration according to a cyclic priority arbitration protocol after the interrupt termination priority arbitration step is performed; If interrupt arbitration is required, the lowest priority arbitration step of arbitrating according to the lowest priority arbitration protocol to mediate the recipient decision; Performing an interrupt termination message transmission cycle for the interrupt controller winning the arbitration step to transmit an interrupt termination message; Performing a short message transmission cycle by the interrupt controller winning the arbitration step to transmit a short message; And performing a non-focus lowest priority arbitration message cycle for the interrupt controller winning the arbitration step to transmit a non-focus lowest priority arbitration message. have.

Description

Method of arbitrating interrupt bus in multi processor system

TECHNICAL FIELD The present invention relates to a technique for handling interrupts in a multiprocessor system of shared memory architecture, and more particularly, to an interrupt bus arbitration method for arbitration at high speeds.

While the performance of single-processor computers has continued to improve as a result of continued microprocessor performance improvements, eventually relying on multiprocessor computers that use multiple processors simultaneously to dramatically improve computational performance.

A multiprocessor computer is divided into a centralized shared memory structure and a distributed memory structure by a memory structure and a connection method. The shared memory structure is a form in which up to several dozen processors access a single shared memory through a shared bus, and is called a UMA (Uniform Memory Access) structure because the memory access time is uniform. Bus-based shared memory architectures are widely used due to their relatively simple programming model and easy implementation of maintaining cache coherency. In contrast, distributed memory architectures in which each processor node has its own local memory. Depending on the implementation, local memory access is performed at high speed, whereas non-uniform memory access (NUMA) structure takes a long time for remote memory access by other nodes, and NO remote memory access (NORMA) structure that does not allow remote memory access. Divided. In recent years, distributed memory architectures have received new attention, but there is still insufficient support for optimized operating systems.

Meanwhile, in a multiprocessor system based on a bus structure and shared memory, each processor agent shares a bus and a memory, and all data is transferred through the system bus. That is, a multiprocessor system, as shown in FIG. 1, includes a plurality of processor agents (MPU: 2), memory agents (SMB: 3), input / output agents (IOP: 4), and a system on one system bus 1. A control agent (SCM) 5 is connected to exchange data via the system bus 1. In such a multiprocessor system, the system bus 1 is an important factor in determining the performance of a computer.

The system bus is divided into an arbitration bus, a data transfer bus, an interrupt transfer bus, and a utility bus, which are address bus arbitration buses and data buses. It consists of an arbitration bus, which consists of an address bus, a data bus, and a status bus. In addition, the utility bus is the default, the necessary signal to the bus portion as a set of signals added to implement the functions, the bus clock (BCLK ^*) for providing a bus clock to the slot position in order to carry out the functions of the bus Geoslot slot address (GA4..0) ^* for indicating slot address, indicating system failure (SFAIL) signal line for indicating system failure, reset (RST) signal line for system reset, Tx4 .. for JTAG boundary scan option. It consists of a 0 signal line light. The operation of the system bus is roughly divided into the arbitration operation by the arbitration bus, the data transmission operation by the data transmission bus, and the interrupt operation by the interrupt bus. These operations are synchronized by the clock of the system bus.

As such, a multiprocessor system may be configured such that an I / O dedicated processor is dedicated to I / O, or may be configured to dynamically distribute I / O operations to unspecified processors. In a HiPi + bus system, a dedicated IPU is separated from a Unix kernel of shared memory. It is a structure dedicated to I / O work while executing its own mini kernel.

And almost all bus systems, including interrupt transfer buses, must be arbitrated before bus use, ensuring that only one bus agent can use the bus at a time. For example, in the case of the data transmission bus, even arbitration algorithms such as round robin can guarantee fair arbitration regardless of the contents of the transmission data. In contrast, an interrupt bus must be arbitrated based on the importance of the message to be transmitted. Therefore, unlike an data bus that is mediated by a simple agent identifier, the interrupt bus should be arbitrated based on the message type and content.

However, in the conventional interrupt bus, since the arbitration method is a sequential asynchronous comparator method that depends on the dedicated BTL device, the arbitration of the interrupt bus takes a long time.

In other words, the problem with the implementation of the interrupt bus arbitration logic is the limitation of the number of signal lines.The data transmission bus can be arbitrated only by the slot address because the data contents to be transmitted are not related to arbitration. In this case, signal lines for data contents are required. For example, since there are 256 priorities in 8-bit arbitration information, assigning one arbitration request signal line to each priority becomes excessive overhead. In order to solve this problem, a conventional high-speed medium-size computer adopts 8-bit sequential asynchronous comparison by a dedicated BTL device.

However, when adopting a sequential comparison method as in the prior art, there is a problem in that it takes much time for arbitration.

Accordingly, an object of the present invention is to provide an interrupt bus arbitration method in a multiprocessor system capable of improving processing time by reducing arbitration time by a parallel comparison method.

In order to achieve the above object, the present invention provides M processor modules and N input / output modules connected to an interrupt bus, and the processor module includes at least one processor interrupt controller and one input / output interrupt controller is also provided in the input / output module. 11. An equipped multiprocessor system, comprising: an interrupt termination priority arbitration step, if an interrupt arbitration is required, mediating the highest priority to an interrupt termination message to mediate bus usage rights; A cyclic priority arbitration step of arbitration according to a cyclic priority arbitration protocol after the interrupt termination priority arbitration step is performed; If interrupt arbitration is required, the lowest priority arbitration step of arbitrating according to a lowest priority arbitration protocol to mediate a recipient decision; Performing an interrupt termination message transmission cycle for the interrupt controller winning the arbitration step to transmit an interrupt termination message; Performing a short message transmission cycle by the interrupt controller winning the arbitration step to transmit a short message; And performing a non-focus lowest priority arbitration message cycle for the interrupt controller winning the arbitration step to transmit the non-focus lowest priority arbitration message.

1 shows an example of a typical multiprocessor system,

2 is an example showing an interrupt related configuration to which the present invention is applied;

3 is a configuration of an input / output interrupt controller shown in FIG. 2;

4 is a configuration of the processor interrupt controller shown in FIG.

5 is a flowchart illustrating an arbitration method in an interrupt bus according to the present invention.

* Explanation of symbols for main parts of the drawings

210-1 to 210-M: Processor module 211-1 to 211-4: Processor

213-1 to 213-4: processor interrupt controller 215: interrupt bus matching unit

220: interrupt bus

230-1 to 230-N: Memory and I / O module 231: I / O interrupt controller

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an example showing an interrupt related configuration to which the present invention is applied, FIG. 3 is a configuration of an input / output interrupt controller shown in FIG. 2, and FIG. 4 is a configuration of a processor interrupt controller shown in FIG. 2.

Referring to FIG. 2, in the multiprocessor system to which the present invention is applied, M processor modules 210-1 to 210 -M and N memory and input / output modules 230-1 to 230 -N are placed on an interrupt bus 220. Is connected. Each processor module 210-1 to 210 -M has the same configuration, and one processor module 210-1 includes four processors 211-1 to 211-4 and four processor interrupt controllers 213. -1 to 213-4, and one interrupt bus matching section 215. Each memory and the input / output modules 230-1 to 230 -N have the same configuration, and one memory and the input / output module 230-1 includes one input / output interrupt controller 231.

As illustrated in FIG. 3, the input / output interrupt controller 231 includes a version register 31 connected to an internal bus, an arbitration ID register 32, and an input / output interrupt controller ID register. I / O APIC ID Register: 33), I / O Register Select Register: 34, I / O Window Register: 35, I / O Redirection Table (36), Send / Receive It consists of logic (Send / Receive logic: 37).

Each processor interrupt controller 213-1 to 213-4 has the same configuration. One processor interrupt controller 231-1 is connected to an internal bus as illustrated in FIG. 4. Version Register (401), Timer (402), LVT (403), Interrupt Command Register (404), First Register Group (405), EOI Register (EOI Register: 406), Task Priority Reg (407), Priority Regulator (408), Second Register Group (409), S / W Transparent Regs (410), Arbitration ID Register ( Arb ID Register (411), First Processor Priority Reg (412), Send / Receive Logic (413), Second Processor Priority Register (414), Vector Decoder (Vector) Decode: 415). The timer 403 includes a current count register, an initial count register, and a divide config reg, and the first register group 405 includes a remote register. ), An interrupt controller ID register (APIC ID Register), a logical destination register (Logical Destination), and a destination format register (Dest Format Reg).

Referring to FIG. 2, all interrupt controllers are connected to the interrupt bus 220. Processor interrupt controllers 213-1 to 213-4 are present in the processor modules 210-1 to 210-M, one per processor. The I / O interrupt controller 231 is present in the memory and the I / O modules 230-1 to 230-N. When there are a plurality of interrupt controllers in one module, each interrupt controller is connected to the interrupt bus through an interrupt bus matching unit 215, where the victory is preceded by arbitration between the interrupts in the module before the arbitration for use of the interrupt bus. Only one interrupt controller participates in the interrupt bus drive.

In the high speed medium computer to which the present invention configured as described above is applied, the arbitration of the interrupt bus is interrupted by the arbitration step (501, 502, 503, 504) for arbitrating the interrupt bus when the interrupt is generated and the interrupt controller winning the arbitration. The mediation stage is divided into bus transmission stages 505 to 510 that transmit messages through the bus, and the mediation stage is divided into bus license arbitration 502 and 503 for arbitrating bus licenses and receiver decision arbitration 504 for determining receivers. The bus transfer phase is performed by interrupt termination (EOI) message cycle 506, short message cycle 507, non-focus lowest priority arbitration message cycle 508, interrupt acknowledgment cycle 509, interrupt transfer error handling cycle 510 Separated by), each is performed.

Referring to FIG. 5, in step 501 an interrupt is requested by an interrupt controller connected to an interrupt bus. If an interrupt is requested, arbitration is required to obtain control over the interrupt bus, which is divided into bus license arbitration and receiver decision arbitration.

As described above, in the case of an interrupt bus whose content of data to be transmitted affects arbitration, many signal lines are needed to distinguish the arbitration information. Therefore, various methods for displaying the arbitration information while reducing the signal line have been studied. The comparison between the HiPi + bus, a system bus used in a high-speed medium computer, the APIC bus of Intel, and the HiPi ++ bus according to the present invention are shown in Table 1 below. Same as

Bus HiPi + Interrupt Bus Intel APIC Bus HiPi ++ Interrupt Bus Arbitration method Sequential non-air comparison dependent on dedicated BTL devices Sequential Comparison Synchronized to Clock Parallel comparison by one hot party Transfer Arbitration Time 16.5 NHz * 5 clocks (8 bits: time required for final mediation victory signal to settle on backplane) 16.5 MHz * 4 clocks (4-bit: allow up to 16 APICs only) 25 MHz * 2 clocks (16 slot IDs divided into 8 bits each for up to 16 slots allowed) Reception Arbitration Time 16.5 MHz * 15 clocks (5 PPR clocks, 5 interrupts received, 5 slot IDs) 16.5 MHz * 12 clocks (8-bit PPR8 clocks, APIC ID 4 clocks) 25 MHz * 6 clocks (8 bit PPR divided by 4 bits (2 clocks each) 4 clocks, slot ID mediated 2 clocks

In Table 1, the HiPi + bus adopts an 8-bit sequential asynchronous comparison method by a dedicated BTL device. This method loses arbitration when its Nth bit is 0 and 1 is interrupted while driving from the most significant bit sequentially. It is regarded as one and does not participate in arbitration from the first bit. Otherwise, it is considered to have won the Nth bit arbitration and continues to participate in the N-1th bit arbitration. If the 0th bit is not lost in arbitration, it is the final winner.

Intel's Advanced Programmable Interrupt Controller (APIC) bus compares arbitration information sequentially over dozens of clocks, one bit at a time. This method differs in that it is synchronized by the same serial comparison method or clock as the conventional interrupt bus method.

The HiPi ++ interrupt bus according to the present invention adopts a parallel comparison arbitration method based on one-hot encoding, thereby dramatically reducing the arbitration time. For example, suppose that interrupt controller A with arbitration ID = 12 and interrupt controller B with arbitration ID = 7 participate in arbitration. Interrupt controller A drives IBD [7: 0] = 0001 0000 in mediation phase0, 0000 0000 in mediation phase1, and interrupt controller B drives 0000 0000 in mediation phase0 and 1000 0000 in mediation phase1. At this time, since it is shown as 0001 0000 and 1000 0000 on the interrupt bus, all the interrupt controllers on the interrupt bus can know that the interrupt controller with arbitration ID = 12 wins the arbitration.

Referring back to FIG. 5, the interrupt bus arbitration protocol according to the present invention provides for bus license arbitration for interrupt transmission and for determining a receiver in the absence of a focus processor during interruption of a lowest priority message. There is mediation. In addition, the present invention uses one-hot encoding over two clocks for arbitration of up to 16 agents on an 8-bit interrupt bus.

When a request for arbitration to use an interrupt bus occurs, priority is given to the request to send an Interrupt Termination (EOI) message first. In other cases, arbitration is performed according to the rotating priority arbitration protocol (501, 502, 503).

For the cyclic priority arbitration protocol, both the processor interrupt controller of the processor module and the I / O interrupt controller of the memory and the I / O module have unique arbitration IDs. The arbitration ID is initialized based on the slot address and has a value between 0 and 15. Among the interrupt controllers participating in arbitration, the controller with the largest arbitration ID has an interrupt bus license. The arbitration ID is a one-hot encoded value that drives 1 in the corresponding time slot of the arbitration phase. Do not drive. Each time an interrupt transfer period on the interrupt bus is terminated successfully, every interrupt controller on the interrupt bus increments its arbitration ID by one. However, the interrupt controller winning the arbitration sets its arbitration ID to 0, and the interrupt controller whose arbitration ID = 15 sets it to the arbitration ID of the winning controller except when it wins the arbitration. If the interrupt transmission is not successful, the arbitration ID is not changed.

Meanwhile, the lowest priority mediation for receiver determination is to dynamically determine 504 the lowest priority message among the unspecified multiple receiving target agents to receive the interrupt in the lowest priority message interrupt. If there is a focus processor, the processor interrupt controller informs itself of the focus processor in the first transmission response and finishes the arbitration without receiving arbitration. If there is no focus processor, the receiving processor interrupt controllers start the lowest priority arbitration.

The lowest priority arbitration protocol is to run the inverse of the LPAR (lowest priority arbitration register) value of each interrupt controller on the interrupt bus to verify its victory. Since one-hot encoding of 8-bit LPARs requires 256 slots, the 4-bit LPARs are sequentially driven twice in 16 slots (4 clocks in total). At this time, if the winning interrupt controller is not determined, arbitration using the arbitration ID is performed.

In this way, when the arbitration is completed and the winning interrupt controller is determined, the transmission cycle by the interrupt controller is started (505). At this time, the transmission cycle is divided into five types as follows.

Step 506 performs an interrupt termination (EOI) message cycle. Interrupt termination message cycles, after the I / O module sends a level triggered interrupt to the processor module, the remote IRR bit in the corresponding redirection table entry of the I / O interrupt controller is set to block homogeneous interrupts. The interrupt termination (EOI) operation of the processor is transferred to the interrupt termination (EOI) message cycle by its processor interrupt controller and transmitted to the input / output interrupt controller that generated the first interrupt. The I / O interrupt controller allows homogeneous interrupts by clearing the redirection table entry remote IRR bit corresponding to the interrupt vector contained in the interrupt termination (EOI) message. For edge triggered interrupts, the processor interrupt termination (EOI) operation is performed on the processor interrupt controller, but no interrupt termination (EOI) message cycle occurs on the interrupt bus. The interrupt termination (EOI) message does not include a destination because the receiving destination is necessarily an input / output interrupt controller.

In step 507, a short message cycle is performed. The short message is a generic term for all messages except EOI message, non-focus priority mediation message, and remote lead message. It is an interrupt with a predetermined destination. Includes Fixed, NMI, INIT, Reset, ExtINT, lowest priority with focus processor interrupts. NMI, Ext INT messages are only used when the system is in PC AT compatible mode, and other messages are only used in multiprocessor mode. Even if the receiver has a low priority priority arbitration message, if there is a focus processor, the processor interrupt controller indicates that it is the focus processor in the first response and terminates the transmission without further reception arbitration. do.

In step 508, a non-focus lowest priority arbitration message transmission cycle is performed. If the focus lowest priority arbitration message transmission cycle is found to have no focus processor for the lowest priority arbitration message, then the lowest priority arbitration is performed. This message only occurs in multiprocessor mode.

In step 509 an interrupt acknowledgment cycle is performed, which typically occurs on the data transfer bus rather than on the interrupt bus. In multiprocessor mode, interrupt acknowledgments occur during the processor and corresponding processor interrupt control periods and do not appear on the system bus. However, in PC AT compatible mode, an interrupt acknowledgment must occur between the BSP and the 8259A PIC and therefore appear on the HiPi ++ bus.

In step 510, an interrupt transmission error processing cycle is performed, in which the processor interrupt controller generates an interrupt error interrupt when the input / output interrupt transmission result is unsuccessful.

As described above, the input / output module to which the present invention is applied only plays a role of redirecting device interrupts to the processor module, and the actual interrupt processing is structured by the processor module to use a single kernel image, thereby minimizing the operating system porting effort. Interrupt arbitration can be done in a full-encoded manner, which can be quickly processed through parallel comparison.

Claims (1)

In a multi-processor system, M processor modules and N input / output modules are connected on an interrupt bus, the processor module includes at least one processor interrupt controller, and the input / output module includes one input / output interrupt controller. If interrupt arbitration is required, an interrupt termination priority arbitration step of arbitrating with the highest priority to the interrupt termination message to mediate bus usage rights; A cyclic priority arbitration step of arbitration according to a cyclic priority arbitration protocol after the interrupt termination priority arbitration step is performed; If interrupt arbitration is required, the lowest priority arbitration step of arbitrating according to the lowest priority arbitration protocol to mediate the recipient decision; Performing an interrupt termination message transmission cycle for the interrupt controller winning the arbitration step to transmit an interrupt termination message; Performing a short message transmission cycle by the interrupt controller winning the arbitration step to transmit a short message; And And performing a non-focus lowest priority arbitration message cycle for the interrupt controller winning the arbitration step to transmit a non-focus lowest priority arbitration message.