KR19990060655A - Frame Signal Control Method in Cell Bus Structure - Google Patents

Abstract

The present invention provides a switch and multiplexing apparatus using a cell bus, which controls a frame signal generated by a frame signal generator by a bus arbiter, and controls an access request of an access device requiring the occupancy of the cell bus according to the frame signal. The present invention relates to a method of controlling a frame signal in a cell bus structure, in which a frame signal is output every 32 system clocks from the frame signal generator by the bus arbiter. Each 2 bits allocated are used to request access to the cell bus, and the access device with the highest priority is identified according to the access request of the access device, and one bus cycle is allowed for the highest priority access device. Cell data for up to 14 cycles Transmit on the bus or receive cell data on the bus, and then determine the next highest priority access device in 15 cycles to determine the frame signal and GTN, and no other device access requests or current access during the next frame. If the priority of the device being the highest, the same frame signal is continuously generated to transmit or receive cell data to be transmitted next, and then generate a frame signal every 32 system clocks.

Description

Frame Signal Control Method in Cell Bus Structure

The present invention provides a switch and multiplexing apparatus using a cell bus, which controls a frame signal generated by a frame signal generator by a bus arbiter, and controls an access request of an access device requiring the occupancy of the cell bus according to the frame signal. The present invention relates to a frame signal control method in a cell bus structure.

In general, the frame format for transmitting cell data in a cell bus structure is such that 16 words of 32-bit wide are transmitted during 16 system clocks. As shown in FIG. 6, a cycle 10 for allocating cell bus access request signals of 16 devices by 2 bits and header information of cell data for transmission, that is, a cell bus routing header (Cell Bus Routing Header), Tandem Routing Header, Generic Flow Control (GFC), Virtual Path Identifier (VPI), Virtual Channel Identifier (VCI), Payload Type (PT), Cell Loss Priority (CLP) Distinguishing these cycles from 1 to 2 cycles 20, 3 to 14 cycles 30 carrying pure data of cell data, 30, BIP-8 and unused parts and 16 devices Grant Terminal Number (hereinafter referred to as GTN) and GEN It consists of a 15-cycle (40).

As described above, one cell data is transferred from the device occupying the cell bus, which is the transmission path of the cell data, to the cell bus during the 16 system clocks. On the contrary, the access devices occupy the cell bus to access the cell data.

At this time, the number of access devices capable of accessing the cell data on the cell bus by using 32 bits of 0 cycle 10 of the frame format according to the 16 system clock is 16 at maximum.

On the other hand, when 16 or more access devices are used, 32 more bits of 0 cycle 10 are required.

However, as described above, when a plurality of occupation rights are required for cell data on a cell bus, the number of access devices capable of sharing cell buses and transmitting cell data is limited to 16 or less, in particular, using 32 bits more. If more than 16 access devices are used, there is a problem that the transmission capacity of the entire data is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to control the frame signal generator to output a frame signal every 32 system clocks by the bus arbiter, and in particular, to grasp the priority of the bus occupancy of the access device. The present invention provides a method of controlling a frame signal in a cell bus structure in which a control signal is outputted so that a cell bus access request signal of 32 access devices can be received through the same system clock.

1 illustrates a frame format for transmitting cell data in a general cell bus structure;

2 is a diagram illustrating a cell bus structure for applying a frame signal control method according to the present invention;

3 is a cell transmission timing diagram according to a frame signal according to the present invention;

4 is a flowchart illustrating a method of controlling a frame signal in a cell bus structure according to the present invention.

Explanation of symbols for main parts of the drawings

100: bus arbiter and frame signal generator

200,201,202: access device

The frame signal control method of the cell bus structure of the present invention for achieving the above object is, when the frame signal is output every 32 system clocks from the frame signal generator by the bus arbiter, the access device to occupy the cell bus frame format Each 2 bits allocated to 0 cycles of the cell request access to the cell bus, and according to the access request of the access device, the access device with the highest priority is identified and the bus access is allocated to the highest priority access device. Allow cell data from 1 cycle to 14 cycles to be transmitted on the bus or receive cell data on the bus, followed by the 15th cycle to determine the next highest priority access device to determine the corresponding frame signal and GTN. Access to other devices during the next frame If there is no request or the priority of the device currently being accessed is the highest, the same frame signal is continuously generated to transmit or receive cell data to be transmitted next, and then generate a frame signal every 32 system clocks.

In this case, when the frame signal is generated every 32 system clocks, 16 devices with lower numbers are allowed to request cell bus access during the first 16 clocks, and the remaining 16 devices with higher numbers are connected to the cell buses during the next 16 clocks. It allows access requests, allowing 32 devices to simultaneously share cell buses to access cell data.

Hereinafter, a method of controlling a frame signal in a cell bus structure according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a cell bus structure for applying a method of controlling a frame signal according to the present invention, in which a plurality of devices arbitrate access request signals for a plurality of cell buses outputted from a plurality of devices, and a plurality of devices are placed on a cell bus. The bus arbiter and frame signal generator 100, which generates a frame signal that allows data transmission or reception of cell data on the cell bus, and the cell bus by sharing the cell bus and outputting an access request signal for the cell bus. It consists of a number of access devices 200, 201, 202 that receive or transmit cell data on a cell bus.

The bus arbiter and frame signal generator 100 and the plurality of access devices 200, 201, and 202 are connected by a cell bus, and cell data, clock signals, frame signals, response signals, and congestion on the cell bus as shown in FIG. 2. The control signal and the like are carried.

A cell bus access process and a cell data transfer process of a device according to the frame signal control method in the cell bus structure configured as described above will now be described with reference to FIGS. 3 and 4.

First, the bus arbiter and the bus arbiter in the frame signal generator 100 control the frame signal generator to output a frame signal every 32 system clocks from the frame signal generator (S1).

When the frame signal is output from the frame signal generator every 32 system clocks in the step S1, a plurality of devices 200, 201, and 202, which are to occupy the cell bus, use a cell bus by using each 2 bits allocated to 0 cycles of the frame format. Requires access to (S2).

Then, the bus arbiter and the frame signal generator 100 identify the access devices 200, 201, 202 having the highest priority according to the access request (a) of the devices 200, 201, 202, and to the access devices 200, 201, 202 having the highest priority. A bus access grant signal is output to allow bus occupancy (S3).

Accordingly, the device receiving the grant signal transmits the cell data to be occupied by the cell bus to the cell bus or receives the cell data on the bus during the system clock from 1 cycle to 14 cycles (S4).

Next, in 15 cycles (b), the next highest priority access device is determined to determine a corresponding frame signal and a GTN (S5).

At this time, GTN is allocated 5 bits for distinguishing 32 devices.

Then, during the next frame, it is determined whether there is no access request of another device or the priority of the device currently being accessed is the highest (S6, S7), so that there is no access request of the other device or the priority of the device currently being accessed is the highest. In this case, the same frame signal is continuously generated (or the next frame request signal is output low if it is initially low as A), so that the next transmitted cell data is transmitted on or received from the cell bus. (S8).

After performing step S8, a frame signal is generated every 32 system clocks (S9), allowing 16 devices with lower numbers to request cell bus access during the first 16 clocks, and high during the next 16 clocks. Allow the remaining 16 devices in the number to make cell bus access requests, allowing 32 devices to simultaneously share the cell bus to access cell data.

On the other hand, if there is an access request of another device or if the priority of the device currently being accessed is not the highest, the flow proceeds to step S9.

Transmission on all such buses is triggered at the edge of the system clock. That is, one 32-bit word is sent per edge, as shown in the timing diagram of FIG. 3, cell data is transferred onto the bus at the falling edge of the write clock and transmitted from the bus at the falling edge of the read clock. do.

At this time, the write clock is delayed from the read clock to ensure the data hold time, and two frame times are required as two bits are allocated to each access device for bus occupancy rights.

In the write clock of all 32 system clocks, the first 16 clocks are used to accommodate the needs of the lower numbered access device, and the next 16 clocks are used to accept the needs of the higher numbered access device.

For example, if the frame signal is active, a lower number of devices is allowed to make an access request, and if it is inactive, an access request of a device with a higher number is allowed.

As described above, according to the present invention, by controlling the frame signal generation of the frame signal generator, the present invention can accept the cell bus access request signals of the 32 times the 16 access devices through the same system clock, thereby improving the data transmission capability. There is an effect that can be improved.

Claims (1)

A method of controlling a frame signal for receiving a cell bus access request of a multiple access device in a cell bus structure in which cell data is shared by transmitting and receiving cell buses, the method comprising: When a frame signal is output from the frame signal generator every 32 system clocks by the bus arbiter, an access device that occupies the cell bus may request access to the cell bus using each of two bits allocated to 0 cycles of the frame format. A second step of identifying an access device having the highest priority according to the access request of the access device requested in the first step, and allowing bus access to the highest priority access device; A third step in which the access device permitted to occupy the bus in the step transmits cell data from 1 cycle to 14 cycles on the bus or receives cell data on the bus; Fourth step of determining the frame signal and the GTN by determining the high priority access device After performing the fourth step, if there is no access request of another device during the next frame or the priority of the device currently being accessed is the highest, the fifth frame for continuously generating the same frame signal and transmitting or receiving the next transmitted cell data; And, after performing the fifth step, generate a frame signal every 32 system clocks, allowing the 16 devices with lower numbers to request cell bus access during the first 16 clocks, and the remaining 16 with higher numbers for the next 16 clocks. A method of controlling a frame signal in a cell bus structure, characterized in that the sixth step is performed to allow four devices to make a cell bus access request.