KR19990058834A - Arbitration Unit on Common Microprocessor Bus - Google Patents

Abstract

The present invention relates to an arbitration apparatus of a common microprocessor bus, and more particularly, to enable access arbitration without requiring a bus license of a central processing unit in a microprocessor bus operating independently in a system or apparatus employing a master processor and a plurality of slave processors. It relates to a mediation device for.

The present invention relates to a plurality of microcontrollers, a main CPU controlling a bus of the microcontroller through a buffer, and a strobe B signal input from a microcontroller in arbitration logic for adjusting bus usage of the microcontroller and the buffer and the main CPU. Is low and logic 2 outputting high only when the output of logic 2 is low, the output of logic 1 is input, and the output of logic 1 is D-flip flop 1, which resets the output of logic 2, The output of logic 2 is reset and the D-flip flop 2 having the clock reversed from the D-flip flop 2, the strobe A input from the main CPU is low, and the D-flip flop 1 and the D-flip flop 2 Logic 2 that outputs high only when the outputs of both are low, an inverter that inverts the output of logic 2 and supplies it as an enable signal of the buffer, and the strobe B signal of the microcontroller Low and logic 3 outputting high only when the output of the D-flip-flop 2, and a delay for delaying the output of the logic 3 to supply the access termination signal of the microcontroller.

Description

Arbitration Unit on Common Microprocessor Bus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbiter logic of a common microprocessor bus, and more particularly, to a system or apparatus employing a master processor and a plurality of slave processors. The present invention relates to an arbitration apparatus for enabling access arbitration on a standalone microprocessor bus without requiring a bus license of a central processing unit (CPU).

In a system containing multiple processors and memory, communication between devices uses a bus. Typically, dual port random access memory (DPRAM) is used for communication between processors. The bidirectional port RAM serves as a buffer for sending and receiving processing messages between processors.

1 is an operation diagram illustrating communication between two conventional processors. As shown, two processors consisting of a CPU and peripheral circuits are connected to a bidirectional RAM via an Address / Data / Control bus. The processor and the bidirectional RAM are coordinated by an arbiter.

However, in this case, when a processor having an independent bus structure attempts to access a register inside another processor that currently performs its own task, a separate bus usage method is required.

Therefore, in order to solve the above problems, the present invention needs to match a plurality of microcontrollers operated as independent buses with a main CPU having one independent bus, thereby requiring a bus license before access. It is an object of the present invention to provide an arbitration device of a common microprocessor bus, which is configured so that the main CPU can access control the internal registers of the microcontroller to influence the operation mode of the microcontroller.

1 is an operational diagram illustrating communication between two conventional processors.

2 is a block diagram showing a communication method of a common microprocessor bus according to the present invention;

3 is an internal configuration diagram of the arbitration logic shown in FIG.

One preferred embodiment of the present invention devised to achieve the object as described above,

In a plurality of microcontrollers, a buffer connected to the microcontroller via a bus, a main CPU controlling the bus of the microcontroller through the buffer, and arbitration logic coordinating the bus usage of the microcontroller and the buffer and the main CPU. ,

Logic 1 for outputting high only when the strobe B signal input from the microcontroller is low and the output of logic 2 is low;

A D-flip-flop 1 for inputting the output of logic 1 and for resetting the output of logic 2;

A D-flip flop 2 having the output of the logic 1 as an input and a reset of the output of logic 2 and having a clock inverted from the D-flip flop 2;

Logic 2 for outputting high only when strobe A input from the main CPU is low and both the outputs of the D-flip flop 1 and the D-flip flop 2 are low;

An inverter for inverting the output of the logic 2 to supply the enable signal of the buffer;

Logic 3 for outputting high only when the strobe B signal of the microcontroller is low and the output of the D-flip-flop 2 is low; And

And a delayer for delaying the output of the logic 3 to supply the access termination signal of the microcontroller.

In one preferred embodiment of the present invention, the D-flip flop 1 and D-flip flop 2 preferably serves as a flag indicating whether the main CPU and the microcontroller is in an access state,

Preferably, the D-flip flop 1 outputs high when the microcontroller is currently occupying a bus.

Preferably, the D-flip flop 2 outputs high when the main CPU is occupying the current bus.

Preferably, the D-flip flop 1 and the D-flip flop 2 are given priority to the access of the main CPU.

Preferably, the delay unit has a delay value according to an access time condition of the microcontroller.

In the above logic 2, the strobe B goes low, and then the output is made high after one clock cycle.

2 is a block diagram illustrating a communication method of a common microprocessor bus according to the present invention. A processor module having a main CPU and a peripheral circuit as shown; A processor module having a microcontroller and peripheral circuitry; A buffer 1 connected to the system via an address / control bus; A buffer 2 connected to the processor module through a data bus; And an arbiter for coordinating bus usage of the processor module and buffer.

The two processor modules separate the buses as buffers. When the main CPU occupies the microcontroller bus, the buffer is opened so that the bus of the main CPU occupies the microcontroller bus momentarily. Arbitration logic allows the main CPU to use the bus by allowing the microcontroller bus to occupy according to the state of the relative strobe when a particular strobe of the main CPU and the microcontroller strobe is active. Arbitration logic can also control access termination to standby access to the main CPU.

FIG. 3 shows an internal configuration diagram of the arbitration logic shown in FIG. 2. As shown, logic 1 outputting high only when the strobe B signal input from the microcontroller is low and the output of logic 2 is low; A D-flip-flop 1 for inputting the output of logic 1 and for resetting the output of logic 2; A D-flip flop 2 having the output of the logic 1 as an input and a reset of the output of logic 2 and having a clock inverted from the D-flip flop 2; Logic 2 for outputting high only when strobe A input from the main CPU is low and both the outputs of the D-flip flop 1 and the D-flip flop 2 are low; An inverter for inverting the output of the logic 2 to supply the enable signal of the buffer; Logic 3 for outputting high only when the strobe B signal of the microcontroller is low and the output of the D-flip-flop 2 is low; And a delayer for delaying the output of the logic 3 to supply the access termination signal of the microcontroller.

Hereinafter, the operation of the present invention will be described with reference to FIGS. 2 and 3. The outputs of logic 2 and logic 3 are the final access selection of the microcontroller. The select A signal, the output of logic 2, becomes a signal that allows the microcontroller to access the bus by the main CPU. The select B signal, the output of logic 3, becomes a signal that allows bus access by the microcontroller itself. The bus selection of the microcontroller is determined by the selection A and selection B signals.

Two D-flip flops serve as flags. Each flip-flop indicates an access state of the other party when one processor module wants to access it. In addition, when the other party is in the access standby state, his or her access information can be registered in the flag.

First, logic 1 outputs high only when strobe B, which is an access strobe of the microcontroller input to logic 1, is low and another input is low. Another input of logic 1 is the select A signal that is the output of logic 2. That is, logic 1 outputs high only when strobe B is low (active) and select A is low (standby). In this case, at the rising edge of the D flip-flop 1 clock, the output of the flip-flop 1 becomes high, indicating that the microcontroller is currently occupying the bus. Flip-flop 1's output remains high while the bus is busy.

If the output of flip-flop 2 input to logic 3 is low (standby), logic 3 outputs high. The output signal of logic 3 then applies an access termination B signal to the microcontroller via a delay element having a delay value corresponding to the access time condition of the microcontroller. The microcontroller to which the access termination B signal is applied allows the access termination.

In the meantime, even if strobe A goes low (active), the logic condition of the flip-flop is not met in the logic circuit of logic 2. Therefore, the logic is blocked. Therefore, selection A remains low (standby), which does not affect the flip condition (high) of the flip-flop. In this case, since selection A is not active and no access termination is applied to the microcontroller, the main CPU's access is pending and the buffer is closed, so the microcontroller closes the current access without any effect.

When the strobe B of the microcontroller goes high (standby), the output of the flip flop goes low after one clock cycle. This is a condition that the Select A signal becomes high (active), and this information affects the logic 1 input condition at the same time as the flip-flop reset. Eventually, the selection B association logic of strobe B is cut off and the buffer is enabled, so that the bus of the main CPU is connected to the bus of the microcontroller. The microcontroller is then controlled according to the access state of the main CPU. The access termination signal provided by the microcontroller is then provided to the main CPU to terminate the access.

As described above, the actual access A is activated when a clock cycle passes after the access of the microcontroller ends. This is substantially an operation in consideration of the release transition time generated in the control signal line of the microcontroller. Also, by using two flip-flops applied by inverting the input clocks, only one side of the microcontroller and the main CPU may be selected even when the occupied signal is simultaneously applied. In this case, the priority is on the main CPU.

By extending the arbitration logic according to the present invention in parallel, it can be applied to the matching of multiple microcontrollers and one main CPU.

According to the present invention operating as described above, communication matching can be performed by determining the bus usage order between processors in the design of a system which adopts a plurality of microprocessors to distribute small words.

Claims (7)

In a plurality of microcontrollers, a buffer connected to the microcontroller via a bus, a main CPU controlling the bus of the microcontroller through the buffer, and arbitration logic coordinating the bus usage of the microcontroller and the buffer and the main CPU. , Logic 1 for outputting high only when the strobe B signal input from the microcontroller is low and the output of logic 2 is low; A D-flip-flop 1 for inputting the output of logic 1 and for resetting the output of logic 2; A D-flip flop 2 having the output of the logic 1 as an input and a reset of the output of logic 2 and having a clock inverted from the D-flip flop 2; Logic 2 for outputting high only when strobe A input from the main CPU is low and both the outputs of the D-flip flop 1 and the D-flip flop 2 are low; An inverter for inverting the output of the logic 2 to supply the enable signal of the buffer; Logic 3 for outputting high only when the strobe B signal of the microcontroller is low and the output of the D-flip-flop 2 is low; And And a delayer for delaying the output of said logic 3 to supply it as an access termination signal of a microcontroller. 2. The apparatus of claim 1, wherein the D-flip-flop 1 and the D-flip-flop 2 serve as flags indicating whether the main CPU and the microcontroller are in an access state. 3. The apparatus of claim 2, wherein D-flip-flop1 outputs high when the microcontroller is currently occupying a bus. 3. The arbitration apparatus of claim 2, wherein D-flip-flop2 outputs high when the main CPU is currently occupying the bus. 3. The apparatus of claim 2, wherein the D-flip-flop 1 and the D-flip-flop 2 prioritize access to the main CPU. 2. The apparatus of claim 1, wherein the delayer has a delay value according to an access time condition of the microcontroller. 2. The apparatus of claim 1, wherein logic 2 causes the output to be high after one cycle of clock after strobe B goes low.