KR19990058269A - Frequency Tracker in Code Division Multiple Access Systems - Google Patents

Abstract

The present invention relates to a frequency tracker in a code division multiple access system. Fingers 200 and 300 receive a transmission signal with different chip delay times for finger 100. The fingers 100, 200, and 300 respectively detect a phase difference in one chip unit, and the detected phase difference is added and applied to the phase feedback loop 500. The phase feedback loop changes the reception frequency in response to the added phase difference.

Description

Frequency Tracker in Code Division Multiple Access Systems

The present invention relates to a code division multiple access system (hereinafter referred to as CDMA), and more particularly, to a frequency tracker of a CDMA receiver.

CDMA is one of modulation and multiple access schemes, and is based on the widely used Spread Spectrum Communication scheme. Recently, CDMA has been applied to digital mobile communication and advanced wireless communication.

In such a CDMA scheme, information to be transmitted is divided into I and Q channels, and the information of the I and Q channels is spread and transmitted as a pseudorandom code division technique.

On the other hand, the CDMA receiving side needs to oscillate the internal clock synchronized with the transmission side signal, but a mismatch occurs due to the environment at the time of transmission, and thus an apparatus for correcting the oscillation frequency of the internal clock is required. Conventionally, as a method of matching the oscillation frequency of the receiving side with the transmitting side signal, a method of correcting using a phase difference between symbols of the fingers has been used.

That is, as shown in Fig. 1, the receiving side is composed of three fingers 1, 2 and 3, and these fingers 1, 2 and 3 are configured to detect the phase difference between symbols, respectively.

Since the fingers 1, 2, and 3 in FIG. 1 have the same configuration, only the configuration of the finger 1 is shown in detail.

As shown, the signals of the I and Q channels are converted into digital signals through the analog / digital converter 11. Therefore, the signals of the analog / digital converter 11 will form a chip in a spread state by a pseudo random number code (hereinafter referred to as PN code) at the transmitting side.

The chips of the analog / digital converter 11 are applied to the despreader 12, and the despreader 12 despreads these chips by a PN code (same as the PN code on the transmitting side). The symbol determiner 13 inputs the output of the despreader 12 to determine a symbol. That is, one symbol at the transmitting side is spread to a plurality of chips by the PN code, and the spreading chips are decoded into the original symbol through the despreading unit 12 and the symbol determining unit 13 at the receiving side.

The I and Q channel symbols from the symbol determiner 13 are delayed through the delay unit 14 and then passed through the multipliers 15 and 16 to the previous Q channel Q _k-1 and I channel I _k-1 . It is multiplied and applied to the adder 17. The output of this adder 17 means the phase difference e (t) between the received signals.

That is, if there is no data transmitted through the I and Q channels, that is, if the chips are in the original PN code state, the symbol determiner 13 outputs sinθ and cosθ through the I and Q channels, so that the multiplier 15, 16) outputs sinθcosθ 'and cosθsinθ'. Is the phase of the symbol delayed by one symbol period.

Therefore, the adder 17 outputs sin (θ-θ ') by summing -sinθcosθ' and cosθsinθ ', and this output represents the phase difference between symbols (previous symbol and current symbol).

On the other hand, the fingers 2 and 3 perform the same operation as the finger 1, but the operation time points are slightly different in units of predetermined chips. That is, the reason why the plurality of fingers 1, 2, 3 is formed is that the transmission signal is received with a slight time difference (several chip units) due to fading. This is because all signals delayed by fading can be received.

As described above, when the operating points of the fingers 1, 2, and 3 are different from each other, the time points at which the phase difference e (t) is detected between symbols are also different from each other. That is, the finger 1 detects the phase difference e (t), and after the time in the predetermined chip unit elapses, the finger 2 detects the phase difference e (t), and the time in the predetermined chip unit After elapse, the finger 3 detects the phase difference e (t).

Meanwhile, the phase feedback loop PLL of the receiver is controlled by using the phase difference e (t), and in the related art, the phase difference e (t) of the fingers 1, 2, and 3 is added to the adder 6. It is configured to control the PLL (4) by the value added through, and requires a memory to temporarily store the phase difference (e (t)) detected by the fingers (1, 2, 3). That is, as described above, since the times at which the fingers 1, 2, 3 detect the phase difference e (t) are different from each other, the phase differences detected by the fingers 1, 2, 3 are determined by the memory 51, 52, 53 is temporarily stored in the PLL (P), and the phase difference e (t) signals of the memories 51, 52, and 53 are applied to the adder 6 at the same time point under the control of a control device (not shown). It is configured to apply to 4).

Therefore, in the conventional apparatus, as described above, a separate memory for storing the phase difference e (t) of the fingers 1, 2, and 3 is required, so that the circuit configuration becomes complicated, thus counteracting the technical trend of miniaturization and weight reduction. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to provide a frequency tracker in a CDMA system that makes it easy to know the frequency correction by detecting the phase difference of the receiving chips.

1 is a schematic block diagram showing a frequency tracker in a conventional code division multiple access system;

2 is a block diagram illustrating a frequency tracker in a code division multiple access system according to the present invention.

<Description of the symbols for the main parts of the drawings>

100, 200, 300: Finger 101-104: Multiplier

105,106: adder 107,108: multiplier

109: delay unit 110: the adder

400: addition circuit 500: PLL

The present invention for achieving this object, in the code division multiple access system I channel signal applied to A circuit for receiving signals of the Q channel and matching the frequency of the oscillation clocks with a first multiplier for multiplying the signal of the I channel with the PN code for the I channel, and the signal of the I channel for the Q channel. A second multiplier that multiplies the PN code, a third multiplier that multiplies the signal of the Q channel with a PN code for the Q channel, a fourth multiplier that multiplies the signal of the Q channel with a PN code for the I channel, and a first multiplier of the first and third multipliers A first adder that adds the output and outputs it as an I-channel signal, a second adder that adds the outputs of the second and fourth multipliers and outputs it as a Q-channel signal, and one chip each of the outputs of the first adder and the second adder A fifth multiplier that multiplies the delay unit for delaying, the I channel signal of the first adder and the Q channel signal delayed in the delay unit, a sixth multiplier for multiplying the Q channel signal of the second adder and the I channel signal delayed in the delay unit, Output of the sixth multiplier From and comprising a summer for calculating a phase difference by subtracting the output of the fifth multiplier, at least two fingers and that has a different operation start time driving; An addition circuit for adding the phase difference of the fingers; And a phase feedback loop for changing the reception frequency in accordance with the output of the addition circuit.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 is a block diagram of a device according to the present invention, three fingers (100, 200, 300) are also configured in the present invention, these fingers (100, 200, 300) have the same configuration, specifically showing only the configuration for the finger 100 It was.

Signal (I _on), (Q _on) on the I and Q channels, the fingers 100 as shown have is applied, signals of the I and Q channels (I _on), (Q _on) is a multiplier (101 - 104) I and Q channel PN code _(PN I) through has a structure that is to be multiplied _(PN Q), respectively.

Of the outputs of the multipliers 101-104, the outputs of the multipliers 101 and 103 are added through the adder 105 (I _K ), and the outputs of the multipliers 102 and 104 are added through the adder 106 (Q _k ). Have

The outputs of the adders 105 and 106 are applied to the multipliers 107 and 108, while after this one chip delay through the one-chip delay unit 109 (I _k-1 ) and (Q _k-1 ) to the relative multipliers 107 and 108, respectively. Is approved.

The outputs of the multipliers 107 and 108 are summed up through the adder 110, and the output of the adder 110 becomes the phase difference e (t) per chip.

That is, the I _on signal and the Q _on signal may be expressed as in Equation (1).

Therefore, if the signal I _k output from the adder 105 is expressed as Equation 2, the signal Q _k output from the adder 106 may be expressed as Equation 3.

I _K = I _on I _PN + Q _on Q _PN = cos (θ)

Q _K = Q _on (-I _PN ) + I _on Q _PN = sin (θ)

The P _k and Q _k values are then made is delayed one chip through a delay unit _{(109) (Q k-1} ,, I k-1) multiplied by the other party P _k and Q _k by the multiplier (107 108), an adder (110 ), The adder 110 outputs an output phase difference e (t) as shown in Equation 4.

e (t) =-I _K Q _K-1 + Q _K I _{K -One}

Here, when the phase of the signal delayed for one chip period is (? '), Equation 4 may be represented by Equation 5.

e (t) =-[cos (θ)] [sin (θ ′)] + [sinθ)] [cos (θ ′)] = sin (θ-θ ′)

Equation 5 shows a phase difference of one chip unit in the finger 100.

On the other hand, since the fingers 200 and 300 detect the phase difference of one chip unit by the same operation as the finger 100 and apply them to the adding circuit 400, the adding circuit 400 performs the phase difference e (t) of the fingers 100, 200 and 300. ) Is added to the PLL 500.

In this case, it can be seen that the fingers 100, 200, and 300 in the present invention detect the phase difference in units of chips differently from the prior art. Here, conventionally, it is configured to detect a phase difference in symbol units, and a memory is required for each finger to detect a phase difference in symbol units because a time difference occurs in a predetermined chip unit. No memory is required. That is, since the chips 100 are continuously input to the fingers 100, 200 and 300 of the present invention, the time for detecting the phase difference between the chips 100, 200 and 300 is the same, and thus a separate memory for storing the detected phase difference may be used. There is no need.

As described above, the present invention allows each finger to detect the phase difference in units of chips, thereby eliminating the need to use a separate memory to store the phase difference of the fingers, thereby reducing the size and weight of the receiving device.

Claims (1)

In code division multiple access system I channel signal applied to A circuit for receiving signals of a Q channel applied to and matching these signals with the frequency of an oscillation clock, A first multiplier for multiplying the signal of the I channel with the PN code for the I channel, a second multiplier for multiplying the signal of the I channel with the PN code for the Q channel, and a third multiplier for the Q channel PN code for the Q channel A multiplier, a fourth multiplier for multiplying the Q-channel signal with an I-channel PN code, a first adder for adding the outputs of the first and third multipliers and outputting the I-channel signal, and the second and fourth A second adder for adding the output of the multiplier and outputting it as a Q channel signal, a delay unit for delaying the outputs of the first adder and the second adder by one chip, and the I channel signal of the first adder and the delay unit A fifth multiplier for multiplying the delayed Q channel signal, a sixth multiplier for multiplying the Q channel signal of the second adder and an I channel signal delayed in the delay unit, and an output of the fifth multiplier from the output of the sixth multiplier top And comprising a summer for calculating a difference, at least two or more fingers for driving has a different operation start time from each other; An addition circuit for adding phase differences of the fingers; A frequency tracker in a code division multiple access system having a phase feedback loop for changing a reception frequency in accordance with an output of the addition circuit.