KR19990057708A - Trench element isolation - Google Patents
Trench element isolation Download PDFInfo
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- KR19990057708A KR19990057708A KR1019970077779A KR19970077779A KR19990057708A KR 19990057708 A KR19990057708 A KR 19990057708A KR 1019970077779 A KR1019970077779 A KR 1019970077779A KR 19970077779 A KR19970077779 A KR 19970077779A KR 19990057708 A KR19990057708 A KR 19990057708A
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- liner
- oxide
- etch stop
- film
- trench
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- 238000002955 isolation Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 3
- 238000009832 plasma treatment Methods 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 239000011241 protective layer Substances 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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Abstract
본 발명은 식각저지 라이너를 사용하는 트렌치 소자분리 방법에 관하여 개시한다. 본 발명은 트렌치 영역의 측벽 및 바닥에 산화막 라이너를 형성하고 산화막 라이너 표면에 질소를 함유하는 가스 분위기에서 플라즈마 처리를 실시함으로써, 산화막 라이너 표면에 산화막 식각용액에 대하여 높은 식각 선택비를 보이는 식각저지 라이너를 선택적으로 형성하는 것을 특징으로 한다. 이에 따라, 트렌치 영역들 사이의 활성영역을 노출시키기 위하여 활성영역 상에 형성된 패드산화막 패턴 및 패드질화막 패턴을 과도식각공정으로 제거할지라도 트렌치 영역의 측벽이 노출되는 것을 방지할 수 있다.The present invention discloses a trench isolation method using an etch stop liner. The present invention forms an oxide liner on the sidewalls and bottom of the trench region and performs a plasma treatment in a gas atmosphere containing nitrogen on the surface of the oxide liner, thereby exhibiting a high etching selectivity with respect to the oxide etch solution on the surface of the oxide liner. It characterized in that to selectively form. Accordingly, even if the pad oxide layer pattern and the pad nitride layer pattern formed on the active region are removed by an overetch process in order to expose the active regions between the trench regions, the sidewalls of the trench regions may be prevented from being exposed.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 식각저지 라이너를 사용하는 트렌치 소자분리 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a trench device isolation method using an etch stop liner.
반도체소자의 집적도가 증가함에따라 소자분리 영역의 폭은 점점 감소하고 있다. 고집적 반도체소자에 적합한 소자분리 기술로서 트렌치 소자분리 기술이 널리 이용되고 있다. 트렌치 소자분리 기술은 반도체기판의 소정영역을 선택적으로 식각하여 좁은 폭을 갖는 트렌치 영역을 형성하고, 트렌치 영역을 산화막으로 채우는 기술이다. 따라서, 트렌치 소자분리 기술을 사용하여 서로 이웃한 모스 트랜지스터를 격리시킬 경우 버즈비크가 생성되는 로코스(LOCOS; local oxidation of silicon) 소자 분리 기술에 비하여 소자분리 영역의 폭을 감소시킬 수 있다. 그러나, 트렌치 소자분리 기술을 사용하여 모스 트랜지스터를 형성하는 경우에, 트렌치 영역 내의 산화막이 리세스(recess)되어 트렌치 영역의 상부측벽(upper sidewall)이 노출된다. 이는, 트렌치 영역을 채우는 산화막을 형성한 후에 트렌치 영역들 사이의 활성영역 표면을 노출시키기 위한 습식식각 공정시 트렌치 영역 내의 산화막 또한 식각되기 때문이다. 상기한 바와 같이 트렌치 영역의 상부측벽이 노출된 반도체기판의 활성영역 표면에 게이트 산화막을 형성하고 게이트 산화막을 가로지르는 게이트 전극을 형성하면, 트렌치 영역의 상부측벽 상에도 게이트 산화막 및 게이트 전극이 형성된다. 이에 따라, 모스 트랜지스터의 게이트 전극에 문턱전압보다 낮은 전압이 인가될지라도 트렌치 영역의 상부 코너부위에 강한 전계가 형성된다. 결과적으로, 모스 트랜지스터의 역협폭 효과(inverse narrow width effect)에 기인하는 채널 누설전류가 증가되어 모스 트랜지스터의 스위칭 특성이 저하된다.As the degree of integration of semiconductor devices increases, the width of device isolation regions decreases. Trench device isolation technology has been widely used as a device isolation technology suitable for highly integrated semiconductor devices. The trench isolation technique is to selectively etch a predetermined region of a semiconductor substrate to form a trench region having a narrow width, and to fill the trench region with an oxide film. Accordingly, when the trench isolation device is used to isolate neighboring MOS transistors, the width of the device isolation area may be reduced as compared to a local oxidation of silicon (LOCOS) device isolation technology in which Buzzbeek is generated. However, when forming a MOS transistor using a trench isolation technique, an oxide film in the trench region is recessed to expose the upper sidewall of the trench region. This is because the oxide film in the trench region is also etched during the wet etching process for exposing the surface of the active region between the trench regions after forming the oxide film filling the trench region. As described above, when the gate oxide film is formed on the surface of the active region of the semiconductor substrate where the upper side wall of the trench region is exposed and the gate electrode that crosses the gate oxide film is formed, the gate oxide film and the gate electrode are also formed on the upper side wall of the trench region. . Accordingly, even when a voltage lower than the threshold voltage is applied to the gate electrode of the MOS transistor, a strong electric field is formed in the upper corner portion of the trench region. As a result, the channel leakage current due to the inverse narrow width effect of the MOS transistor is increased, thereby lowering the switching characteristics of the MOS transistor.
상기한 문제점을 개선시키기 위한 트렌치 소자분리 기술이 미국 특허 제5,447,884호에 개시되었다. 미국 특허 제5,447,884호에 따르면, 트렌치 영역이 형성된 기판 전면을 덮는 질화막 및 트렌치 영역을 채우는 TEOS 산화막을 순차적으로 형성한 후에 약 800℃의 온도에서 습식 산화공정을 실시함으로써, 상기 TEOS 산화막 및 상기 질화막을 응축(densification)시킨다. 이와 같이 800℃의 저온에서 습식 산화공정에 의해 응축된 TEOS 산화막 및 질화막은 각각 불산 용액(hydrofluoric acid) 및 인산 용액(phosphoric acid)에 대하여 느린 습식 식각률을 보인다. 따라서, 트렌치 영역들 사이의 활성영역을 노출시키기 위한 패드질화막 및 패드산화막을 식각하는 후속 공정을 실시할 때 트렌치 영역 내의 TEOS 산화막 및 질화막이 리세스되는 현상을 방지할 수 있다. 그러나, 미국 특허 제5,447,884호는 트렌치 영역들 사이의 활성영역을 노출시킨 후에 트렌치 영역 내의 TEOS 산화막 표면이 활성영역의 표면보다 높은 상태를 유지한다. 따라서, 평탄화 공정에 불리한 문제점이 있다.Trench isolation techniques have been disclosed in US Pat. No. 5,447,884 to improve the above problem. According to US Pat. No. 5,447,884, the TEOS oxide film and the nitride film are formed by sequentially forming a nitride film covering the entire surface of the substrate where the trench region is formed and a TEOS oxide film filling the trench region, and then performing a wet oxidation process at a temperature of about 800 ° C. Condensation. As such, the TEOS oxide film and the nitride film condensed by the wet oxidation process at a low temperature of 800 ° C. show a slow wet etching rate with respect to the hydrofluoric acid and the phosphoric acid solution, respectively. Therefore, when a subsequent process of etching the pad nitride film and the pad oxide film for exposing the active regions between the trench regions is performed, the phenomenon in which the TEOS oxide film and the nitride film in the trench region are recessed can be prevented. However, U. S. Patent No. 5,447, 884 maintains the surface of the TEOS oxide film in the trench region higher than the surface of the active region after exposing the active region between the trench regions. Therefore, there is a disadvantage in the planarization process.
본 발명이 이루고자하는 기술적 과제는 평탄화 공정에 유리하면서 모스 트랜지스터의 역협폭 효과를 개선시킬 수 있는 트렌치 소자분리 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a trench isolation method that may improve the reverse narrowing effect of a MOS transistor while being advantageous for a planarization process.
도 1 내지 도 5는 본 발명에 따른 트렌치 소자분리 방법을 설명하기 위한 단면도들이다.1 to 5 are cross-sectional views for describing a trench isolation method according to the present invention.
상기 기술적 과제를 달성하기 위하여 본 발명은 반도체기판 상에 반도체기판의 소정영역을 노출시키는 보호층 패턴을 형성하고, 상기 노출된 반도체기판을 식각하여 트렌치 영역을 형성한다. 여기서, 상기 보호층 패턴은 차례로 적층된 패드산화막 패턴 및 패드질화막 패턴으로 구성된다. 상기 트렌치 영역의 측벽 및 바닥에 선택적으로 산화막 라이너(oxide liner)를 형성한 다음, 상기 산화막 라이너의 표면에 식각저지 라이너(etch stop liner)를 형성한다. 상기 식각저지 라이너는 산화막 식각용액에 대하여 높은 식각 선택비(high etch selectivity)를 갖는 물질막, 예컨대 실리콘 옥시나이트라이드(silicon oxynitride)막으로 형성하는 것이 바람직하며, 질소원자를 함유하는 가스 분위기에서 플라즈마 처리를 실시함으로써 산화막 라이너의 표면에 선택적으로 형성할 수 있다. 상기 식각저지 라이너가 형성된 기판 전면에 상기 트렌치 영역을 채우는 CVD 산화막을 형성하고, 상기 보호층 패턴이 노출될 때까지 CVD 산화막을 평탄화시키어 트렌치 영역 내에 CVD 산화막 패턴을 형성한다. 상기 노출된 보호층 패턴을 구성하는 패드질화막 패턴 및 패드산화막 패턴을 화학용액들을 사용하여 연속적으로 제거함으로써, 트렌치 영역들 사이의 활성영역 표면을 노출시킨다. 여기서, 상기 패드질화막 패턴을 제거하기 위한 화학용액으로는 인산용액(H3PO4)이 널리 사용되고, 상기 패드산화막 패턴을 제거하기 위한 화학용액으로는 불산용액(hydrofluoric acid) 또는 완충 산화막 식각용액(BOE;buffered oxide etchant) 등이 널리 사용된다. 상기 패드질화막 패턴 및 상기 패드산화막 패턴을 제거할 때 상기 식각저지 라이너는 상기 산화막 라이너가 불산용액 또는 완충산화막 식각용액에 의해 식각되는 것을 방지하는 역할을 한다. 그리고, 상기 패드산화막 패턴을 제거하는 공정은 활성영역 표면을 완전히 노출시키기 위하여 과도하게 식각하여야 한다. 이에 따라, 식각저지 라이너의 상부 측벽이 노출되고 트렌치 영역 내에 리세스된 CVD 산화막 패턴이 형성된다. 상기한 바와 같이, 트렌치 영역의 측벽은 산화막 라이너 및 식각저지 라이너에 의해 둘러싸이므로 노출되는 것을 방지할 수 있다. 이어서, 상기 활성영역 표면에 게이트 산화막을 형성하고, 상기 게이트 산화막의 소정영역 상을 지나는 게이트 전극을 형성하여 모스 트랜지스터를 형성한다. 여기서, 상기 산화막 라이너는 상기 게이트 산화막보다 두껍게 형성하는 것이 바람직하다.In order to achieve the above technical problem, the present invention forms a protective layer pattern exposing a predetermined region of a semiconductor substrate on a semiconductor substrate, and forms a trench region by etching the exposed semiconductor substrate. The protective layer pattern may include a pad oxide layer pattern and a pad nitride layer pattern that are sequentially stacked. An oxide liner is selectively formed on sidewalls and bottoms of the trench region, and then an etch stop liner is formed on the surface of the oxide liner. The etch stop liner may be formed of a material film having a high etch selectivity with respect to an oxide etching solution, such as a silicon oxynitride film, and a plasma in a gas atmosphere containing nitrogen atoms. By carrying out the treatment, it can be selectively formed on the surface of the oxide film liner. A CVD oxide layer filling the trench region is formed on the entire surface of the substrate on which the etch stop liner is formed, and the CVD oxide layer is planarized until the protective layer pattern is exposed to form a CVD oxide layer pattern in the trench region. The pad nitride layer pattern and the pad oxide layer pattern constituting the exposed protective layer pattern are continuously removed using chemical solutions, thereby exposing the surface of the active region between the trench regions. Here, a phosphoric acid solution (H 3 PO 4 ) is widely used as a chemical solution for removing the pad nitride layer pattern, and a hydrofluoric acid or a buffered oxide etching solution (H 3 PO 4 ) is used as the chemical solution for removing the pad oxide layer pattern. BOE (buffered oxide etchant) is widely used. When the pad nitride layer pattern and the pad oxide layer pattern are removed, the etch stop liner prevents the oxide liner from being etched by the hydrofluoric acid solution or the buffer oxide layer etching solution. In addition, the process of removing the pad oxide layer pattern may be excessively etched to completely expose the surface of the active region. As a result, an upper sidewall of the etch stop liner is exposed and a CVD oxide film pattern recessed in the trench region is formed. As described above, the sidewalls of the trench region may be surrounded by the oxide liner and the etch stop liner, thereby preventing exposure. Next, a gate oxide film is formed on the surface of the active region, and a gate electrode passing over a predetermined region of the gate oxide film is formed to form a MOS transistor. Here, the oxide film liner is preferably formed thicker than the gate oxide film.
상술한 본 발명에 의하면, 활성영역을 노출시키기 위하여 패드질화막 패턴 및 패드산화막 패턴을 제거할 때, 트렌치 영역의 측벽이 노출되는 것을 방지할 수 있다. 이에 따라, 모스 트랜지스터의 역협폭 효과에 기인하는 스위칭 특성의 저하를 방지할 수 있다.According to the present invention described above, when the pad nitride layer pattern and the pad oxide layer pattern are removed to expose the active region, the sidewalls of the trench region can be prevented from being exposed. Thereby, the fall of the switching characteristic resulting from the reverse narrowing effect of a MOS transistor can be prevented.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 보호층 패턴(6)을 형성하는 단계를 설명하기 위한 단면도이다. 도 1을 참조하면, 반도체기판(1), 예컨대 실리콘 기판 상에 패드산화막 및 패드질화막을 차례로 형성한다. 상기 패드질화막 및 상기 패드산화막을 연속적으로 패터닝하여 상기 반도체기판(1)의 소정영역을 노출시키는 패드산화막 패턴(3) 및 패드질화막 패턴(5)을 형성한다. 여기서, 상기 패드산화막 패턴(3) 및 패드질화막 패턴(5)은 보호층 패턴(6)을 구성한다. 상기 패드산화막으로는 열산화막이 널리 사용되고, 상기 패드질화막으로는 CVD 질화막이 널리 사용된다.1 is a cross-sectional view for explaining a step of forming the protective layer pattern 6. Referring to FIG. 1, a pad oxide film and a pad nitride film are sequentially formed on a semiconductor substrate 1, for example, a silicon substrate. The pad nitride film and the pad oxide film are successively patterned to form a pad oxide film pattern 3 and a pad nitride film pattern 5 exposing predetermined regions of the semiconductor substrate 1. Here, the pad oxide film pattern 3 and the pad nitride film pattern 5 constitute a protective layer pattern 6. A thermal oxide film is widely used as the pad oxide film, and a CVD nitride film is widely used as the pad nitride film.
도 2는 트렌치 영역(T) 및 산화막 라이너(7)를 형성하는 단계를 설명하기 위한 단면도이다. 상세히 설명하면, 상기 보호층 패턴(6)에 의해 노출된 반도체기판(1)을 식각하여 트렌치 영역(T)을 형성한다. 상기 트렌치 영역(T)이 형성된 기판을 열산화시키어 상기 트렌치 영역의 측벽 및 바닥에 산화막 라이너(7)를 선택적으로 형성한다. 상기 산화막 라이너(7)는 100Å 내지 300Å의 두께로 형성하는 것이 바람직하다.2 is a cross-sectional view for describing a step of forming the trench region T and the oxide film liner 7. In detail, a trench region T is formed by etching the semiconductor substrate 1 exposed by the protective layer pattern 6. The substrate on which the trench region T is formed is thermally oxidized to selectively form an oxide film liner 7 on sidewalls and bottoms of the trench region. The oxide film liner 7 is preferably formed to a thickness of 100 kPa to 300 kPa.
도 3은 식각저지 라이너(9) 및 CVD 산화막 패턴(11)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 상기 산화막 라이너(7)가 형성된 결과물을 질소를 함유하는 가스 분위기에서 플라즈마 처리를 실시함으로써, 산화막 라이너(7) 표면에 산화막 식각용액에 대하여 높은 식각 선택비를 보이는 식각저지 라이너(9), 즉 실리콘 옥시나이트라이드(silicon oxynitride)막을 선택적으로 형성한다. 상기 질소를 함유하는 가스로는 N2O 가스, NO 가스 및 암모니아(NH3) 가스로 이루어진 일 군중 선택된 어느 하나인 것이 바람직하다. 다음에, 상기 식각저지 라이너(9)가 형성된 결과물 전면에 트렌치 영역(T)을 채우는 CVD 산화막을 형성한다. 여기서, 상기 CVD 산화막은 트렌치 영역(T)을 완전히 채우기 위하여 단차도포성이 우수한 물질막으로 형성하는 것이 바람직하다. 상기 단차도포성이 우수한 물질막으로는 O3-TEOS(Ozone - TetraEthylOrthoSilicate)막과 같은 언도우프트 산화막(undoped silicate glass layer)으로 형성할 수도 있고, PSG(PhosphoSilicate Glass)막 또는 BPSG(BoroPhosphoSilicate Glass)막과 같은 도우프트 산화막(doped silicate glass layer)으로 형성할 수도 있다. 이어서, 상기 패드질화막 패턴(5)이 노출될 때까지 상기 CVD 산화막을 에치백(etch-back) 공정 또는 화학기계적 연마(CMP) 공정으로 평탄화시키어 트렌치 영역(T) 내에 CVD 산화막 패턴(11)을 형성한다.3 is a cross-sectional view for explaining a step of forming the etch stop liner 9 and the CVD oxide film pattern 11. Specifically, by performing a plasma treatment on the resultant product in which the oxide liner 7 is formed in a gas atmosphere containing nitrogen, an etch stop liner having a high etching selectivity with respect to the oxide layer etching solution on the surface of the oxide liner 7 ( 9), that is, a silicon oxynitride film is selectively formed. The nitrogen-containing gas is preferably any one selected from N 2 O gas, NO gas and ammonia (NH 3 ) gas. Next, a CVD oxide film filling the trench region T is formed on the entire surface of the resultant in which the etch stop liner 9 is formed. In this case, the CVD oxide film is preferably formed of a material film having excellent step coverage in order to completely fill the trench region T. The material layer having excellent step coverage may be formed of an undoped silicate glass layer such as an O 3 -TEOS (Ozone-TetraEthylOrthoSilicate) film, a PSG (PhosphoSilicate Glass) film, or BPSG (BoroPhosphoSilicate Glass). It may be formed of a doped silicate glass layer such as a film. Subsequently, the CVD oxide layer is planarized by an etch-back process or a chemical mechanical polishing (CMP) process until the pad nitride layer pattern 5 is exposed, thereby forming the CVD oxide layer pattern 11 in the trench region T. Form.
도 4는 리세스된(recessed) CVD 산화막 패턴(11a)을 형성하는 단계를 설명하기 위한 단면도이다. 좀 더 상세히 설명하면, 상기 노출된 패드질화막 패턴(5)을 화학용액, 예컨대 인산용액으로 제거하여 패드산화막 패턴(3)을 노출시킨다. 다음에, 상기 노출된 패드산화막 패턴(3)을 불산용액(hydrofluoric acid) 또는 완충 산화막 식각용액(BOE; Buffered Oxide Etchant)으로 제거하여 트렌치 영역들 사이의 활성영역 표면을 노출시킨다. 이때, 반도체기판 전체에 걸친 모든 활성영역 표면을 완전히 노출시키기 위하여 상기 패드산화막 패턴(3)은 과도식각 공정으로 제거하여야 한다. 이에 따라, 도 4에 도시된 바와 같이 CVD 산화막 패턴(11)이 식각되어 그 크기가 작아진 리세스된 CVD 산화막 패턴(11a)이 형성된다. 그러나, 패드산화막 패턴(3)을 과도한 식각공정으로 제거할지라도, 상기 트렌치 영역의 측벽에 형성된 산화막 라이너(7)는 식각되지 않는다. 이는, 산화막 라이너(7)의 표면을 덮는 식각저지 라이너(9)가 산화막 식각용액, 즉 불산용액 또는 완충 산화막 식각용액에 대하여 높은 식각 선택비를 갖고 있기 때문이다. 따라서, 리세스된 CVD 산화막 패턴(11a)을 형성한 후에 상기 식각저지 라이너(9)의 상부측벽(upper sidewall)은 노출될지라도, 트렌치 영역의 측벽은 산화막 라이너(7) 및 식각저지 라이너(9)에 의해 덮여져 있다.4 is a cross-sectional view for explaining a step of forming a recessed CVD oxide film pattern 11a. In more detail, the exposed pad nitride layer pattern 5 is removed with a chemical solution such as a phosphoric acid solution to expose the pad oxide layer pattern 3. Next, the exposed pad oxide layer pattern 3 is removed with hydrofluoric acid or buffered oxide etchant (BOE) to expose the active region surfaces between the trench regions. In this case, in order to completely expose all active surface surfaces of the entire semiconductor substrate, the pad oxide layer pattern 3 should be removed by an overetch process. Accordingly, as shown in FIG. 4, the CVD oxide pattern 11 is etched to form a recessed CVD oxide pattern 11a having a smaller size. However, even if the pad oxide film pattern 3 is removed by an excessive etching process, the oxide film liner 7 formed on the sidewall of the trench region is not etched. This is because the etch stop liner 9 covering the surface of the oxide film liner 7 has a high etching selectivity with respect to the oxide film etching solution, that is, the hydrofluoric acid solution or the buffer oxide film etching solution. Thus, although the upper sidewall of the etch stop liner 9 is exposed after the recessed CVD oxide pattern 11a is formed, the sidewalls of the trench region are the oxide liner 7 and the etch stop liner 9. Covered by).
도 5는 본 발명에 따른 트렌치 소자분리 방법을 적용하여 모스 트랜지스터를 형성하는 단계를 설명하기 위한 단면도이다. 좀 더 구체적으로 설명하면, 상기 활성영역 표면에 게이트 산화막(13)을 형성하고, 상기 게이트 산화막(13)의 소정영역 상을 지나는 게이트 전극(15)을 형성한다. 이와 같이 형성된 게이트 전극(15)은 도 5의 C로 표시한 부분에 도시된 바와 같이 식각저지 라이너(9)의 상부측벽을 덮는다. 이에 따라, 게이트 전극(15) 및 트렌치 영역(T)의 측벽 사이에 산화막 라이너(7) 및 식각저지 라이너(9)가 개재된 형태를 보인다. 여기서, 상기 게이트 산화막은 통상적으로 고집적 반도체소자에 적합한 두께, 예컨대 50Å 내지 80Å의 두께로 형성한다. 따라서, 산화막 라이너(7)가 게이트 산화막(13)에 비하여 두꺼우므로 게이트 전극(15)에 문턱전압이 인가된 상태에서 상기 활성영역 표면에는 채널이 형성되는 반면에 상기 트렌치 영역의 측벽에는 채널이 형성되는 것을 방지할 수 있다. 결과적으로, 채널 누설전류를 발생시키는 역협폭 효과를 억제시킬 수 있으므로 모스 트랜지스터의 특성을 개선시킬 수 있다.5 is a cross-sectional view for explaining a step of forming a MOS transistor by applying a trench device isolation method according to the present invention. In more detail, the gate oxide layer 13 is formed on the surface of the active region, and the gate electrode 15 passing over the predetermined region of the gate oxide layer 13 is formed. The gate electrode 15 formed as described above covers the upper side wall of the etch stop liner 9 as shown in the portion indicated by C in FIG. 5. Accordingly, the oxide liner 7 and the etch stop liner 9 are interposed between the gate electrode 15 and the sidewalls of the trench region T. Here, the gate oxide film is typically formed to a thickness suitable for a highly integrated semiconductor device, for example, 50 kPa to 80 kPa. Therefore, since the oxide liner 7 is thicker than the gate oxide layer 13, a channel is formed on the surface of the active region while a threshold voltage is applied to the gate electrode 15, while a channel is formed on the sidewall of the trench region. Can be prevented. As a result, the reverse narrowing effect that generates the channel leakage current can be suppressed, so that the characteristics of the MOS transistor can be improved.
본 발명은 상기 실시예에 한정되지 않고 당업자의 수준에서 그 변형 및 개량이 가능하다.The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.
상기한 바와 같이 본 발명에 따르면, 활성영역을 완전히 노출시키기 위하여 상기 패드질화막 및 상기 패드산화막을 과도한 식각공정으로 제거할지라도 트렌치 영역의 측벽이 노출되는 것을 방지할 수 있다. 이에 따라, 모스 트랜지스터의 역협폭 효과에 기인하는 채널누설전류 특성을 개선시킬 수 있다.As described above, even if the pad nitride film and the pad oxide film are removed by an excessive etching process in order to completely expose the active region, the sidewalls of the trench region may be prevented from being exposed. As a result, it is possible to improve the channel leakage current characteristic due to the reverse narrowing effect of the MOS transistor.
Claims (14)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100338767B1 (en) * | 1999-10-12 | 2002-05-30 | 윤종용 | Trench Isolation structure and semiconductor device having the same, trench isolation method |
KR20030021011A (en) * | 2001-09-05 | 2003-03-12 | 동부전자 주식회사 | Method for providing an oxynitride layer in a shallow trench isolation |
KR100801724B1 (en) * | 2001-12-18 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming isolation of semiconductor device |
WO2017116046A1 (en) | 2015-12-29 | 2017-07-06 | 장영철 | Delivery method for enabling advertisement of delivery orderer |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100338767B1 (en) * | 1999-10-12 | 2002-05-30 | 윤종용 | Trench Isolation structure and semiconductor device having the same, trench isolation method |
US6465866B2 (en) | 1999-10-12 | 2002-10-15 | Samsung Electronics Co., Ltd. | Trench isolation regions having trench liners with recessed ends |
KR20030021011A (en) * | 2001-09-05 | 2003-03-12 | 동부전자 주식회사 | Method for providing an oxynitride layer in a shallow trench isolation |
KR100801724B1 (en) * | 2001-12-18 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming isolation of semiconductor device |
WO2017116046A1 (en) | 2015-12-29 | 2017-07-06 | 장영철 | Delivery method for enabling advertisement of delivery orderer |
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