KR19990057378A - Method of forming device isolation film of semiconductor device - Google Patents
Method of forming device isolation film of semiconductor device Download PDFInfo
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- KR19990057378A KR19990057378A KR1019970077429A KR19970077429A KR19990057378A KR 19990057378 A KR19990057378 A KR 19990057378A KR 1019970077429 A KR1019970077429 A KR 1019970077429A KR 19970077429 A KR19970077429 A KR 19970077429A KR 19990057378 A KR19990057378 A KR 19990057378A
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- silicon nitride
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000002955 isolation Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 125000006850 spacer group Chemical group 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 실리콘 질화막 스페이서 하부에 다결정실리콘을 형성하여 소자분리 산화막 형성시 상기 다결정실리콘도 동시에 산화시켜줌으로써 소자분리 산화막과 반도체기판의 경계부분에 수직 단차를 제거하여 게이트 산화막을 정상적으로 성장시켜 반도체소자의 공정수율 및 소자 동작의 신뢰성을 향상시키고, 질화막에 의해 반도체기판에 격자결함이 발생되는 것을 방지하여 상기 격자결함에 의해 누설전류가 발생하는 것을 방지하는 기술이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, wherein a polycrystalline silicon is formed under a silicon nitride film spacer to simultaneously oxidize the polycrystalline silicon at the time of forming a device isolation oxide, thereby forming a vertical step at the boundary between the device isolation oxide film and the semiconductor substrate. Technology to improve the process yield and the reliability of device operation by removing the gate oxide film normally by removing the gate oxide film, and prevent the occurrence of leakage current by the lattice defect by preventing the lattice defect from occurring in the semiconductor substrate by the nitride film to be.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 소자분리 산화막 형성시 실리콘 질화막 스페이서 하부에 다결정실리콘을 형성시켜 활성영역과 소자분리막간의 연결부위의 단차를 줄여 접합 누설전류를 최소화하고, 실리콘 질화막에 의한 스트레스를 줄여 반도체기판의 격자결합에 의해 누설전류가 발생하는 것을 방지하는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation layer of a semiconductor device, and in particular, polycrystalline silicon is formed under a silicon nitride spacer when forming a device isolation oxide layer, thereby minimizing junction leakage current by reducing a step difference between an active region and a device isolation layer. The present invention relates to a technique for reducing a stress caused by a nitride film and preventing leakage current due to lattice coupling of a semiconductor substrate.
일반적으로 반도체소자는 트랜지스터나 커패시터 등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작이 서로 방해되지 않도록 활성 영역들을 분리하는 소자분리 영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region in which devices such as a transistor or a capacitor are formed, and an isolation region separating the active regions so that the operation of the devices does not interfere with each other.
최근 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리 영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, with the trend toward higher integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.
이러한 소자분리 영역의 제조방법으로는 질화막 패턴을 마스크로 하여 반도체기판을 연산화시키는 통상의 로코스(local oxidation of silicon : 이하 LOCOS 라 함)방법이나 반도체기판에 트렌치를 형성하고 이를 절연물질로 매립하는 트렌치분리 등의 방법이 사용되고 있으며, 그 중 LOCOS 방법은 비교적 공정이 간단하여 널리 사용되지만 소자분리 면적이 크고, 경계면에 버즈빅이 생성되어 기판 스트레스(stress) 에 의한 격자결함이 발생되는 단점이 있다.As a method of manufacturing the device isolation region, a conventional local oxidation of silicon (hereinafter referred to as LOCOS) method of computing a semiconductor substrate using a nitride film pattern as a mask, or forming a trench in a semiconductor substrate and filling it with an insulating material Trench separation is used, and LOCOS method is widely used because of its relatively simple process, but has a large device separation area, and has a disadvantage of generating lattice defects due to substrate stress due to the generation of buzz big at the interface. .
상기 LOCOS 필드산화막의 제조방법을 첨부된 도면을 참고로 하여 살펴보면 다음과 같다.Looking at the LOCOS field oxide film manufacturing method with reference to the accompanying drawings as follows.
도 1 a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
먼저, 반도체기판(11)의 상부에 패드산화막(도시안됨)을 형성한다.First, a pad oxide film (not shown) is formed on the semiconductor substrate 11.
다음, 상기 패드산화막 상부에 제1질화막(도시안됨)을 증착한다.Next, a first nitride layer (not shown) is deposited on the pad oxide layer.
그 다음, 상기 제1질화막 상부에 제1감광막(도시안됨)을 도포한다.Next, a first photosensitive film (not shown) is applied on the first nitride film.
그 후, 소자분리 마스크를 이용한 노광 및 현상공정을 실시하여 제1감광막 패턴을 형성한다.Thereafter, an exposure and development process using an element isolation mask is performed to form a first photosensitive film pattern.
이어서, 상기 제1감광막 패턴을 식각마스크로 사용하여, 상기 제1질화막 및 패드산화막을 패터닝한다.Subsequently, the first nitride film and the pad oxide film are patterned by using the first photoresist pattern as an etching mask.
그리고, 상기 제1감광막 패턴을 제거하고, 상기 구조 상부에 제2질화막을 증착한다.The first photoresist layer pattern is removed, and a second nitride layer is deposited on the structure.
그 다음, 상기 제2질화막은 전면식각공정을 실시하여 상기 제1질화막의 측벽에 제2질화막 스페이서를 형성한다.Next, the second nitride film is subjected to an entire surface etching process to form a second nitride film spacer on the sidewall of the first nitride film.
그 후, 상기 일정 두께의 반도체기판(11)을 식각한다.Thereafter, the semiconductor substrate 11 having the predetermined thickness is etched.
이어서, 상기 노출된 반도체기판(11) 상부에 산화시켜 소자분리 산화막(13)을 형성한다.Subsequently, the device isolation oxide layer 13 is formed by oxidation on the exposed semiconductor substrate 11.
다음, 상기 제1질화막 및 제2질화막 스페이서를 습식식각공정으로 제거한다(도 1a 참조).Next, the first nitride film and the second nitride film spacer are removed by a wet etching process (see FIG. 1A).
그 다음, 전 공정에 의해 발생한 화이트 리본(White ribbon)의 제거와 후속공정으로 형성되는 게이트 산화막의 질을 향상시키기 위하여 반도체기판(11)을 희생산화시켜 희생산화막(도시안됨)을 형성시킨다.Then, the sacrificial oxide film (not shown) is formed by sacrificial oxidation of the semiconductor substrate 11 to remove the white ribbon generated by the previous process and to improve the quality of the gate oxide film formed by the subsequent process.
이때, 상기 활성영역은 산화되지만 소자분리영역 상부에는 실리콘성분이 없기 때문에 산화가 되지 않는다.At this time, the active region is oxidized but does not oxidize because there is no silicon component on the device isolation region.
상기와 같은 이유로 상기 희생산화막을 제거하는 후속 세정공정시 상기 소자분리 산화막(13)도 동시에 식각되어 활성영역의 끝부분이 ⓐ 부분과 같이 단차가 크게 발생한다.For the same reason, in the subsequent cleaning process of removing the sacrificial oxide film, the device isolation oxide film 13 is also simultaneously etched so that the end of the active region has a large step like the ⓐ portion.
다음, 게이트 산화막(15)을 형성한 후, 워드라인(17)을 형성한다(도 1b 참조).Next, after the gate oxide film 15 is formed, a word line 17 is formed (see FIG. 1B).
상기와 같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 질화막의 두께가 두꺼울수록 소자분리 산화막과 반도체기판의 경계 부분 아래쪽의 반도체기판 또는 활성영역 아래쪽에 격자결함(19)이 발생하여 그로 인한 누설전류가 발생하게 된다(도 1a 참조). 또한, 상기 소자분리 산화막과 반도체기판의 경게부분에는 질화막 제거공정, 희생산화 등의 후속공정에 의해 단차가 발생하고, 상기 단차가 발생한 부분의 반도체기판에는 소자분리 산화막 형성시 스트레스를 많이 받는 곳으로서, 게이트 산화막 형성시 산화막이 비정상적으로 성장되어 질적으로 저하되고, 게이트 전극이 패터닝 불량 또는 단선 등이 발생되는 문제점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the related art, as the thickness of the nitride film becomes thicker, lattice defects 19 occur below the semiconductor substrate or the active region below the boundary between the device isolation oxide film and the semiconductor substrate. A leakage current is generated (see FIG. 1A). In addition, the stepped portion is formed in the light emitting portion of the device isolation oxide film and the semiconductor substrate by a subsequent process such as a nitride film removing process or a sacrificial oxidation, and the semiconductor substrate in the portion where the step occurs has a high stress when forming the device isolation oxide film. When the gate oxide film is formed, the oxide film is abnormally grown and degraded in quality, so that the gate electrode is poor in patterning or disconnection.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 활성영역의 질화막 하부에 다결정실리콘을 형성하여 질화막에 의한 스트레스에 의해 반도체기판 내부에 격자결함이 발생되어 누설전류가 발생하는 것을 방지하고, 소자분리막과 활성영역의 접합부분에서 단차를 줄임으로써 상기 접합부분에서의 누설전류를 최소화시키는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, polycrystalline silicon is formed below the nitride film of the active region to prevent lattice defects from being generated inside the semiconductor substrate due to stress of the nitride film, thereby preventing leakage current. An object of the present invention is to provide a method of forming a device isolation layer of a semiconductor device which minimizes leakage current at the junction by reducing a step at a junction between the separator and the active region.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 내지 도 2h 는 본 발명의 제1실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.2A to 2H are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device in accordance with a first embodiment of the present invention.
도 3a 내지 도 3d 는 본 발명의 제2실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.3A to 3D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device in accordance with a second embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명 ><Description of the code for the main part of the drawing>
11, 12, 40 : 반도체기판 13, 26 : 소자분리 산화막11, 12, 40: semiconductor substrate 13, 26: device isolation oxide film
14, 42 : 패드산화막 15, 28 ; 게이트 산화막14, 42: pad oxide films 15, 28; Gate oxide
16 : 제1감광막 패턴 17 : 워드라인16: first photosensitive film pattern 17: word line
18, 44 : 다결정 실리콘 19 : 격자결함18, 44 polycrystalline silicon 19: lattice defect
20 : 제2감광막 패턴 22, 46 : 제1실리콘 질화막20: second photosensitive film pattern 22, 46: first silicon nitride film
24, 48 : 제2실리콘 질화막 스페이서24, 48: second silicon nitride film spacer
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은,Device isolation film forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 패드절연막패턴을 형성하는 공정과,Forming a pad insulating film pattern on the semiconductor substrate;
상기 패드절연막 패턴 상부에 다결정실리콘을 형성하는 공정과,Forming polycrystalline silicon on the pad insulating film pattern;
상기 다결정실리콘 상부에 활성영역을 노출시키는 제1감광막패턴을 형성하는 공정과,Forming a first photoresist film pattern exposing an active region on the polycrystalline silicon;
상기 제1감광막패턴을 마스크로 하여 상기 다결정실리콘을 일정두께 식각하고 상기 제1감광막패턴을 제거하는 공정과,Etching the polycrystalline silicon by a predetermined thickness using the first photoresist pattern as a mask and removing the first photoresist pattern;
상기 다결정실리콘 상부에 소자분리영역을 노출시키는 제1실리콘질화막을 형성하는 공정과,Forming a first silicon nitride film exposing the device isolation region on the polycrystalline silicon;
상기 제1실리콘질화막 측벽에 제2실리콘질화막 스페이서를 형성하는 공정과,Forming a second silicon nitride film spacer on the sidewalls of the first silicon nitride film;
상기 제1실리콘질화막 및 제2실리콘질화막 스페이서를 마스크로하여 상기 다결정실리콘을 식각하되, 과도식각을 수반하는 공정과,Etching the polysilicon using the first silicon nitride film and the second silicon nitride film spacer as a mask, but including a transient etching;
상기 반도체기판을 열산화시켜 소자분리막을 형성하는 공정과,Thermally oxidizing the semiconductor substrate to form an isolation layer;
상기 제1실리콘질화막 및 제2실리콘질화막 스페이서을 제거하는 공정을 포함하는 것을 제1특징으로 한다.It is a 1st characteristic that it includes the process of removing the said 1st silicon nitride film and the 2nd silicon nitride film spacer.
또한, 이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In addition, the device isolation film forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 패드산화막, 다결정실리콘 및 제1실리콘 질화막을 순차적으로 형성하는 공정과,Sequentially forming a pad oxide film, a polycrystalline silicon, and a first silicon nitride film on the semiconductor substrate;
상기 반도체기판의 소자분리마스크를 이용한 식각공정으로 상기 제1실리콘질화막 및 일정두께의 다결정실리콘을 식각하는 공정과,Etching the first silicon nitride film and polycrystalline silicon of a predetermined thickness by an etching process using an element isolation mask of the semiconductor substrate;
상기 제1실리콘질화막의 식각된 측벽에 제2실리콘질화막 스페이서를 형성하는 공정과,Forming a second silicon nitride film spacer on the etched sidewall of the first silicon nitride film;
상기 제1실리콘질화막 및 제2실리콘질화막 스페이서를 마스크로하여 상기 다결정실리콘, 패드산화막 및 일정두께의 반도체기판을 식각하되, 과도식각을 수반하는 공정과,Etching the polysilicon, the pad oxide film, and the semiconductor substrate having a predetermined thickness using the first silicon nitride film and the second silicon nitride film spacer as a mask, but including an excessive etching;
상기 반도체기판을 열산화시켜 소자분리막을 형성하는 공정과,Thermally oxidizing the semiconductor substrate to form an isolation layer;
상기 제1실리콘질화막 및 제2실리콘질화막 스페이서를 제거하는 공정을 포함하는 것을 제2특징으로 한다.It is a 2nd characteristic that it includes the process of removing the said 1st silicon nitride film | membrane and the 2nd silicon nitride film spacer.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h 는 본 발명의 제1실시예에 의한 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.2A to 2H are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to a first embodiment of the present invention.
먼저, 반도체기판(12)의 상부에 패드산화막(14)을 형성하고, 그 상부에 소자분리 영역으로 예정된 부분의 반도체기판(12)을 노출시키는 제1감광막 패턴(16)을 형성한다. 여기서, 상기 패드산화막(14)은 질소성분을 함유한다.First, a pad oxide film 14 is formed on the semiconductor substrate 12, and a first photoresist film pattern 16 is formed on the semiconductor substrate 12 to expose the semiconductor substrate 12 in a predetermined portion as a device isolation region. Here, the pad oxide film 14 contains a nitrogen component.
그리고, 상기 제1감광막 패턴(16)을 식각마스크로 사용하여 상기 패드산화막(14)을 식각한다(도 2a참조).The pad oxide layer 14 is etched using the first photoresist layer pattern 16 as an etching mask (see FIG. 2A).
다음, 상기 제1감광막 패턴(16)을 제거하고, 상기 구조 표면에 다결정실리콘(18)을 형성한다.Next, the first photoresist layer pattern 16 is removed, and polysilicon 18 is formed on the surface of the structure.
그 다음, 상기 다결정실리콘(18)상부에 소자분리 영역을 보호하는 제2감광막 패턴(18)을 형성하고, 상기 제2감광막 패턴(20)을 식각마스크로 사용하여 상기 다결정실리콘(18)을 일정 두께 식각한다. 여기서, 상기 제2감광막 패턴(20)은 네가티브 감광막을 사용한다(도 2b참조).Next, a second photoresist layer pattern 18 is formed on the polysilicon layer 18 to protect the device isolation region, and the polysilicon layer 18 is fixed using the second photoresist layer pattern 20 as an etching mask. Etch thickness. Here, the second photoresist film pattern 20 uses a negative photoresist film (see FIG. 2B).
다음, 상기 제2감광막 패턴(20)을 제거하고, 상기 구조 상부에 소자분리 영역을 노출시키는 제1실리콘 질화막 패턴(22)을 형성한다(도 2c참조).Next, the second photoresist layer pattern 20 is removed, and a first silicon nitride layer pattern 22 exposing the device isolation region is formed on the structure (see FIG. 2C).
그 다음, 상기 제1실리콘 질화막 패턴(22)의 측벽에 제2실리콘 질화막 스페이서(24)를 형성한다. 여기서, 상기 제2실리콘 질화막 스페이서(24)는 산화막 또는 질화막으로 형성할 수 있다(도 2d참조).Next, a second silicon nitride film spacer 24 is formed on sidewalls of the first silicon nitride film pattern 22. The second silicon nitride film spacer 24 may be formed of an oxide film or a nitride film (see FIG. 2D).
다음, 상기 제1실리콘 질화막 패턴(22) 및 제2실리콘 질화막 스페이서(24)를 식각마스크로 사용하여 상기 소자분리 영역으로 예정되어 있는 다결정실리콘(18) 및 일정 두께의 반도체기판(12)을 식각한다(도 2e참조).Next, by using the first silicon nitride film pattern 22 and the second silicon nitride film spacer 24 as an etching mask, the polysilicon 18 and the semiconductor substrate 12 having a predetermined thickness are etched. (See FIG. 2E).
그 다음, 상기 노출된 반도체기판(12) 상부를 산화시켜 소자분리 산화막(26)을 형성한다(도 2f참조).Then, the exposed semiconductor substrate 12 is oxidized to form an isolation oxide layer 26 (see FIG. 2F).
다음, 상기 제1실리콘 질화막 패턴(22) 및 제2실리콘 질화막 스페이서(24)를 제거한다.Next, the first silicon nitride film pattern 22 and the second silicon nitride film spacer 24 are removed.
그 다음, 전 공정에 의해 발생한 화이트 리본(white ribbon)의 제거와 후속 공정으로 형성되는 게이트 산화막의 질을 향상시키기 위하여 반도체기판(12)을 희생산화시켜 희생산화막(도시안됨)을 형성시킨다.Then, the sacrificial oxide film (not shown) is formed by sacrificial oxidation of the semiconductor substrate 12 in order to remove the white ribbon generated by the previous process and to improve the quality of the gate oxide film formed by the subsequent process.
그 후, 상기 희생산화막을 제거하는 세정공정을 실시한다(도 2g참조).Thereafter, a washing step of removing the sacrificial oxide film is performed (see FIG. 2G).
그 다음, 산화공정을 실시하여 게이트 산화막(28)을 형성한다(도 2h참조).Then, an oxidation process is performed to form a gate oxide film 28 (see Fig. 2H).
도 3a 내지 도 3d는 본 발명의 제2실시예에 의한 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 반도체기판(40) 상부에 패드산화막(42), 다결정실리콘(44) 및 제1실리콘 질화막(46)을 형성한다(도 3a참조).First, a pad oxide film 42, a polycrystalline silicon 44, and a first silicon nitride film 46 are formed on the semiconductor substrate 40 (see FIG. 3A).
다음, 상기 제1실리콘 질화막(46) 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the first silicon nitride layer 46 to expose a predetermined portion as a device isolation region.
그 다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 제1실리콘 질화막(46) 및 일정두께의 다결정실리콘(44)을 식각하고, 상기 감광막 패턴을 제거한다(도 3b참조).Next, the first silicon nitride film 46 and the polysilicon 44 having a predetermined thickness are etched using the photoresist pattern as an etching mask, and the photoresist pattern is removed (see FIG. 3B).
다음, 상기 제1실리콘 질화막(46) 및 다결정실리콘(44)의 측벽에 제2실리콘 질화막 스페이서(48)를 형성한다(도 3c참조).Next, a second silicon nitride film spacer 48 is formed on the sidewalls of the first silicon nitride film 46 and the polycrystalline silicon 44 (see FIG. 3C).
그 다음, 상기 제1실리콘 질화막(46) 및 제2실리콘 질화막 스페이서(48)를 식각마스크로 사용하여 상기 다결정실리콘(44), 패드산화막(42) 및 일정두께의 반도체기판(40)을 식각한다(도 3d참조).Next, the polysilicon 44, the pad oxide film 42, and the semiconductor substrate 40 having a predetermined thickness are etched using the first silicon nitride film 46 and the second silicon nitride film spacer 48 as an etching mask. (See FIG. 3D).
그리고, 상기 제1실시예의 도 2f 의 후속공정과 동일한 공정을 실시하여 소자분리 산화막을 형성하면, 상기 제2실리콘 질화막 스페이서 아래 부분의 다결정실리콘의 양을 줄여줄 수 있기 때문에 수직 단차를 줄여줌과 동시에 산화막 형성시 산화되는 다결정 실리콘 양이 적기 때문에 새부리 모양의 산화막이 활성영역 내부로 적게 치고 들어가게 해줄 수 있으므로 소자분리 산화막 영역의 면적의 증가를 막아줌으로써 활성영역의 면적 확보를 해줄 수 있는 장점이 있다.In addition, when the device isolation oxide film is formed by performing the same process as the subsequent process of FIG. 2F of the first embodiment, the amount of polysilicon under the second silicon nitride film spacer can be reduced, thereby reducing the vertical step. At the same time, since the amount of polycrystalline silicon oxidized during the formation of the oxide film is small, the beak-shaped oxide film can be made to enter the active area less, thereby preventing the increase of the area of the device isolation oxide area, thereby securing the area of the active area. .
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 실리콘 질화막 스페이서 하부에 다결정실리콘을 형성하여 소자분리 산화막 형성시 상기 다결정실리콘도 동시에 산화시켜줌으로써 소자분리 산화막과 반도체기판의 경계부분의 수직단차를 제거하여 게이트 산화막을 정상적으로 성장시켜 반도체소자의 공정수율 및 소자 동작의 신뢰성을 향상시키고, 질화막에 의해 반도체기판에 격자결함이 발생되는 것을 방지하여 상기 격자결함에 의해 누설전류가 발생하는 것을 방지하는 이점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, a polycrystalline silicon is formed under a silicon nitride film spacer to simultaneously oxidize the polycrystalline silicon when the device isolation oxide film is formed, thereby forming a boundary between the device isolation oxide film and the semiconductor substrate. The gate oxide film is grown normally by removing the vertical step to improve the process yield and reliability of the operation of the semiconductor device, and prevent the lattice defects from occurring in the semiconductor substrate by the nitride film. There is an advantage to prevent that.
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| KR0139267B1 (en) * | 1994-12-29 | 1998-06-01 | 김주용 | Forming method of field oxide in a semicondcutor device |
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