KR19990057325A - Folded bit line sensing device - Google Patents

Abstract

The present invention relates to a folded bit line sensing device for a semiconductor memory device, and more particularly to a DRAM capable of sensing / restoring folded bit line by setting the cell area to 6 F.F., It consists of two sense amplifiers, three bit lines connecting them, a control switch for adjusting the connection between the cell array and the sense amplifier, and a connection switch for dividing the cell array into two parts at the center of the cell array The chip area is reduced and the sensing margin is improved.

Description

Folded bit line sensing device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a folded bit line sensing device for a semiconductor memory device, and more particularly, to a folded bit line sensing device capable of sensing / restoring folded bit lines with an area of a cell of 6F / .

In general, 1Gb-DRAM was introduced to the Gb-scale area in 1996 with the announcement of ISSCC.

Since such a Gb-DRAM needs to be manufactured using Deep Sub-Micron technology, an increase in manufacturing cost is a serious problem. In addition, since the chip size is increased to the area of several cm, yield problems arise, and large-sized wafers must be used, resulting in enlargement of manufacturing equipment and high cost.

Therefore, in order to solve such a problem, the chip size must be reduced.

The most effective way to reduce chip size is to reduce cell area.

On the other hand, although it is possible to reduce the chip area by reducing the area of the peripheral circuit, in this case, there is a problem that the characteristics of the circuit deteriorate and much effort is required for routing.

One way to reduce the cell area is to reduce the line dimension, ie, the length and spacing of the lines, and to change the cell layout.

The former requires more advanced technology, which makes the process more difficult and requires an increase in manufacturing cost, while the latter makes it easier to reduce the chip area without burdening the process.

On the other hand, the cell arrangement depends on the sensing method.

1A to 1C show the shape of the cell array and the cell area according to the sensing method.

In the folded bit line (FBL) sensing in FIG. 1A, since the bit line BL and the reference bit line / BL are formed close to each other, the array noise of the cell can be reduced However, the cell area is as large as 8F ² .

Here, " F " refers to a minimum feature size, and " F ² " refers to an area having a minimum form size.

For example, 8F ² means 8 times the area of the smallest size.

In the open bit line (OBL) sensing of FIG. 1B, since the bit line BL and the reference bit line / BL are arranged on both sides of the sense amplifier, the cell area can be reduced to 4F ² However, there arises a problem that the array noise increases.

Therefore, although the FBL sensing method is widely used in spite of the damage on the area due to the noise problem, the OBL sensing method is recently adopted to reduce the cell area.

Here, the cell area assumes a case where the structure of the cell is a conventional structure.

This structure refers to forming a bit line on a capacitor, and is susceptible to noise generated on the bit line and the bit line electrically.

To overcome this problem, a capacitor over bit line (COB) structure is proposed and widely used.

This structure is resistant to bit line noise because the bit line exists under the plate, and is therefore called as a shielded bit line structure. However, this structure has a disadvantage that the cell area is larger than that of the conventional structure, and the OBL sensing increases from 4F ² to 8F ² .

The present invention enables FBL sensing while reducing the area of the COB cell to 6F ² .

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a semiconductor memory device, The present invention is directed to a 6F ^two- fold bit line sensing device.

Figure 1a is a prior art folded bit line sensing block;

1B is an open bit line sensing block diagram according to the prior art.

1C is a 3-bit folded bit line sensing block diagram according to the prior art;

2 is a block diagram of pulley folded bit line sensing / restoring according to an embodiment of the present invention;

FIG. 3A is a block diagram showing the operation relationship in the pre-charge cycle of FIG. 2; FIG.

FIG. 3B is a block diagram showing the operation of charge sharing in FIG. 2; FIG.

FIG. 3C is a configuration diagram illustrating the sensing operation of FIG. 2; FIG.

FIG. 3D is a configuration diagram showing an operation relationship at the time of re-saving of FIG. 2; FIG.

Fig. 4 is a timing chart of the read operation in Fig. 2; Fig.

5A is a circuit diagram of the connection switch signal generator of FIG. 2;

5B is an adjustment switch signal generating circuit of FIG. 2; FIG.

FIG. 6 is an operation timing diagram of FIG. 2; FIG.

Description of the Related Art

20: Sense Amplifier 1 22: Sense Amplifier 2

24: Connection switch 26: Left half adjustment switch

28: Right half control switch 30: Left half counter 6 F /

32: Fifth half of the right half FEP cell 34: Bit line 0 (BL0)

36: bit line 1 (BL1) 38: bit line 2 (BL2)

L0 to L2: Left half adjust switch signal H0 to H2: Right half adjust switch signal

S0 to S2: Connection switch signals W0 to W2: Word line

BLs: Left half bit lines (BL0, BL1, BL2)

In order to achieve the above object, a folded bit line sensing apparatus of the present invention includes three bit lines for connecting sense amplifiers 1 and sense amplifiers 2 present at both ends,

And on the opposite sides of the bit line, there are a left half-half F / F-Frescell portion and a right half-half F-Frescell portion. In the charge distribution mode, the bit line is turned on by a connection switch signal, A connection switching means for connecting the corresponding bit line by the connection switch signal,

And is connected to the sense amplifier 1 and connected to the left half of the F-Fresnel unit. The left half is controlled by a left half-adjust switch signal to turn on all three bit lines in the pre-charge mode to connect the three bit lines to the sense amplifier 1, Left half adjusting switching means for connecting any two bit lines to the sense amplifier 1 in the mode,

And is connected to the sense amplifiers 2 and is connected to the sense amplifiers 2. The sense amplifier 2 is connected to the right half 6 F / And a right half adjusting switching unit for connecting any two bit lines to the sense amplifier 2 in a mode.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a Fully False Bit Line Sensing / Restore (FFSR) structure according to an embodiment of the present invention. Referring to FIG. 2, A bit line 0 and a bit line 2 connected between the left half sense amplifier 1 (20) and the right half sense amp 2 (22), and a sense amplifier 1 (20) A bit line 1 connected between a connection point of the left half sense amplifier 1 (20) and the bit line 2 and a connection point of the right half sense amplifier 2 (22) and the bit line 0; a sense amplifier 1 A connection switch 24 for turning on / off the left half and the right half of the bit line 0, the bit line 1 and the bit line 2 connecting the connection switch 22 and the connection switch 24, The left half of the 6-cell FEP consisting of 6 cells activated by the word line signal The left semi-adjustable switch 26 connected between the sense amplifier 1 (20) and the left half-half F-Fres cell, the right half F-F / F cell and the sense amp 2, and a right half-adjustment switch 28 connected between the first and second switches 22 and 22.

The connection switch 24 is composed of three NMOS transistors connected to the bit line 0, the bit line 1 and the bit line 2, respectively, to which gate connection switch signals S0, S1 and S2 are applied.

The left half of the Fifth Fifth cell and the right half of the Fifth FPC are connected to the bit line 0 and the connection point of the bit line 1 and the word line 0, the bit line 1 and the connection point of the bit line 2 and the word line 1, Cells are arranged at the connection point of line 2 and word line 2.

The left half adjust switch 26 is composed of three NMOS transistors connected to the bit line 0, the bit line 1 and the bit line 2 respectively and to which the left semi-adjust switch signals L0, L1 and L2 are applied to the gates, respectively.

The right half control switch 28 is composed of three NMOS transistors connected to the bit line 0, the bit line 1 and the bit line 2, respectively, to which the right half regulating switch signals H0, H1 and H2 are applied as gates, respectively

That is, in the configuration of the present invention, two cells are arranged in series and one insulating region is provided, and sense amplifiers are provided at both ends of the cell array, and each sense amplifier is connected to three bit lines.

Between the cell array and the amplifier there are control switches that can control their connection, which are controlled by the L0 to L2 and H0 to H2 signals, respectively.

At the center of the cell array is a connection switch 24 that divides the cell array into two parts.

The cell array has 6F ² cell areas because there are one insulated area in ^two cells.

This is easy to see when compared to the existing FBL array with one insulated area per cell and a cell area of 8F ² .

6F The concept of FBL sensing in ² cell array is as follows.

Assuming that word line 0 (W0) is activated, two cells dependent on word line 0 (W0) are activated. These two cells are cells which depend on the bit line 0 (BL0) 34 and the bit line 1 (BL1) 36. The cell of the bit line 0 (BL0) 34 is connected to the sense amplifier 1 The left half of the bit line 2 (BL2) 38 is sensed as the reference bit line / BL and the cells of the bit line 1 (BL1) 36 are sensed by the sense amplifier 2 (22) 38) to the reference bit line (/ BL).

The bit line 2 (BL2) 38 is divided in half into the reference bit line (/ BL) of the sense amplifier 1 (20) and the sense amplifier 2 (22).

FIG. 3A shows operation states of respective components in the pre-charge mode according to the present invention having the configuration of FIG.

Hereinafter, FIG. 3B shows the charge distribution, FIG. 3C shows the sensing, and FIG. 3D shows the operation state of the present invention in the re-storing mode, which will be described below with reference to the operation timing chart of FIG.

Here, the solid line shown in Figs. 3A to 3D is an activated part, and the dotted line indicates a non-activated state.

First, in the precharge mode, both the left half control switch 26 and the right half control switch 28 are closed and the precharge signal is activated with the connection switch 24 opened to make the bit lines the same.

At this time, the above operation may be performed with the connection switch 24 closed.

The state of each signal for this is shown in Fig.

BLs in FIG. 4 represents a left half bit line.

Next, in the charge distribution mode (FIG. 3B) in which the data of the cell is loaded on the bit line, both the left half and right half control switches 28 are opened and word line 0 (WL0) is activated after all the connection switches 24 are closed .

Here, it is assumed that cell "0" and cell "1" are stored at the connection point between bit line 0 and bit line 1 and word line 0, respectively.

Then, the data of the cell " 0 " is written to the bit line 0 (BL0) 34 and the data of the cell " 1 "

That is, since the potentials of the bit line 0 (BL0) 34 and the bit line 1 (BL1) 36 are changed by the data of the cell, and the bit line 2 (BL2) Gt; Vcc. ≪ / RTI >

An operation timing chart for this is shown in Fig.

In the sensing mode (FIG. 3C), all of the connection switches 24 are opened and the left half control switch signals L0 and L2 are closed in the control switches so that the left half of the bit line 0 and the bit line 2 are connected to the sense amplifier 1 (20) Similarly, the right half regulating switch signals H1 and H2 are closed so that the right half of the bit line 1 and the bit line 2 are connected to the sense amplifier 2 (22). The data of the cell " 0 " is loaded in the left half of the bit line 0 and the data of the cell " 1 " is loaded in the right half of the bit line 1, and the left half and the right half of the bit line 2 are connected to the reference bit line / And FBL sensing is performed.

That is, after the activation signal of the sense amplifier, the left half of bit line 0 and bit line 2 and the right half of bit line 1 and bit line 2 are split into full Vcc and ground.

Thus, the sensing operation is completed by the sense amplifier 1 (20) for the cell "0" and the sense amplifier 2 (22) for the cell "1".

In the re-storing mode (FIG. 3D), only the connection switch signals S0 and S1 among the connection switches 24 are activated while the adjustment switches of FIG. 3C are left.

The cell " 0 " completes the restoration at the same time as the sensing by the sense amplifier 1 (20), but the cell " 1 "

When S1 is open, the right half of bit line 1 is split into Vcc or Ground, but the left half of bit line 1 with cell "1" has a potential of almost 1/2 Vcc. When the connection switch signal S1 is closed, the cell "1" is restored by the sense amplifier 2 (22).

Figure 4 shows a timing diagram of the signals for the above operation.

5A and 5B illustrate a connection switch signal and a left half / right half-adjust switch signal generation circuit used in FIG. 2, wherein FIG. 5A shows a first Noah gate for receiving C1, C2, and C3 signals, A first NAND gate for receiving the NOR gate output signal and the RPE signal as two inputs, a second NOR gate for receiving the CAE signal and the C2 signal, a first inverter for inverting the first NOR gate output signal, A second NAND gate having two inverters output signals and the second NOR gate output signal as two inputs and a second NAND gate output signal and a second NAND gate output signal as two inputs and outputting a connection switch signal gS1 And a third NAND gate.

FIG. 5B is a circuit diagram showing a configuration in which the third Noah gate receiving the C1, C2, and C3 signals, the second inverter inverting the BLP signal, and the second inverter output signal and the third Noah gate output signal, and a fourth NAND gate outputting gL1.

Here, the signals C1, C2, and C3 are obtained by replacing the Lao address with three mode signals. C1 represents mode 0, C2 represents mode 1, and C3 represents mode 2.

In FIG. 5A, Rising of the connection switch 24 uses the RPE signal and Falling uses the CAE signal.

FIG. 6 illustrates a result of a Read operation using the logic shown in FIG. 5, which constitutes the cell array of FIG.

Quot; 1 " in which high data is stored and a cell " 0 " in which low data is stored.

Here, noise occurs at the potential of the bit line 2 because half of the bit line is at Vcc or ground when the connection switch 24 is closed in the re-storing mode, and half of the bit line has a potential of 1/2 Vcc, -Up).

The present invention can improve the operation speed by driving half of the bit line during sensing to reduce the capacitance of the bit line in half.

As described above, the present invention realizes a 6-F / F cell array while maintaining the folded bit line Scheme, thereby improving the sensing margin without increasing the area and reducing the area of the chip.

A further advantage of the present invention is that by driving only half of the bit line during sensing, the capacitance of the bit line is reduced in half to improve the operating speed.

The preferred embodiments of the present invention are for the purpose of illustration and various modifications, alterations, substitutions and additions will occur to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (7)

Connection switching means connected between the left half-half F-Fresnel portion and the right half-half F-Fresnel portion, A left semi-adjustable switching means connected between the left half-half F-Fresnel portion and the one-side sense amplifier, And a right semi-adjustable switching unit connected between the right half F-Fresnel unit and the other side sense amplifier. The method according to claim 1, Wherein the connection switching means is turned on by a connection switch signal in a charge distribution mode to transfer data on a cell to a bit line and to connect the corresponding bit line by the connection switch signal in a re- A folded bit line sensing device. The method according to claim 1, The left semi-adjustable switching means is controlled by a left half-adjust switch signal to turn on all three bit lines in the pre-charge mode to connect the one sense amplifier to the one sense amplifier, And a function of connecting the sense amplifier to the one-side sense amplifier. The method according to claim 1, Wherein the right half control switching means is controlled by a right half control switch signal to turn on all three bit lines in the precharge mode to connect the two sense amplifiers to the other sense amplifier, And a second sense amplifier connected to the second sense amplifier. The method according to claim 1, Wherein the connection switching means, the left half-adjustment switching means and the right half-adjustment switching means are provided using a MOS transistor. The method according to claim 3 or 4, Wherein one of the three bit lines is used as a reference bit line. The method as claimed in claim 2, 3, or 4, Wherein the connection switch signal, the left half-adjust switch signal, and the right half-adjust switch signal are provided using a Noah gate, a NAND gate, and an inverter.