KR19990055839A - The read operation address generator of the block interleaver - Google Patents

Abstract

The present invention relates to an efficient address generator of an interleaver, and more particularly to a block interleaver having n × b (n, m and b are positive integers) The operation address generator is a read operation address generator of a block interleaver consisting of an address counter for generating an address for a block having a combination of a plurality of counters and a bit selection counter for generating an address for a specific bit in the block.

Description

The read operation address generator of the block interleaver

The present invention relates to a circuit for generating an address for reading in a block interleaver.

The interleaver plays a role of random error in the burst error.

Channel coding is generally optimized to overcome errors due to Additive White Gaussian Noise. However, since channel error is likely to occur under a multipath fading channel environment such as mobile communication, it is difficult to overcome the error only by channel coding.

Therefore, the transmitting terminal performs temporal reconstruction of the signal by an interleaver, and the receiving terminal restores the original signal sequence by a deinterleaver. By interleaving / deinterleaving, burst error spreads in time so that errors in one codeword become independent.

1 is a diagram showing a read and write operation of a block interleaver. Here we show, for example, reading and writing 320 bits of data. This indicates the size of the block interleaver used in the synchronous, call / access channel in the current wireless local loop (WLL) standard.

The interleaver writes in the vertical direction and reads in the horizontal direction. As shown in FIG. 1, the writing operation in the vertical direction is sequential, but in order to read in the horizontal direction, it is only necessary to generate a memory address. In order to generate a memory address, it is necessary to find a certain tendency of an address, and an efficient method is needed since this tendency varies with the size of the block interleaver.

Therefore, the present invention proposes an efficient address generation circuit for reading addresses of non-sequential interleavers as described above.

1 is a diagram showing a write / read operation of a block interleaver,

2 is a diagram showing memory address allocation of a block interleaver,

3 is a diagram showing an address generator of a specific block interleaver read operation,

4 is a diagram showing an address generator of a generalized block interleaver read operation.

In order to solve the above-described problems, the present invention provides a read operation address generator for a block interleaver configured with n bits of memory, comprising: an address counter generating an address for a block composed of a plurality of counters; And a bit selection counter for generating the address of the block interleaver.

That is, in the present invention, an n-bit memory is used and an address is generated by selecting one of n bits.

The address generator includes an address counter for generating an address for a block having a combination of a plurality of counters and a bit selection counter for generating an address for a specific bit in the block.

Its generalized overall structure is shown in Fig.

The address and bit selection bits are generated in an address counter and a bit selection counter, respectively, and muxing the address and bit selection bits generates an address of the interleaver.

This will be described in detail as follows.

A block size of n bits, and a total of A × B block interleavers. The memory size n, the number of bits (B1, B2) of two address counters (B1, B2) the number of bits (B3) of the bit selection counter and the determination method thereof will be described.

First, the relationship between the block size n and a is as follows. In other words,

. For example, in the case of WLL synchronous and paging channels, 20 × 16 (320), and for IS-95 traffic channels, 32 × 18 (576).

Next, the number of bits of the counter should be determined, which is as follows.

Here, < x > means a maximum integer smaller than x + 1, for example, < 2.3 > = 3, < 4.1 > = 4 and < 2 &

Here, the total number of bits of the counter is m + <log ₂ m> + <log ₂ n>. It is desirable that the number of these bits is minimized for cost and simplification of the overall control.

To do this, the number of counter bits is calculated for several candidates of n and m, and the most suitable n, m is selected.

For example, in the case of WLL,

.

Therefore, there is a trade-off relationship between the memory size n and the number of bits of the counter (B = B1 + B2 + B3). It is the most efficient way to minimize the sum (n + B) of the two.

As a concrete example of applying the above method, if a 5-bit memory is used to configure the interleaver, the memory address shown in FIG. 2 is allocated for the write operation of the interleaver as shown in FIG.

3 is a circuit for generating a memory address for a read operation for the above-described interleaver. The 4-bit counter in this circuit is the counter for the horizontal increase in the memory address of FIG. After the 4-bit counter increments to " 1111 ", the 3-bit counter increments to select the bit. The Bit_sel signal means a bit to be selected from 5-bit data. The 2-bit counter is incremented by enabling the bit_sel signal of the 3-bit counter indicating "100". This counter is a counter for increasing in the vertical direction in Fig.

The present invention can be configured as a simple circuit as described above, so that the address of the interleaver can be efficiently generated.

Therefore, there is an excellent technical effect which can attain price reduction as well as promptness of processing.

Claims (7)

(N, m, and b are positive integers) composed of one block of n bits of memory, which is a read operation operation address generator of the block interleaver, An address counter for generating an address for a block composed of a plurality of counters; As a bit selection counter for generating an address for a specific bit in a block A Read Synchronization Address Generator for Block Interleaver. The method of claim 1, wherein There are two address counters. Characterized in that the read interworking address generator of the block interleaver. The method according to claim 2, wherein The two address counters are counters for incrementing in the horizontal direction and counters for incrementing in the vertical direction Characterized in that the read interworking address generator of the block interleaver. The method according to claim 2, wherein The address counter consists of an address counter of m bits and an address counter of <log ₂ m> bits (where <x> is the largest integer less than x + 1) Characterized in that the read interworking address generator of the block interleaver. The method of claim 1, wherein The bit selection counter is a bit selection counter of <log ₂ n> bits (where <x> is the largest integer less than x + 1) Characterized in that the read interworking address generator of the block interleaver. The method according to any one of claims 1 to 5, wherein The size of the block (n bits), the size of each address counter, and the size of the bit selection counter are minimized Characterized in that the read interworking address generator of the block interleaver. The method according to claim 1, The block interleaver is used in a synchronous, call / access channel of a 320-bit Wireless Local Loop (WLL) standard in which 5 bits are one block, The address counter consists of a combination of a 4-bit counter and a 2-bit counter, The bit selection counter consists of a 3-bit counter Characterized in that the read interworking address generator of the block interleaver.