KR19990054400A - Semiconductor memory device and program verification method thereof - Google Patents

Abstract

The present invention relates to program verification, and more particularly, to a program verification method capable of verifying even a disturb cell, comprising: a memory cell array for storing data, a first register for storing data of a selected cell, and a second A program verification method for a semiconductor memory device comprising a register and a third register for storing a result of verifying data of a programmed cell, the method comprising: inputting an address; Inputting data to be programmed into the first and second registers, storing data of logic 0 corresponding to the program protection cell and storing program data of logic 1 corresponding to the selected cell; Performing a program operation; Verifying a program cell; Determining whether the selected cells are correctly programmed; When the selected cells are correctly programmed, performing a second program verification; After completion of the second program verify, storing the verified pass data in a third register; Outputting the pass data of the programmed cell, and comparing the maximum number of programs when the selected cells are not properly programmed; Performing a further program when less than the maximum number of programs; Storing fail data in the third register when greater than a maximum number of programs; And outputting whether or not the selected cell is to be failed.

Description

Semiconductor memory device and program verification method

The present invention relates to a program verification method of a semiconductor memory device, and more particularly, to a program verification method capable of detecting a disturb cell.

In general, each cell of an electrically erasable programmable ROM (hereinafter referred to as an EEPROM) has a floating gate so that when a high voltage is applied to the cell, hot electron injection is performed. Charge and accumulation are discharged to the floating gate of the selected cell by Fowler-Nordheim tunneling and program and erase operations are performed. When the program and erase operations are repeatedly performed in the semiconductor memory device, stress is applied to the oxide layer between the floating gate and the channel or between the floating gate and the source and the drain, thereby reducing the reliability of the cell and the overall device. In general, the EEPROM specifies a cycle of 10 ⁵ to 10 ⁶ as a specification according to a program and an erase method, so that the user can refer to it.

Another factor affecting the reliability of the EEPROM is the occurrence of a disturbance failure in which unselected cells are programmed or erased when programming the selected cells. The disturbance error occurs when the program coupling ratio of an unselected cell is greater than normal cells. One example is programming under an inhibitor bias condition.

FIG. 1 is a diagram illustrating a distribution of threshold voltages of an EEPROM in the case of including disturbance cells.

Referring to FIG. 1, when the erased cells are affected by the disturb, the threshold voltage of some cells becomes high in the A direction, resulting in a logic 0 during a read operation, thereby causing a read error. When the programmed cell is affected by the disturb, the threshold voltage of the cell becomes higher in the B direction. In the read operation, all cells of a string are always read out of logic 0 regardless of the threshold voltage.

2 is a flowchart sequentially illustrating a program verification method.

Referring to FIG. 2, a mode selection code for loading data to be programmed is input (S20), and address signals for selecting a program cell are input (S22). The data to be programmed to the selected cell is input into a register. At this time, logic 1 is input as data for the program protection cell and logic 0 is input as data for the cell to be programmed. After inputting the program mode selection code after inputting the data (S26), the program operation is performed (S28). After the program is executed for a predetermined time by the program control logic inside the chip, the threshold voltage of the selected cell sets a desired level. Must be verified to maintain (S30). When determining whether the cells have been programmed properly (S32), if the desired number of programs are programmed, all registers are stored in the fail / pass register as pass data of logic 1 (S34). If it is determined that the program of the cells is to be performed less, the corresponding register maintains the logic 0 at the time of input and repeats the program and verify operations for a predetermined number of programs (S32-1) (S32-2). At this time, the register which stores the data corresponding to the program protection cell maintains the state of original logic 1. The verification result of each cell is stored in the pass / fail register before the program is completed (S34). If the read selection code is input after the program is completed (S38), the program result (S40) can be known without the read operation on the program cells.

However, when the program protection cells in the selected memory cell array receive the disturb, the disturb cells cannot be detected. Therefore, the pass / fail cannot be accurately determined during program verification. This is a problem that occurs as the register corresponding to the program protection cell maintains the state of logic 1 until the program completion. Therefore, the read operation after the program is terminated and the overall system execution is reduced with the trouble of checking.

Accordingly, an object of the present invention is to provide a program verification method capable of detecting a disturb cell during a program operation.

1 shows a distribution of threshold voltages of a memory cell:

2 is an operation flowchart sequentially showing a program verification method according to the prior art:

3 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention:

4 is a flowchart illustrating a program verification method sequentially according to an embodiment of the present invention:

5 is an operation flowchart showing in detail a second program verification method:

6 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention:

* Explanation of symbols on the main parts of the drawings

100: memory cell array 110: X address buffer

120: Y address buffer 130: mode selection code register

140: data input buffer 150: control logic

160: Y address counter 170: core control circuit

180: first register 190: second register

200: first selection circuit 210: second selection circuit

220: comparison circuit 230: third register

(Configuration)

According to an aspect of the present invention, a memory cell array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in an area where the word lines and the bit lines intersect. Wow; A first register for storing data to be written to the cells and data to be read; A second register for storing data to be written to the cells; A first selection circuit for selecting the first register corresponding to the number of bit lines; A second selection circuit for selecting a second register corresponding to the first register number; A counter for sequentially enabling the first select circuit and the second select circuits from least significant bit to most significant bit; A comparison circuit for comparing the data of the first and second registers corresponding to the enabled first selection circuit and the second selection circuit after the program; And circuit for outputting the pass / fail of the selected cell after the program ends.

In a preferred embodiment, when the data stored in the first register and the second register after the program is different from each other, data for the program is not input.

According to still another aspect of the present invention, a memory cell array including a plurality of memory cells, a first register and a second register for storing data of a selected cell, and a result of verifying data of a programmed cell are stored. A program verification method for a semiconductor memory device including a third register, comprising: inputting an address; Inputting data to be programmed into the first and second registers, storing data of logic 0 corresponding to the program protection cell and storing program data of logic 1 corresponding to the selected cell; Performing a program operation; Verifying a program cell; Determining whether the selected cells are correctly programmed; When the selected cells are correctly programmed, performing a second program verification; After completion of the second program verify, storing the verified pass data in a third register; Outputting the pass data of the programmed cell, and comparing the maximum number of programs when the selected cells are not properly programmed; Performing a further program when less than the maximum number of programs; Storing fail data in the third register when greater than a maximum number of programs; And outputting whether or not the selected cell is to be failed.

In a preferred embodiment, the second program verifying step comprises: receiving an address signal of a least significant bit; Comparing data stored in the first and second registers; Determining whether the compared data is the same; When the data are the same, storing in a third register; Determining whether an address signal is most significant bit when the data compared are not the same; When the address signal is not the most significant bit, performing program verification; Terminating a program when the most significant bit and storing fail data in the third register; And notifying the occurrence of the failure of data to the outside.

(Example)

Hereinafter, a description will be given with reference to FIGS. 3 to 6 according to a preferred embodiment of the present invention.

3 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a nonvolatile semiconductor memory device includes a memory cell array 100, an X address buffer 110, a Y address buffer 120, a mode selection code register 130, a data input buffer 140, and read / write. Program / erase control logic 150, Y address counter 160, core control circuit 170, first register 180, second register 190, first Y select circuit 200, second Y select A circuit 210, a comparison circuit 220, a third register 230, an output data selection circuit 240, and a data output buffer 250.

4 is an operation flowchart sequentially showing a program verification method according to an exemplary embodiment of the present invention. In the program operation, a program data input selection mode is input (S120), and data S122 is input to a programmed cell. Data input to the cell is equally applied to the first register 180 and the second register 190. Then, the program mode selection code is input (S126) to perform a program operation (S128), and firstly verify whether the programmed cells are correctly programmed (S130). In this case, when the selected cell is sufficiently programmed, the first register 180 maintains the state of logic 1 (132), and undergoes secondary verification to detect the disturb cells among the programmed cells (100). In the read mode, after the program mode is terminated by storing the fail data in the third register 230 when the disturb cells are present through the second verification 100 and the pass data when the disturb cells are not present (S140). Determine pass / fail.

5 is a flowchart sequentially illustrating a secondary program verification method.

Referring to FIG. 5, when the result of the first verification (S130) is a pass (S132), the second verification senses selected cells during programming and stores the read data in the first register 180 (S138). . At this time, the data of the program protection cell is stored in the logic 1 state, and the data for the program cell or the disturb cells are stored in the logic 0 state. After the read data of the cells are stored as described above, the column address is set to the least significant bit (S100), and the data stored in the first register 180 corresponding to the data stored in the first register 180 and the data of the second register 190 are compared through the comparison circuit 220. Comparison is made (S102). If the data to be compared are equal to each other, the Y-address is counted up (S104-1, S104-2) to compare the data again. On the contrary, if the data to be compared are different from each other, the second program verification operation is terminated and the fail is stored in the third register 230 (S110). If the data up to the most significant bit (MSB) of the Y-address is the same, the path is stored in the third register 230.

The states of the first register and the second register after the first verification and the second verification as described above are shown in detail in the table.

[table]

Is there a disturb cell? Data entry Primary verification 2nd verification Data status NO First data register 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101 pass Second data register 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101 YES First data register 1010 ‥‥‥ 0101 1111 ‥‥ 1111 0010 ‥‥‥ 0100 fail Second data register 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101 1010 ‥‥‥ 0101

FIG. 6 shows that when a program operation is performed on one cell in a cell array of two EEPROMs in which bulk is separated, a second register corresponds to the other array block.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

Therefore, there is an effect that can detect even the disturbed cells during the program operation.

Claims (4)

A memory cell array having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in an area where the word lines and the bit lines cross each other; A first register for storing data to be written to the cells and data to be read; A second register for storing data to be written to the cells; First selecting means for selecting the first register corresponding to the number of bit lines; Second selecting means for selecting a second register corresponding to the first register number; A counter for sequentially enabling said first and second selection means from least significant bit to most significant bit; After program, comparing means for comparing data of the first and second registers corresponding to the first and second selection means enabled; And means for outputting a pass / fail of the selected cell after the program ends. The method of claim 1, And when data stored in the first register and the second register are different from each other after programming, data for the program is not input. A memory cell array including a plurality of memory cells, a first register for storing data of selected cells, a second register, and a third register for storing a result of verifying data of a programmed cell. In the program verification method, Inputting an address; Inputting data to be programmed into the first and second registers, storing data of logic 0 corresponding to the program protection cell and storing program data of logic 1 corresponding to the selected cell; Performing a program operation; Verifying a program cell; Determining whether the selected cells are correctly programmed; When the selected cells are correctly programmed, performing a second program verification; After completion of the second program verify, storing the verified pass data in a third register; Outputting path data of the programmed cell, Comparing the maximum number of programs when the selected cells are not properly programmed; Performing a further program when less than the maximum number of programs; Storing fail data in the third register when greater than a maximum number of programs; And outputting whether or not the selected cell is to be failed. The method of claim 3, wherein The second program verifying step includes receiving an address signal of a least significant bit; Comparing data stored in the first and second registers; Determining whether the compared data is the same; When the data are the same, storing in a third register; Determining whether an address signal is most significant bit when the data compared are not the same; Performing program verification when the address signal is not the most significant bit; Terminating a program when the most significant bit and storing fail data in the third register; And informing a failure occurrence of data to the outside.