KR19990053231A - Digital Single Chip Amplitude Modulation / Frequency Modulation Stereo Signal Generator - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital input /

2. Technical Challenges to be Solved by the Invention

The present invention relates to a method and apparatus for synthesizing quadrature-phase modulated carriers having no phase delay using a direct digital frequency synthesizer and synchronizing the signals using a single system clock, thereby improving the accuracy of the signal modulation and tuning. To provide an amplitude modulation / frequency-modulated stereo signal generator.

3. The point of the solution of the invention

The present invention includes an analog processing unit for calculating two independent external voice signals; An analog-to-digital converter for digitally sampling an analog signal and an external audio signal and outputting the digital signal as a digital signal; A digital processor for receiving an output signal of the analog-to-digital converter and outputting a digital frequency modulated stereo synthesized signal and a digital amplitude modulated stereo modulated signal according to an external selection bit and a single clock; And a digital-analog converter for outputting the digital signal as an analog signal.

4. Important Uses of the Invention

The present invention is used for digital AM / FM stereo modulation and synthesis signal generation.

Description

Digital Single Chip Amplitude Modulation / Frequency Modulation Stereo Signal Generator

The present invention relates to a digital single-chip amplitude modulation / demodulation method and a digital single-chip modulation / demodulation method, which improves accuracy, stability, and integration by processing a conventional analog-based amplitude modulation (AM) stereo modulator and a frequency modulation (FM) To a frequency-modulated stereo signal generator.

A conventional analog AM stereo modulator and an FM stereo synthesis signal generator will be described as follows.

Generally, an analog AM stereo modulator comprises a matrix circuit for adding and subtracting signals, two balanced modulators for amplitude modulating the output of the local oscillator and the local oscillator, a signal synthesizer for synthesizing the signals, a limiter, and an amplitude modulator.

The operation of the conventional AM stereophonic modulator having the above-described configuration will now be described.

The matrix circuit adds (L + R) and (LR) signals by adding / subtracting the left-side signal L and the right-side signal R inputted from the outside, (L + R) Modulates the oscillation frequency with the carrier wave, (L - R) Modulates the oscillation frequency by using an orthogonal frequency different from the 90-degree phase as a carrier wave.

Thereafter, the two modulated signals are synthesized and then converted into a carrier wave having a constant amplitude in the limiter, and the synthesized signal is converted into a carrier wave (L + R) Is subjected to large carrier suppression amplitude modulation.

(L + R) and (L-R) are orthogonal to each other and modulated.

This quadrature-phase modulated wave (v ₁ ) can be expressed by the following equation ( ₁ ).

_{v 1 = (1 + L +} R) cosω c t + (LR) cos (ω c t + π / 2)

= _{* Cos (ω c t + θ} )

here, to be.

However, in a mono broadcast, a square amplitude sweep (v ₂ ) can be expressed by the following equation ( ₂ ).

_{v 2 = (1 + L +} R) cosω c t

The right angle amplitude modulation (v ₂ ) is not the same as the amplitude value of the right angle amplitude modulation (v ₁ ). This means that distortion occurs when a stereo broadcast is received by a receiver. Therefore, compatibility is not maintained.

This right-angled amplitude modulation (v ₁ ) cosθ Multiplied by the amplitude of the quadrature amplitude modulation (v ₂ ) becomes equal to the amplitude of the quadrature amplitude modulation (v ₂ ). This can be expressed by the following equation (3).

v ₃ = v ₁ ? cos?

= (1 + L + R) cos (ω c t + θ)

Thus, v ₃ has the same amplitude as v ₂ and has a mono and stereo compatibility.

However, in the AM stereo modulator, a phase delay problem occurs between the reference carrier and the orthogonal carrier wave.

The process of synthesizing an orthogonal carrier having a phase difference of 90 degrees with respect to a reference carrier generates a phase delay between two frequencies. It also requires tuning of a sophisticated RC circuit to match the signals.

The FM stereo synthesis signal synthesizes a compatible signal so that both left and right signals can be transmitted simultaneously in a single wave for stereo broadcasting.

The FM stereo synthesis signal generator consists of a matrix circuit for adding and subtracting operations, a 19 kHz local oscillator, a doubler multiplier for 38 kHz, a carrier suppression amplitude modulator, and a signal synthesizer to add three signals.

The operation of the FM stereo synthesis signal generator having the above-described configuration will be described below.

(L + R) and (L-R) signals through a matrix circuit for adding and subtracting the left-side signal L and the right-side signal R inputted from the outside. Here, (L + R) is frequency-modulated by the frequency modulator as it is, and this signal is the same signal as the mono broadcast signal and is compatible when it receives the stereo broadcast by the mono receiver.

(L-R) signal modulates a 38 kHz subcarrier as carrier-suppressed amplitude modulation as an additional signal to the stereo.

On the receiving side, it is necessary to create subcarriers having the same frequency and phase as the subcarriers used in the transmitting side. A 19kHz pilot signal corresponding to 1/2 of the subcarriers is used to produce the subcarriers. The reason for using 19kHz instead of 38kHz as a pilot signal is that since there are no other signal components within ± 4kHz around the frequency, the receiving side easily extracts the pilot signal and multiplies it by 2 to achieve synchronization of 38kHz It is because.

The FM stereo synthesized signal can be expressed by the following equation (4).

Here,? _S is 2? X 38 kHz at each frequency of the subcarrier, sin (? _s / 2) t Is the pilot signal of 19 kHz, and p is the level value of the pilot signal. Therefore, the frequency spectrum for the FM stereo signal is (L + R) in the audible frequency range, and the (LR) signal is the frequency band in the range of 23 kHz to 53 kHz centered on the 38 kHz subcarrier suppressed by the carrier suppression amplitude modulation. .

At 19 kHz, there exists a pilot signal for synchronizing the transmission side and the reception side.

However, in the FM stereo synthesis signal generator, there arises a problem such as delay of signals and difficulty in synchronization.

38kHz is synthesized by doubling the local oscillator 19kHz, which causes a phase delay between the two frequencies. Here, the phase delay makes it difficult to synthesize the signal in the correct phase, and also causes the reception side to demodulate the distorted synthesized signal. In addition, for accurate signal synthesis, synchronization through inter-signal delay is required, and precise tuning of the RC circuit is required.

Conventionally, in the process of synthesizing orthogonal carriers having a 90-degree phase orthogonal to the oscillation frequency and synthesizing subcarriers by doubling the pilot signal, phase delay has occurred between the frequencies when using the conventional analog method. Therefore, it is necessary to precisely tune the circuit in order to avoid such a phase delay because the external input signal is amplitude-modulated with respect to the carrier whose signal is phase-modulated on the same time axis and the signal is not distorted on the receiving side This is because the signal separation can be maximized.

In the conventional analog signal generator as described above, the frequency phase between the reference carrier and the orthogonal carrier is delayed, the phase between the pilot signal and the subcarrier is delayed, the data is delayed with respect to the external input signal, There is a problem that the accuracy and the degree of integration are lowered.

In order to solve the above problems, the present invention is directed to a frequency synthesizer which synthesizes quadrature-phase modulated carriers having no phase delay using a direct digital frequency synthesizer and synchronizes the signals using a single system clock, Frequency modulation stereo signal generator capable of increasing the stability of a digital input / output chip amplitude modulated / frequency-modulated stereo signal.

1 is an overall block diagram of an embodiment of a digital single-chip stereo signal generator according to the present invention.

2 is a detailed block diagram of an embodiment of the digital processing unit of FIG. 1 according to the present invention.

3 is a detailed block diagram of an embodiment of the digital AM modulation unit of FIG. 1 according to the present invention.

FIG. 4 is a detailed block diagram of an embodiment of a digital frequency modulation (FM) stereo modulator of FIG. 1 according to the present invention; FIG.

5 is an output waveform diagram of a direct digital frequency synthesizer according to an embodiment of the present invention.

6 is an output waveform diagram of a digital frequency modulation (FM) stereo synthesis signal generator according to an embodiment of the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

10: analog processing units 20 to 23: analog-to-

30: digital processing unit 40: digital-analog conversion unit

According to an aspect of the present invention, there is provided an audio signal processing apparatus comprising: analog processing means for obtaining phase angles of at least two independent external audio signals and synthesizing the two audio signals; First analog-digital conversion means for digitally sampling an output signal of the analog processing means and the external audio signal to output a digital signal; Digital processing means for receiving an output signal of the first analog-to-digital conversion means and outputting a digital frequency modulation (FM) stereo synthesis signal and a digital amplitude modulation (AM) stereo modulation signal according to an external selection bit and a single clock; And a digital-analog conversion means for converting the digital output of the digital processing means into an analog signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall block diagram of an embodiment of a digital single-chip stereo signal generator according to the present invention.

The digital single chip stereo signal generating apparatus according to the preferred embodiment of the present invention includes an analog processing unit 10, a plurality of analog-digital processing units (ADC) 20 to 23, a digital processing unit 30, and a digital- (DAC) 40 as shown in FIG.

The analog processing unit 10 includes an arithmetic unit 101 as an Arch TANC calculator for obtaining a phase angle θ with respect to two independent external audio signals L and R, And an adder 102 for synthesizing (L + R) with respect to the input signal, and uses an analog component.

A plurality of analog-digital processing units (ADC) 20 to 23 digitally samples the output signal of the analog processing unit 10 and two independent signals L and R and outputs the digital signal.

The digital processing unit 30 includes a digital FM stereo synthesis signal generating unit 36 for receiving an output signal of the analog-digital processing units 20 to 23 and generating a digital FM stereo synthesis signal and a digital AM stereo modulation signal by a selection bit, And a digital AM stereo modulation unit 38. Further, it is composed of a reset switch 35, one common sine ROM 37, and a plurality of multiplexing units 31 to 34.

The reset switch 35 resets the digital circuitry and the selection bit for selecting AM or FM externally includes the function of selecting the digital AM stereo modulation section 38 or the digital FM stereo synthesis signal generation section 36, .

The sine ROM 37 commonly used by multiplexing in AM and FM receives the phase address output from the digital AM stereo modulation section 38 or the digital FM stereo synthesis signal generation section 36 by the selection bit, .

The digital-analog processing unit (DAC) 40 receives the digital output of the digital processing unit 30 and outputs an analog signal.

FIG. 2 is a detailed block diagram of the digital processor according to the present invention shown in FIG. 1. Referring to FIG.

A digital processor 30 according to a preferred embodiment of the present invention includes a data latch 201, a pilot signal adjuster 202, a signal combiner 203, an output signal adjuster 204, multipliers 205, 214 representing a carrier suppression amplitude modulator A frequency divider 206, a signal acceleration and frequency phase generator 207, a frequency multiplexer 208, a sine ROM 209, a multiplexer 210, a 4-stage shifter 211, a phase accumulator 212, An adder 213 representing a phase modulator, and an adder 215 representing a large carrier amplitude modulator.

The phase accumulator 212 is composed of a frequency register 212-1, a phase adder 212-2, and a phase register 212-3.

3 is a detailed block diagram of an embodiment of the digital AM modulation unit of FIG. 1 according to the present invention.

The digital AM stereo modulation section 38 includes a phase accumulator 212 for outputting a phase address of a carrier wave, an adder 213 for performing phase modulation for synthesizing a quadrature-phase modulated carrier wave, a digital FM stereo synthesis signal generating section 36, A four-stage shifter 211, a multiplier 214 for modulating a carrier wave suppression amplitude, and an adder 215 for performing a large carrier amplitude modulation.

The phase accumulator 212 outputs the phase address value of the frequency to synthesize the carrier used in the large carrier amplitude modulation or the carrier suppression amplitude modulation.

The phase accumulator 212 comprises a 32-bit frequency adjustment register 212-1, a 32-bit phase adder 212-2, and a 32-bit phase register 212-3 storing the outputs of the phase adder 212-2. do.

The frequency adjustment register 212-1 receives and stores a frequency adjustment word for adjusting the output value of the frequency.

The phase adder 212-2 adds the output value of the frequency adjustment register 212-1 and the output of the phase register 212-3 as inputs.

The phase register 212-3 stores the output of the phase adder 212-2 which performs a linear increase and the upper 16 bits of the output of the 32-bit phase register 212-3 are stored in the adder 213 as a phase modulator And outputs it as an input.

A phase modulator 213 composed of an adder performs phase modulation to synthesize an orthogonal phase modulated carrier wave and adds a nonlinear phase value to an output value of a linearly increasing phase accumulator 212 to obtain a phase modulated And outputs the phase address. That is, the 16 high-order bits outputted from the phase accumulator 212 and the 16-bit phase shifted piece arctangent tangent input from the outside are added to the phase-modulated carrier wave cos (ω _c t + θ) And outputs the phase address.

However, in the case of the mono mode, since the left signal L and the right signal R are the same, the phase difference of the signal does not occur. Therefore, the value of the phase shifted Arch TAN &thetas; becomes 0, cos ω _c t The phase address of the ROM table corresponding to the "

The sine ROM 209 used together with the digital FM stereo synthesis signal generator 36 outputs the phase-modulated carrier wave to the multiplier 214 and the 4-stage shifter 211.

The high-speed four-stage pipeline multiplier 214 modulates the carrier suppression amplitude, and is composed of a four-stage pipeline adder to perform a multiplier function.

The first pipeline performs an exclusive OR operation on the two input signals using the Exclusive-OR gate (Ex-OR), and the remaining lower bits are used to select one input for one input as the selection bit of the multiplexer use. That is, in the first pipeline, all the bits to be added are output in advance through the multiplexer, and in the remaining pipelines, the addition operation is performed by adjusting the number of digits of the calculation result of the previous pipeline.

Therefore, the 4-stage pipeline multiplier 214 multiplies the (L + R) signal input from the outside and the quadrature-phase modulated carrier outputted from the carrier divider (L + R) cos (ω c t + θ) .

Since the output of the 4-stage pipeline 211 is input to the 4-stage pipeline high-speed multiplier 214 after 4 clocks, cos (ω _c t + θ) And outputs the latched data. Here, the data synchronization through the signal delay has an accurate signal synthesis function.

An amplitude modulator 215 configured with an adder amplitude modulates the large carrier, and outputs a large carrier amplitude modulation, a carrier suppression amplitude modulation, and a mono signal.

Stage pipeline high-speed multiplier 214 and the output of the 4-stage shifter 211 are input to perform the addition operation when the large carrier wave amplitude modulation is outputted by the large carrier / carrier suppression mode selection bits, The amplitude modulation (C-QUAM) signal (1 + L + R) cos (ω c t + θ) ).

Stage pipeline multiplier 214 as the output of the amplitude modulator 215 when outputting the carrier suppressing amplitude modulation.

FIG. 4 is a detailed block diagram of an embodiment of a digital frequency modulation (FM) stereo modulator of FIG. 1 according to the present invention.

The digital FM stereo synthesized signal generating section 36 includes a signal add / drop frequency phase generator 207, a phase accumulator 212, a frequency multiplexer 208, a frequency divider 206 and a subcarrier suppression amplitude modulator 205 A pilot signal regulator 202, a data latch 201, a signal synthesizer 203, an output signal regulator 204, and a sign ROM 209.

The data flow between each block is controlled by a combined signal of the divided clock frequency and the divided clock frequency.

The signal enhancement and frequency phase generator 207 is constituted by an input data converter and a frequency phase generator as blocks serving as a matrix circuit and a local oscillator in an analog circuit.

The input data converter corrects the data input to the analog-to-digital converter according to the digital circuit, and functions to binarize the data to facilitate signal calculation.

The input data converter consists of a data size adjustment unit and a binary maintenance output unit.

The data size adjustment unit inverts the most significant bit (i.e., sign bit) input from the analog-digital conversion units 20 to 23. Since the analog-to-digital conversion units 20 to 23 have a characteristic of outputting 0 when the analog-to-digital conversion unit 20 is negative and outputting 1 when the analog-digital conversion unit 20 to 23 is a positive number, the data size is adjusted to a positive number 0, To initialize the positive zero data value to zero.

The binary complement output unit binarizes the data output from the data size adjustment unit so that data having a negative sign can be easily calculated in the next block.

The frequency phase generator functions as a matrix circuit and a frequency oscillator in an analog circuit.

The frequency generation and signal addition and subtraction calculator 207 is composed of a pilot signal and a subcarrier generation unit using the adder / subtractor of the left signal L and the right signal R and the direct digital frequency synthesizer.

The left signal and the right signal addition / subtraction operation unit adds the binary left-hand signal and the right signal output from the input data converter to output a sum signal (L + R) and a difference signal (LR) 2 < / RTI > In addition, the pilot signal and the subcarrier generator output the phase address corresponding to the pilot signal of 19 kHz and the subcarrier of 38 kHz by continuously accumulating the fixed 32-bit binary frequency adjustment word in the phase adder.

The frequency multiplexer and frequency divider 207 and 209 multiplex the phase values of the frequency and distribute the data output from the sine ROM 209 to the corresponding block.

The frequency multiplexer and frequency divider 207 and 209 include a phase accumulator 212 for outputting the phase address in the case of the internal mode, a frequency multiplexer 208 for multiplexing the 19 kHz, 38 kHz, and internal mode phase values, And a frequency divider 206 for distributing sine values output from the sine ROM 209 and the sine ROM 209.

The phase accumulator 212 receives the 32-bit binary frequency adjustment word from the outside in the internal mode, accumulates the phase value, and outputs the phase address.

The frequency multiplexer 208 receives the phase addresses of 19 kHz and 38 kHz and the output value of the phase accumulator 212 oscillating in the case of the internal mode.

The frequency multiplexer 208 multiplexes the 32 frequency clock and the 16 frequency clock with the selection bit to output a 19 kHz phase address in the case of "0", an internal mode phase (INT) address in the case of "1" And outputs a 38 kHz phase address.

The address outputted from the frequency multiplexer 208 becomes the phase address of the sine ROM 209 on which the sine lookup table is mounted and the digital sine waveform is output from the sine ROM 209 and input to the frequency divider 206 do.

The frequency divider 206 receives the input of the clock divider in response to the frequency divider 208, latches the data, and distributes the values to the desired block.

The subcarrier suppressing amplitude modulator 205 composed of multipliers modulates the (L-R) signal by carrier suppression amplitude modulation on the subcarriers, and performs the multiplication operation through repetition of consecutive shift operation and addition operation.

The multiplier 205 includes a 30-bit shift register for receiving and shifting the LR signal, a 15-bit shift register for receiving a phase value of 38 kHz, a 30-bit adder for calculating two shifted values, a 30- And a sign bit and a data latch for storing the upper 15 bits of the output value of the accumulator and outputting together with the sign bit.

The L-R signal is input to the 30-bit shift register, and the 38 kHz phase value is input to the 15-bit shift register.

The output value of the 15-bit shift register is selected as a multiplexer select bit. When the value is 1, the shifted 30 bits are outputted. When the value is 0, 30 bits are outputted as a 0 value.

The 30-bit accumulator latches the value output from the adder to maintain the accumulated value, and the upper 15 bits of the value are input to the sign bit and the data latch.

The sign bit and data latches latch the upper 15 bits output from the sign bit and the 30 bit accumulator and output (L-R) * 38 kHz by the 16 period data output signal. Also, the (L-R) signal and the 38 kHz signal are input to the shift register by the 16-period data input signal, and are multiplied again by successive shift and addition operations.

The pilot signal adjuster 202 adjusts the amplitude of the 19 kHz pilot signal and performs a multiplication operation through a series of iterations of shift and addition.

"FCC" specifies that 10% of the maximum frequency deviation in a stereo broadcast shall be assigned to a 19 kHz pilot signal and the remaining 90% shall be assigned to (L + R) and (L-R).

The pilot signal adjuster 202 includes a 23-bit shift register for receiving and shifting a phase value, an 8-bit shift register for receiving and shifting 8-bit pilot control bits, a 23-bit adder for calculating two shifted values, And a sign bit and a data latch for latching the upper 15 bits of the output value of the accumulator and outputting it together with the sign bit.

The 19 kHz phase value signal is input to the 23-bit shift register, and the 8-bit pilot signal control bit value is input to the 8-bit shift register.

The output value of the 8-bit shift register is selected as a multiplexer select bit, and when it is 1, the shifted 23 bits are outputted. When it is 0, the 23 bit adder performs a sum operation by outputting 23 bits.

The 23-bit accumulator latches the value output from the adder to maintain the accumulated value, and inputs the upper 15 bits of the value to the sign bit and data latch.

The sign bit and data latches latch the sign bit and the upper 15 bits output from the 23-bit accumulator, and output a 19 kHz level adjusted by the 8 period data output signal. Also, the 8-bit pilot signal control bit value and the phase value of 19 kHz are inputted to the shift register by the 8-period data input signal, and the multiplication operation is repeated.

The data latch 201 maintains the (L + R) signal to synchronize the output and synchronization of the subcarrier suppression amplitude modulator 205 and the pilot signal adjuster 202. It synchronizes through the signal delay so that it can output the correct composite signal. Also,

The signal synthesizer 203 generates three signals (i.e., (L + R) , (L - R) sin? _S t , And p sin (? _s / 2) t ).

The signal synthesizer 203 is composed of two addition operation units.

(L-R) * 38 kHz and the level-adjusted 19 kHz value, and the operation result value is added again with (L + R). Here, if the calculated result value is a negative number, it is binary-coded and output.

The output signal adjuster 204 converts the data to fit the level adjustment for the final output signal and the input signal of the digital-to-analog converter 40.

The output level adjustment and data converter (not shown in the figure) consists of an internal / external mode and a stereo / mono selector and a level adjuster.

The input of the external mode is the input of the analog-to-digital converter, so there is no sign bit inversion, but the internal mode and stereo input inverts the sign bit for the digital-analog input.

The output value multiplexed by the outer / inner and stereo / mono selection bits is level-adjusted by the level adjuster, and inverts the sign bit to match the input of the digital-to-analog converter to output the final digital FM stereo synthesized signal.

5 is an output waveform diagram of a direct digital frequency synthesizer according to an embodiment of the present invention.

Direct Digital Frequency Synthesizer (DDFS) is a device that receives a digital frequency adjustment word and synthesizes the frequency of an analog waveform, providing a short transition time and continuous phase shift, high precision, and stability.

The direct digital frequency synthesizer is composed of a phase accumulator for accumulating the phase change, a sine function calculator for calculating a sine value according to the phase change, and a digital-to-analog converter for converting the generated digital sine wave into an analog signal.

The output waveform of the direct digital frequency synthesizer having the above-described configuration is as shown in FIG.

The digital single-chip amplitude modulation / frequency-modulated stereo signal generating apparatus according to the preferred embodiment of the present invention is functionally compatible with a conventional analog stereo signal generating apparatus, thereby providing a digital signal having advantages of low noise, high integration, And it can be used as a precise data measuring equipment by being used as a digital AM / FM synthesis signal generating instrument in addition to analog to digital conversion of various measuring instruments.

For example, the output waveform of a digital frequency modulation (FM) stereo synthesis signal generator is shown in FIG.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. The present invention is not limited to the drawings.

The present invention as described above can improve the integration degree of the circuit and the stability of the tuning by improving the signal-to-noise ratio by synchronizing the signals by the single system clock by eliminating the frequency phase delay and the data delay, The signal can be modulated without distortion and the signal separation on the receiving side can be greatly improved.

Claims (10)

Analog processing means for obtaining a phase angle with respect to at least two independent external audio signals and synthesizing the two audio signals; First analog-digital conversion means for digitally sampling an output signal of the analog processing means and the external audio signal to output a digital signal; Digital processing means for receiving an output signal of the first analog-to-digital conversion means and outputting a digital frequency modulation (FM) stereo synthesis signal and a digital amplitude modulation (AM) stereo modulation signal according to an external selection bit and a single clock; And A digital-to-analog conversion means for converting the digital output of the digital processing means into an analog signal, / RTI > modulated / frequency modulated stereo signal generator. The method according to claim 1, Wherein the analog processing means comprises: Calculating means for obtaining a phase slice for the external audio signal and outputting the phase slice to the first analog-digital converting means; And An adding means for adding the external audio signal and outputting the result to the first analog-digital converting means; / RTI > modulated / frequency modulated stereo signal generator. 3. The method of claim 2, Wherein the first analog-to- Second analog-digital conversion means for receiving one of the external audio signals and converting the digital audio signal into a digital signal and outputting the digital signal to the digital processing means; Third analog-digital conversion means for converting an output value of the calculation means into a digital signal and outputting the digital signal to the digital processing means; Fourth analog-digital conversion means for receiving the other one of the external audio signals and converting the same into a digital signal and outputting the digital signal to the digital processing means; And A fifth analog-to-digital conversion means for converting an output value of the addition means into a digital signal and outputting the digital signal to the digital processing means / RTI > modulated / frequency modulated stereo signal generator. The method according to claim 1 or 3, Wherein the digital processing means comprises: First multiplexing means for selecting one of the digital signals input from the second and third analog-digital conversion means according to the external selection signal and outputting the selected digital signal; Second multiplexing means for selecting one of the digital signals input from the fourth and fifth analog-digital conversion means according to the external selection signal and outputting the selected digital signal; Reset switching means for selectively interrupting a reset signal input from the outside according to an external selection signal; A reset signal of the reset switching means and a clock, a frequency adjustment word, a pilot signal, a final output control bit, an internal / external mode selection signal, a stereo / mono signal And digital frequency modulated (FM) synthesized signal generation means for generating a digital frequency modulated (FM) stereo synthesized signal in accordance with the test mode signal; A test mode selection signal, and a large-band signal / carrier suppression mode selection signal, which are received from the output signal of the first and second multiplexing means, from a reset signal of the reset switching means and a clock, a frequency adjustment word, a stereo / mono signal, A digital amplitude modulation (AM) stereo modulation means for receiving a digital amplitude modulation (AM) stereo signal and generating a digital amplitude modulation (AM) stereo modulation signal; Third multiplexing means for selecting one of the digital frequency modulation (FM) synthesized signal generation means and the output phase address of the digital amplitude modulation (AM) stereo modulation means according to an external selection signal and outputting the selected signal; Storage means for receiving a corresponding phase address selected by the third multiplexing means and outputting the frequency to the digital frequency modulation (FM) stereo synthesis signal generation means and the digital amplitude modulation (AM) stereo modulation means; And A fourth multiplexing means for selectively outputting one of output signals of the digital frequency modulation (FM) stereo synthesis signal generation means and the digital amplitude modulation (AM) stereo modulation means in accordance with an external selection signal / RTI > modulated / frequency modulated stereo signal generator. 5. The method of claim 4, The digital amplitude modulation (AM) stereo modulation means comprises: A phase accumulation means for receiving a frequency adjustment word from the outside and counting and outputting the frequency adjustment word according to a system clock; Phase modulating means for receiving a linear output value of the phase accumulating means and a nonlinear phase shifter input from the outside and outputting the phase address of the phase-modulated carrier wave; Carrier suppression amplitude modulation means for receiving the output of the storage means and modulating carrier wave amplitude modulation; Shifting means for receiving an output value of the carrier suppressing amplitude modulating means and latching and outputting the output value for synchronizing data; And A carrier amplitude modulating signal of the carrier suppressing amplitude modulating means and a latched synchronizing signal of the shifting means to output a digital amplitude modulated stereo signal; / RTI > modulated / frequency modulated stereo signal generator. 6. The method of claim 5, Wherein the phase accumulating means comprises: A frequency storage means for receiving an external frequency adjustment word for synthesizing a carrier wave used in a large carrier amplitude modulation or a carrier suppression amplitude modulation; Phase addition means for adding the data word of the frequency storage means and the output value of the phase storage means and outputting the resultant data in accordance with the clock frequency; And The phase storage means storing an output of the phase addition means / RTI > modulated / frequency modulated stereo signal generator. The method according to claim 6, Wherein the phase modulating means comprises: And a first adder for adding a linear output value of said phase accumulating means and a non-linear phase shifter inputted from the outside. 8. The method of claim 7, Wherein the carrier suppressing amplitude modulating means comprises: And a multiplier configured by a four stage pipeline adder to perform carrier suppression amplitude modulation. ≪ RTI ID = 0.0 > [0002] < / RTI > 9. The method of claim 8, Wherein the large carrier amplitude modulation means comprises: Stage pipeline adder and a second adder for adding the outputs of the shifting means. 5. The method of claim 4, Wherein the digital frequency modulation (FM) A signal enhancement and frequency phase generation means for correcting data selected by the first multiplexing means to perform binary compensation and inverting an input most significant bit; A frequency multiplexing means for selectively outputting any one of the output signals of the signal enhancement and frequency phase generating means according to an output signal of the digital amplitude modulation stereo modulation means; Frequency distributing means for distributing respective sine values output from the sine lookup table; Subcarrier suppressing amplitude modulating means for subcarrier suppressing amplitude modulation of the error of the external audio signal to a subcarrier; Pilot signal adjusting means for adjusting the amplitude of the pilot signal; Data latch means for holding a signal obtained by adding the external voice signal to synchronize with the outputs of the sub-carrier suppression amplitude modulating means and the pilot signal adjusting means; Signal combining means for combining the output signals of said data latch means, said sub-carrier suppression amplitude modulating means, and said pilot signal adjusting means; And An output signal adjusting means for adjusting the level of the final output signal and converting the data to match the input of the digital- / RTI > modulated / frequency modulated stereo signal generator.