KR19990052892A - How to implement standby test function of electronic exchange - Google Patents

Abstract

The present invention relates to a method for implementing a standby side processor test function of an electronic switch, wherein a standby side processor test request is made by an operator and the active side / standby side redundancy state is checked at an initial stage of the standby side test, and a standby side test is performed. When the state is completed, the memory stored on the active side is copied to the standby side memory when the memory is empty by the transfer of the test result and the standby processor restarted to the active side, and when the test progress state is completed and returns to the normal state, the test Since the result is output to the operator, the problem of the standby processor may be recognized in advance so that a stable response may be made in the event of a failure of the active processor.

Description

How to Implement Standby-side Processor Test Capabilities in Electronic Switching Systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Full Electronic Telephone eXchange, and more particularly, in a TDX-100 switch, in which a standby side of the Standby side processor board (Board) can be identified in advance. The present invention relates to a processor test function implementation method.

In general, electronic switchboards require that all upper and lower processors and the physical layer have basically been set-up completed, the operating system started up, and operated for a long time without any special faults. In case of a distributed system that needs to be operated for a long time due to the repair of the lower processor, whenever the various faults and failures occur, check the board abnormality and replace the board with various functions of the processor board. Quick and accurate checks ensure reliable response in the event of an active processor failure.

In the test process of the standby side processor board of the upper and lower processors mounted in the conventional electronic switchboard, the system does not undergo the interworking test, and is actually mounted in the electronic switchboard so that the system can be linked.

Therefore, after being substantially mounted in the electronic switchboard, there is a problem in that it is not possible to stably deal with a failure of the active processor without affecting the active processor by recognizing an abnormality occurring in the standby processor in advance.

The present invention has been made to solve such a problem, and its purpose is to test the failure response in the standby processor inside the switch in advance, so that the active processor is not affected, and the standby is immediately performed without time delay or disconnection. The present invention provides a method for implementing a standby side processor test function of an electronic switch that can be performed on the side processor.

The present invention for achieving this object relates to a method for implementing a standby side processor test function of an electronic switch, comprising the steps of: receiving a standby side processor test request using a man & machine communication port by an operator request; Checking an active / standby side redundancy state as an initial step of a standby test; Checking the active side / standby side redundancy state, and then performing a standby side test; If the standby side test progress is not completed, performing the standby side test progress again; When the standby test is completed, transmitting the test result information to the active side; Restarting the standby side processor after the test result information is transmitted; Resuming the memory of the standby processor according to the restart; Copying the memory stored on the active side to the standby side memory; And when the standby processor test progress state is completed and returns to the normal state, outputting the test result to the operator.

1 is an overall block diagram of a method for implementing a standby side processor test function of an electronic switch according to the present invention;

2 is a detailed detailed flowchart of the present invention for a method of implementing a standby side processor test function of an electronic switching system.

<Description of the symbols for the main parts of the drawings>

10: CCP unit 20: IPC unit

30-0 to 30-n: MP0 to MPn 40-0 to 40-n: TP0 to TPn

Hereinafter, the objects and features of the present invention will be described in more detail with reference to the accompanying drawings so that the objects and features of the present invention can be more clearly understood.

1 is an overall block diagram of a method for implementing a standby side processor test function of an electronic switching system according to the present invention, and includes a central control processor (hereinafter, referred to as CCP) unit 10 and an internal processor communication ( Inter Processor Communication (hereinafter, abbreviated as IPC) unit 20, Main Processor (hereinafter, abbreviated as MP) 0 to MPn (30-0 to 30-n), and Telephony Processor: TPn (hereinafter abbreviated as TP) 0 to TPn (40-0 to 40-n).

The CCP unit 10 is a central control processor, and is a processor board existing in the central control subsystem. The CCP unit 10 is divided into an active side and a standby side, and the active side is internally digital. Digital signal processor assembly board (hereinafter abbreviated as DSPA) 212, DSPA 211, and RS232C port is an active processor that performs / processes the functions entrusted to itself in the actual exchange, The Standby side is internally equipped with DSPA 212, DSPA 211, and RS232C ports, and is a side waiting for itself without performing any functions originally entrusted to the actual processor. If it is judged that the function of the abnormal processor cannot be performed and a transfer request is received, it immediately becomes an active side. Be a standby processors that have awaited so poised to perform.

In addition, the CCP unit 10 is a processor having a maintenance function. The CCP unit 10 operates for hardware test and operating system initialization, loading according to the processor operation mode, and software initialization for normal operation, and active / standby side duplication. A processor structured as a structure, a hard disk unit (DisK Unit), a removable disk (Removable DisK Unit), a cartridge tape (Cartridge Tape Unit), a magnetic tape unit (Magnetic Tape Unit), and a small computer system interface ( Small Computer System Interface (hereinafter, abbreviated as SCSI) A processor that performs maintenance using the bus and tests IPC, timer, memory, SCSI, and MMC functions.

In addition, an unshown man & machine communication port interfaced with the CCP unit 10 provides an RS232C interface port for controlling an input / output link operated by an unshown input output processor. to be.

Here, the input output processor (hereinafter, referred to as IOP) is an input / output processor that is in charge of the input / output link control, and performs message data handling for analyzing and managing messages input and output through the input / output link. Data Handling, Input Output Process Management, which performs status management and I / O control functions for each I / O link, Disk Handling, which performs file management functions for hard disks in a PC, It consists of Data Generation that performs the function of generating the station data of the system and matching with the system software, and Data Extraction, which extracts the station data from the system package in operation. The MCP port is used to interface with the CCP unit 10.

The IPC unit 20 is an indispensable communication means in the electronic switch processor. The IPC unit 20 tests local, loop-back, and external IPCs, and includes a plurality of MP0 to MPn units (30-0 to 30-n) and a plurality of TP0s. Allow processor communication between the TPn sections 40-0 to 40-n.

The MP0 to MPn units (30-0 to 30-n) are composed of active / standby side redundancy using the concurrent writing method. If a serious failure occurs on the active side, the standby side immediately loses the service. Since it executes immediately after the active side without any execution, the service is guaranteed without loss of online service, and many main processors can be operated in conjunction with DSPA211 and DSPA212 (maintenance processor) by default. The memory, timer and test functions are common, and the SCSI and MMC (DSPA212) functions are higher processors that are tested separately according to the characteristics of the processor.

The TP0 to TPn sections 40-0 to 40-n are composed of the MP0 to MPn sections 30-0 to 30-n and an active / standby side redundant structure via the IPC section 20 to perform internal communication. It is a lower processor that can test IPC, memory, timer and HIT functions through HIT bus.

Here, the HIT bus is a high data link control type communication path having a speed of up to 2Mbps, and is a bus that interfaces with a bandwidth of 2Mbps between the lower processor and the device.

The overall block diagram of the method for implementing the standby side processor test function of the all-electronic exchange according to the present invention configured as described above has been described. FIG. 2 is a detailed view of the present invention for the method for implementing the standby side processor test function of the all-electronic exchange. The detailed flowchart is demonstrated.

In order to test the standby processor functions of the TP0 to TPn sections (40-0 to 40-n) and the MP0 to MPn sections (30-0 to 30-n), which are all-electronic exchange processors, If a standby test request is received (step 200), the active / standby redundancy state is checked as an initial step of the standby test (step 201).

Here, in the standby test, all processors inside the electronic switchboard are all mounted in a redundant structure, so it may be necessary to change the active side or change due to hardware failure. At this time, the operator checks the board status for stable system operation.

After the active side / standby side redundancy is confirmed, the standby side test is performed (step 202), it is determined whether the test is completed (step 203), and if the process is not completed, the standby side test progress is performed again.

When the standby test is completed, the test result information is transmitted to the active side (step 204).

Here, the active side is a side for performing / processing a function entrusted to itself in an actual exchange, and the standby side is a side waiting for itself without performing any function entrusted to the actual processor. Side that is fully prepared to change all functions from standby side to active side immediately when a transfer request is made because it is determined that a serious failure has occurred and the side can no longer function as a processor. to be.

After restarting the standby processor (step 205), when the memory of the standby processor becomes empty (step 206), the memory stored on the active side is copied to the standby memory (step 207).

When the standby processor test progress state is completed and returns to the normal state (step 208), the test result is output to the operator (step 209).

In conclusion, the standby side processor test by the operator's request in the processor status reported to the operator is in progress, and after the test is completed, the standby state is returned to the standby state before starting the normal process. Problems of the side processor can be recognized in advance, and stable actions can be taken in case of failure of the active side processor.

As described above, the present invention described above is a process in which the standby side processor test by the operator's request is in progress during the operation of the electronic switching system, and after the test is completed, the process of returning to the standby state before starting the normal state process is completed. In addition, it is possible to recognize the problem of the standby processor in advance and to stably deal with a failure of the active processor.

Claims (1)

In the standby side processor test function implementation method comprising an operator of an electronic switchboard, an active side / standby side, and a man & machine communication port, Receiving, by the operator request, the standby side processor test request by using the man & machine communication port; Checking the active side / standby side redundancy state as an initial step of the standby side test; Checking the active side / standby side redundancy state and then performing the standby side test; If the standby side test progress is not completed, performing a standby side test progress again; Transmitting the test result information to the active side when the standby test is completed; Restarting the standby processor after the test result information is transmitted; Leaving the memory of the standby side processor empty according to the restart; Copying the memory stored in the active side to the standby side memory; And when the standby side processor test progress state is completed and returns to a normal state, outputting a test result to an operator.