KR19990048773A - Flash Ipyrom Cell Array - Google Patents

Abstract

The present invention relates to a flash EEPROM cell array having a bit line divide structure, wherein a memory cell block is divided into first and second memory cell blocks by a local bit line selection circuit. The line is divided into local bit lines, and two local bit lines of the first memory cell block and two local bit lines of the second memory cell block into one global bit line. The present invention relates to a flash EPIROM array in which at least one of four local bit lines can be selected by a switching operation of select transistors provided in a local bit line select circuit.

Description

Flash Ipyrom Cell Array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPROM cell array, in particular dividing a bit line into local bit lines, and four local bit lines into one global bit line. The present invention relates to a flash Y pyrom cell array shorted to a bit line so that any one of four local bit lines can be selected by a switching means.

In general, in a flash Y pyrom cell array, a plurality of memory cells form a matrix. In many memory cells, word lines are connected to an X-decoder and bit lines are connected to a Y-decoder. The program, erase or read operation of the flash Y pyrom is performed in a memory cell selected by electrical signals of word lines and bit lines, respectively.

Since the conventional flash Y pyrom cell array is configured such that a bit line is connected to the drain of each memory cell, when a voltage is applied to the bit line to select a memory cell, capacitance is generated in the bit line portion to which the voltage is applied. . Since one bit line occupies a large area in the cell array, a large amount of capacitance is generated, and the capacitance causes a slow operation speed. Therefore, in order to reduce the capacitance generated in the bit line portion and to increase the operation speed of the device, a bit line division structure is applied.

1 is a circuit diagram illustrating a flash Y pyrom cell array having a bit line division structure.

A memory cell block 100 having a plurality of memory cells organized in a matrix is divided into first and second memory cell blocks 10 and 20 and localized between the first and second memory cell blocks 10 and 20. A local bit line select circuit 30 is provided. For convenience of description, the memory cell block 100 illustrates only a portion in which one source line SL1 shares two memory cells.

The first memory cell block 10 includes first to n / 2 word lines WL1 to WLn / 2 (hereinafter, “n” is defined as a positive even number) and first to fourth local bit lines LB1 to LB4). The second memory cell block 20 is composed of n / 2 + 1 to n word lines WLn / 2 + 1 to WLn and fifth to eighth local bit lines LB5 to LB8. The local bit line select circuit 30 is composed of first and second select lines QL1 and QL2. The first select line QL1 includes first to fourth select transistors Q1 to Q4, and the second select line QL2 includes fifth to eight select transistors Q5 to Q8. The first to fourth global bit lines GB1 to GB4 are connected to the local bit line selection circuit 30.

The first local bit line LB1 is connected to the source of the first select transistor Q1, the fifth local bit line LB5 is connected to the source of the fifth select transistor Q5, and the first global bit line LB1 is connected to the source of the fifth select transistor Q5. GB1 is connected to the drains of the first and fifth select transistors Q1 and Q5. Therefore, the first global bit line GB1 is electrically connected to the first and fifth local bit lines LB1 and LB5 by the switching action of the first and fifth select transistors Q1 and Q5.

In the above connection method, the second global bit line GB2 is electrically connected to the second and sixth local bit lines LB2 and LB6 by a switching action of the second and sixth selection transistors Q2 and Q6, and the third The global bit line GB3 is electrically connected to the third and seventh local bit lines LB3 and LB7 by the switching action of the third and seventh selection transistors Q3 and Q7, and the fourth global bit line GB4 is It is electrically connected to the fourth and eighth local bit lines LB4 and LB8 by the switching action of the fourth and eighth select transistors Q4 and Q8.

The first to n word lines WL1 to WLn and the first and second select lines QL1 and QL2 are respectively connected to the X-decoder 40. Each of the first to fourth global bit lines GB1 to GB4 is connected to the Y-decoder 50.

The operation method of the flash Y pyrom having the bit line division structure configured as described above is as follows.

Applies a voltage to at least one of the first to n word lines WL1 to WLn, applies a voltage to at least one of the first and second select lines QL1 and QL2, and applies the first to fourth global bits. At least one of the plurality of memory cells of the memory cell block 100 is selected by applying a voltage to at least one of the lines GB1 to GB4 to perform a program, erase, or read operation.

For example, a state in which a voltage is applied to the first word line WL1 and a voltage is applied to the first select line QL1 to turn on the first to fourth selection transistors Q1 to Q4. When the voltage is applied to the first global bit line GB1, the first global bit line GB1 is electrically connected to the first local bit line LB1 through the first selection transistor Q1 to be electrically connected to the first global bit line GB1. The memory cell M1 performs a program, erase, or read operation.

In this way, two local bit lines are shorted to one global bit line so that a desired local bit line can be selected. By dividing the bit lines, the capacitance can be reduced, thereby increasing the operation speed of the device. However, since the area occupied by the local bit line select circuit in the cell array portion and the area where the first and second select lines are connected in the area of the X-decoder are increased, it is difficult to realize high integration of the device. In addition, since one global bit line must be contacted between two local bit lines, it is difficult to secure a contact process margin, which makes it difficult to apply a bit line division structure to a high technology cell.

Accordingly, an object of the present invention is to provide a flash Y pyrom cell array capable of realizing high integration of the device by reducing the area occupied by the Y-decoder while reducing the capacitance generated by the bit line to increase the operation speed of the device.

In order to achieve this object, a flash Y-pyrom cell array of the present invention may include: first and second memory cell blocks including a plurality of word lines and a plurality of local bit lines; A local bit line select circuit comprising first to fourth select lines between the first memory cell block and the second memory cell block; A plurality of global bits configured to share two local bit lines of the first memory cell block and two local bit lines of the second memory cell block among the plurality of local bit lines through the local bit line selection circuit Lines; An X-decoder connected to the plurality of word lines and the first to fourth select lines; And a Y-decoder connected to the plurality of global bit lines.

1 is a circuit diagram for explaining a conventional flash ypyrom cell array.

2 is a circuit diagram illustrating a flash Y pyrom cell array according to an embodiment of the present invention.

3 is a layout of a flash Y pyrom cell array showing main parts of the circuit diagram shown in FIG.

<Explanation of symbols for main parts of the drawings>

100 and 200: memory cell blocks 10 and 110: first memory cell blocks

20 and 120: second memory cell blocks 30 and 130: local bit line selection circuit

40 and 140: X-decoder 50 and 150: Y-decoder

160: device isolation region

SL: source line WL: word line

LB: local bit line GB: global bit line

QL: select line Q: select transistor

M: memory cell DD: conducting portion

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating a flash Y pyrom cell array having a bit line division structure according to an exemplary embodiment of the present invention, and FIG. 3 is a layout of a flash Y pyrom cell array showing main parts of the circuit diagram shown in FIG. 2. . The same reference numerals in FIGS. 2 and 3 mean the same elements.

A memory cell block 200 having a plurality of memory cells organized in a matrix is divided into first and second memory cell blocks 110 and 120, and a local bit line selection circuit between the first and second memory cell blocks 110 and 120. 130 is provided. For convenience of description, the memory cell block 200 illustrates only a portion in which one source line SL1 shares two memory cells.

The first memory cell block 110 may include first to n / 2 word lines WL1 to WLn / 2 (hereinafter, “n” is defined as a positive even number) and first to fourth local bit lines LB1 to LB4). The second memory cell block 120 is composed of n / 2 + 1 to n word lines WLn / 2 + 1 to WLn and fifth to eighth local bit lines LB5 to LB8. The local bit line select circuit 130 is composed of first to fourth select lines QL1 to QL4. The first select line QL1 includes first and third select transistors Q1 and Q3, the second select line QL2 includes second and fourth select transistors Q2 and Q4, and the third select line. QL3 includes fifth and seventh selection transistors Q5 and Q7, and fourth selection line QL4 includes sixth and eighth selection transistors Q6 and Q8. The first and second global bit lines GB1 and GB2 are connected to the local bit line select circuit 130.

The first local bit line LB1 is connected to the source of the first select transistor Q1, and the second local bit line LB2 is connected to the source of the second select transistor Q2 through the second conductive portion DD2. The fifth local bit line LB5 is connected to the source of the fifth select transistor Q5 through the fifth conductive part DD5, and the sixth local bit line LB6 is connected to the sixth select transistor Q6. Is connected to the source of. The first global bit line GB1 is connected to the drains of the first, second, fifth, and sixth select transistors Q1, Q2, Q5, and Q6, respectively, and each of the first and sixth select transistors Q1 and Q6. The drain of is connected through the first conductive portion DD1 and the sixth conductive portion DD6. Therefore, the first global bit line GB1 is connected to the first, second, fifth and sixth local bit lines LB1 and LB2 by the switching action of the first, second, fifth and sixth selection transistors Q1, Q2, Q5 and Q6. , LB5 and LB6).

As in the connection method described above, the third local bit line LB3 is connected to the source of the third select transistor Q3, and the fourth local bit line LB4 is fourth selected through the fourth conductive part DD4. The seventh local bit line LB7 is connected to the source of the transistor Q4, and the seventh local bit line LB7 is connected to the source of the seventh selection transistor Q7 through the seventh conductive part DD7. It is connected to the source of the eighth select transistor Q8. The second global bit line GB2 is connected to the drains of the third, fourth, seventh and eighth select transistors Q3, Q4, Q7 and Q8, respectively, and the third and eighth select transistors Q3 and 8th select transistor Q8, respectively. The drain of is connected through the third conductive portion DD3 and the eighth conductive portion DD8. Accordingly, the second global bit line GB2 is connected to the third, fourth, seventh and eighth local bit lines LB3 and LB4 by the switching action of the third, fourth, seventh and eighth select transistors Q3, Q4, Q7 and Q8. , LB7 and LB8).

The first to eighth conducting portions DD1 to DD8 are formed of general transistors when the first to eighth selection transistors Q1 to Q8 are manufactured, and the transistor portions are opened using a cell source / drain mask and impurities It is formed by injecting ions in high energy and high concentration so that current can always pass.

The first to n word lines WL1 to WLn and the first to fourth select lines QL1 to QL4 are connected to the X-decoder 140, respectively. Each of the first and second global bit lines GB1 and GB2 is connected to the Y-decoder 150.

In FIG. 3, reference numeral 160 is an isolation region.

The operation method of the flash Y pyrom having the bit line division structure configured as described above is as follows.

A voltage is applied to at least one of the first to n word lines WL1 to WLn, a voltage is applied to at least one of the first to fourth select lines QL1 to QL4, and the first and second global bits. At least one of the plurality of memory cells of the memory cell block 200 is selected by applying a voltage to at least one of the lines GB1 and GB2 to perform a program, erase, or read operation.

For example, a state in which a voltage is applied to the first word line WL1 and a voltage is applied to the first select line QL1 to turn on the first and third select transistors Q1 and Q3. When the voltage is applied to the first global bit line GB1, the first global bit line GB1 is connected to the first local bit line LB1 through the first conductive part DD1 and the first selection transistor Q1. ) Is electrically connected to the first memory cell M1 to perform a program, erase, or read operation.

As described above, the present invention allows four local bit lines to be shorted on one global bit line so that the desired local bit line can be selected, and the capacitance can be reduced by dividing the bit lines to increase the operation speed of the device. Can be. The area of the cell array is increased by the area occupied by the local bit line selection circuit, but the increased area reduces the number of global bit lines, thus reducing the area of the area occupied by the Y-decoder, which adds about 10% more free area. This ensures high integration of the device. In addition, since one global bit line is contacted every four local bit lines, a contact process margin is secured so that the bit line division structure may be applied to a high technology cell.

Claims (5)

First and second memory cell blocks consisting of a plurality of word lines and a plurality of local bit lines; A local bit line select circuit comprising first to fourth select lines between the first memory cell block and the second memory cell block; A plurality of global bits configured to share two local bit lines of the first memory cell block and two local bit lines of the second memory cell block among the plurality of local bit lines through the local bit line selection circuit Lines; An X-decoder connected to the plurality of word lines and the first to fourth select lines; And And a Y-decoder connected to the plurality of global bit lines. 2. The flash Y pyrom cell array of claim 1, wherein the plurality of local bit lines are formed at two sides of one source line. The method of claim 1, wherein each of the first to fourth selection lines includes selection transistors, wherein the selection transistor of the first selection line is any one of two local bit lines of the global bit line and the first memory cell block. And a select transistor of a second select line is provided between the global bit line and another one of two local bit lines of the first memory cell block, and selects a third select line. A transistor is provided between the global bit line and any one of two local bit lines of the second memory cell block, and the select transistor of the fourth select line is selected from the global bit line and the second memory cell block. A flash Y pyrom cell array, characterized in that provided between the other of the two local bit lines. 4. The array of claim 3, wherein each of the local bit lines is connected to a source of each of the select transistors, and the global bit line is connected to a drain of each of the select transistors. 4. The flash Y pyrom cell array of claim 3, wherein at least one of the local bit lines is selected by a switching action of the selection transistors.