KR19990039639A - Frame Synchronization Detection Circuit in Wireless Asynchronous Transmission Mode System - Google Patents

Abstract

According to the present invention, when receiving data from the outside in a wireless ATM system or satellite communication, when reconstructing a frame, only three frame header / subframe header patterns are detected among four subframes stored in a buffer in a lost frame synchronization state. The present invention relates to a frame synchronization detecting circuit of an wireless asynchronous transmission mode (ATM) system that can confirm that the device has entered the frame synchronization state, and stores data corresponding to four subframes of the input data in a buffer and Detecting normal frame headers or three subframe headers enables the checking of frame synchronization.

Description

Frame Synchronization Detection Circuit in Wireless Asynchronous Transmission Mode System

The present invention relates to an asynchronous transfer mode (ATM) exchange, hereinafter abbreviated as 'ATM', particularly in case of reconstructing a frame when receiving data from the outside in a wireless ATM or satellite communication. A frame synchronization detecting circuit of a wireless asynchronous transmission mode (ATM) system that detects only three frame header / subframe header patterns among four subframes stored in a buffer in a frame synchronization loss state can be confirmed. will be.

In the conventional STM-1 frame structure, the frame synchronization function is performed with the received 8-bit parallel data.

Alarm signals detected during the deframer function are Out Of Frame (OOF) and Loss of Frame (LOF).

OOF alarm is declared when an error occurs in 4 consecutive sync patterns, and LOF alarm is declared when more than 24 OOF occur. When the frame sync status is maintained for 3 ms, the accumulator is reset to "0" to release and resynchronize. Return to the state.

The declaration and release states of the LOF are communicated to the CPU in an interrupt manner.

However, in the structure of the STM-1 frame based on the 155.52 Mbps rate, only 2 bytes of frame headers are allocated to 2430 bytes, so to enter the resynchronization state, the minimum next frame header byte must be counted. You may have to go through.

In addition, the frame header byte must be detected continuously for 3ms in the lost synchronization state to enter the frame synchronized state.

Therefore, in the conventional noisy wireless environment, there is a problem that a lot of time and data are lost to resynchronize with this structure.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and stores a number of subframes of received data and examines thousands of data thereof so that there is no fixed number of frame / subframe header errors. An object of the present invention is to provide a frame synchronization detecting circuit of a wireless asynchronous transmission mode (ATM) system capable of finding and declaring a synchronization state immediately.

In order to achieve the above object, the present invention can check the frame synchronization state by storing data corresponding to four subframes of input data in a buffer and detecting three normal frame headers or three subframe headers with respect to the data. It is characterized by the configuration so that.

1 is a frame synchronization detection circuit diagram of the wireless asynchronous transfer mode (ATM) switch of the present invention.

2 is a circuit diagram showing an embodiment according to the present invention;

3 is a diagram illustrating a frame synchronization state transition diagram according to the present invention.

<Explanation of symbols for main parts of drawing>

1: first register portion 2: first pattern matching circuit

3: first addition and count circuit 4: second register portion

5: second pattern matching circuit 6: second addition and count circuit

7: Oagate 8: first church

9: 2nd Non-Church 11-14: Register

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram for detecting an out-of-frame state of a frame according to the present invention. The first register part 1 includes a plurality of registers and shift registers for moving input data according to a frame synchronization clock. And the first pattern matching circuit 2 for outputting a high level when the frame header value and the subframe error value determined by the output of the first register unit 1 are matched, and a low level when they do not match. A second register comprising a first addition and counter circuit 3 for adding and counting the output of the first matching circuit 2, and a plurality of registers and shift registers for moving the input data according to the subframe synchronization clock. A second pattern matching circuit which compares the frame header value and the subframe error value determined at the output of the second register unit 4 with a high level when the unit 4 matches and a low level when the unit 4 does not match; 5) and a second addition and count circuit 6 for adding and counting the output of the first matching circuit 5, and the first addition and count circuit 3 and the second addition count circuit 6; A frame synchronizing position is detected by logically combining the first and second non-crossing paths (9) and the second non-crossing paths (9) for comparing an output with a reference value, and the output signals of the first and second addition and count circuits (2) and (6). It is composed of an oragate (7).

FIG. 2 shows a partial detailed circuit configuration of FIG. 1, wherein the first register unit 1 is composed of four registers and a shift register.

The first and second pattern matching circuits (2) and (5), which consist of eight flip-flops, are composed of NAND gates (N1-N4) that are non-logically multiplied with the output of the register as an input. Is the eight pull-flop and the shift register, 12-14 is made of the same structure as 11, SR is a shift register.

However, a reference value is set in the first and second addition and count circuits 3 so that the first and second addition and count circuits 3 are compared with the counted value and output.

According to the present invention configured as described above, the received data is input in accordance with the frame synchronization clock and the subframe synchronization clock.

Data passed through four registers and eight shift registers (SR) of eight deflip-flops are input to the first and second pattern matching circuits (2) (5) and compared with preset frame header values and subframe error values. "1" is output if there is a match and "0" is not matched.

Accordingly, the values output from the first and second pattern matching circuits 2 and 5 are input to the first and second addition and count circuits 3 and 6, added and counted, and then the first and second values are output. The comparison circuit 8 (9) is compared with a preset threshold (e.g., 3). If one of the two headers counts the value "1" equal to or greater than 3, the frame sync position is detected, and less than 3 If yes, the next bit is checked to determine the synchronization status.

On the other hand, the 2-byte frame header, subframe header, and frame structure of 45 cells use several cell header error detection methods (ie, HEC) to improve cell boundary identification in high noise environments. Patterns are provided to perform frame functions from received 8-bit parallel data.

The periodic arrival of a frame header pattern and a subframe header pattern is used to confirm that the system is synchronized.

However, in order to return from the lost synchronization state to the frame synchronization state, it is performed when three error-free frame / subframe headers are found in the last four subframes.

Herein, four subframe block headers are found to shorten the frame synchronization detection time.

In order to reduce the frame synchronization detection time, a buffer capable of storing four subframe blocks is adopted.

3 shows a frame synchronization state transition diagram. In the OOP state, data of four subframes is passed through a frame header pattern and a subframe header pattern matching circuit to count the number of matches and enter a synchronization state if three or more.

That is, if X (eg 3) frames or subframe headers without error are found within Y (eg 4) subframes in the OOF state, the result is FS state. When a subframe header or frame header error and M cell header errors are detected, an OOF state is detected.

The four subframes are 5 header bytes + 5 cells x 53 bytes = 270 bytes x 8 = 2160 bits.

As described above, the present invention stores four subframes in the buffer for the received data, inputs only the data into the frame / subframe header pattern matching circuit, and finds the number of times of matching. If found, there is an effect that can confirm the motivation.

Claims (4)

A first register unit for moving the input data according to the frame sync clock and a frame header value and a subframe error value determined by the output of the first register unit are compared and output a high level when they match and a low level when they do not match. A first pattern matching circuit, a first addition and counter circuit for adding and counting the output of the first matching circuit, a second register unit for moving the input data according to the subframe synchronization clock, and the second register A second pattern matching circuit for outputting a high level when the frame header value and the subframe error value matched at the negative output match and a low level when they do not match; and a second pattern matching circuit for adding and counting the output of the first matching circuit. Two addition and count circuits, a first and second comparison circuits for comparing outputs of the first and second addition and count circuits with reference values, and the first and second addition and count circuits. Wireless asynchronous transfer mode by a logical OR output signal, characterized in that consisting of Iowa gate for detecting a frame synchronization position (ATM) frame synchronization detecting circuit of the system. The frame synchronization detection circuit of claim 1, wherein the first and second register units comprise a plurality of registers and a shift register. 3. The frame synchronization detection circuit of claim 2, wherein the register comprises a plurality of flip flops. The frame synchronization detection circuit of claim 1, wherein the first and second pattern matching circuits comprise a plurality of NAND gates that nonlogically multiply an output value of an input register.