KR19990035653A - Full-Band Phaser with Automatic Band-Scan - Google Patents

Abstract

In the present invention, a full-band phaser with an automatic band-scan function is disclosed, which is provided with a dedicated decoder for performing the necessary decoding process. Moreover, the dedicated decoder has a channel switching function that assists the microprocessor in the pager to scan all the available channels to find a suitable channel for pager communication. The dedicated decoder also controls the enable / disable operation of the PLL frequency synthesizer and IF demodulator in the pager. To reduce power consumption, these two components, the PLL frequency synthesizer and the IF demodulator, are deactivated whenever they are not active. By using a dedicated decoder separate from the microprocessor, system design work becomes much simpler when compared to a technique in which a conventional microprocessor controls all of the pager functions. The microprocessor of the pager according to the invention does not need to be structurally complex to contain the necessary pager communication protocols; Thus, any product's microprocessor and PLL frequency synthesizer can be used to make the pager.

Description

FULL-BAND PAGER WITH AUTO BAND-SCAN CAPABILITY

The present invention is directed to a full-band phaser with an automatic band-scan function that can automatically scan the frequency bands of all useful channels to find a suitable channel for pager communication, more specifically called beeper. It is about.

A pager is a pocket-sized electrical device that can display a message, often accompanied by an alarm, in response to a modulated radio-frequency (RF) radio wave signal transmitted freely from a distant sender by a paging base station. It can be. This can inform the user carrying the pager of important messages from the caller or the receiving telephone number. Pager is generally carried around by people, so they don't miss a call. Since the pager operates on radio propagation signals, a specific frequency band is designated by the pager system in a particular area and used to propagate the pager message signal to a pager in the same area.

At present, there is not yet a standard frequency band for pager communication. So different bands are used in different countries, even in different countries. This limits the use of the pager when the user moves from one place to another. To solve this problem, Phaser provides multiple channels for all frequency bands that are commonly used for phaser communication worldwide. The automatic tuning of the phaser to the frequency band of the channel suitable for phaser communication is called the band-scan function. This kind of pager is customarily a full-band pager.

1 is a block diagram of a conventional full-band phaser designed to European standards. This full-band phaser is comprised of a microprocessor 11, a phase-locked loop (PLL) frequency synthesizer 12, a superheterodyne receiver 13, an intermediate frequency (IF) demodulator 14, and an output device 15. Include.

The microprocessor 11 uses two signals PLEN (phase lock enable) and radio-frequency enable (RFEN) to control the activation / deactivation of the PLL frequency synthesizer 12 and the IF demodulator 14, respectively. In order to reduce the power consumption, it is activated only during the operation time. When the PLEN signal is switched to the high-voltage state, the PLL frequency synthesizer 12 is activated; And when switched to the low-voltage state, the PLL frequency synthesizer 12 is deactivated. Similarly, if the RFEN signal is switched to a high-voltage state, the IF demodulator 14 is activated; And when switched to the low-voltage state, the IF demodulator 14 is deactivated.

When the above described phaser starts to operate, the microprocessor 11 sends the channel-selection parameter to the PLL frequency synthesizer 12 via the data bus 103, during which the PLL frequency synthesizer 12 and the IF demodulator 14 Activate. This function causes the PLL frequency synthesizer 12 to send an oscillating frequency (hereinafter referred to as a local-oscillator frequency) to the superheterodyne receiver 13 via the signal line 102, where the local-oscillator frequency is an antenna. And synthesized with the received RF carrier signal. The received RF carrier signal is thus converted into an intermediate frequency (IF) signal. The superheterodyne process performed by the superheterodyne receiver 13 to obtain the IF carrier signal is a well known technique in the field of electronic communication systems and will not be described here in detail. The output IF carrier signal from the superheterodyne receiver 13 is transmitted via the signal line 106 to the IF demodulator 14 to demodulate to restore the original encoded form of the pager message signal from the paging station. Rate. The demodulated data from the IF demodulator 14 is transmitted via the data bus 108 to the microprocessor 11 for decoding.

The decoding process performed by the microprocessor 11 is designed in accordance with the European Telecommunications Standards (ETS) by the European Radio Message System (ERMES), which modulates the modulated data from the IF demodulator 14 from the sender. Can be decoded to restore the message to its original form. This pager message is then sent to the output device 15 via the data bus 105. In general, output device 15 includes a speaker (not shown) for generating an alarm sound and a digital display (not shown) for displaying pager messages to attract the attention of the person carrying the pager. do.

As described above, the microprocessor 11 is a key element of the phaser, which performs and controls the core functions of the phaser, among which the control of the PLL frequency synthesizer 12 for frequency fixing, demodulating the received signal. Control of the IF demodulator 14 for control, control for decoding the demodulated data from the IF demodulator 14, and PLL frequency synthesizer 12 and IF demodulator 14 at a suitable time for the purpose of saving power consumption. Controls to enable / disable the device are included. So the control firmware built into the microprocessor 11 is very complicated. Moreover, since the design of the firmware programs of the microprocessor 11 must follow the standard defined by ERMES, the firmware developer can design the firmware program required for the microprocessor 11 to be the European Telecommunication Standards. Be familiar with the ETS 300 133 regulations established by the Institute. These constraints make the development of firmware a lot of time.

It is therefore an object of the present invention to provide a decoder dedicated to the decoding process required in place of the microprocessor 11 in the above-described prior art pager in order to reduce the workload of the microprocessor 11 in order to increase the efficiency of the phaser. To provide a full-band phaser with

It is yet another object of the present invention to provide a dedicated decoder that performs the decoding process of the phaser in accordance with the standards of the ERMES specification, and a full-band provided with an automatic band-scan function which allows the phaser to quickly find a suitable channel for phaser communication. To provide a pager.

It is still another object of the present invention to provide a full-band pager provided with a dedicated decoder that can shorten the development period of the phaser.

It is a further object of the present invention to provide a dedicated decoder which is used to activate / deactivate the PLL frequency synthesizer and IF demodulator at a suitable time to reduce power consumption.

It is still another object of the present invention that the microprocessor and the PLL frequency synthesizer required in the pager may be non-dedicated, and the microprocessor and PLL frequency synthesizers of various products can be selected and used.

1 is a block diagram of a full-band phaser according to the prior art;

2 is a block diagram of a full-band phaser according to the present invention;

3 is a diagram illustrating an automatic band-scan process performed by the full-band phaser of the present invention;

4 is a timing diagram of various signals of a full-band phaser according to the present invention;

5A is a flow chart showing the steps involved in the automatic band-scan process performed by the full-band pager of the present invention;

5B is a flow chart showing the steps connected to the flow chart of FIG. 5A.

Explanation of symbols on the main parts of the drawing

21 microprocessor 22 PLL frequency synthesizer

23: super heterodyne receiver 24: IF demodulator

25: decoder 26: channel register

27: output device 204: antenna

In accordance with the objects of the present invention described above, a full-band phaser with an auto-band scan function is provided. The full-band phaser of the present invention includes the following components.

(a) a superheterodyne designated for a frequency band of a selected channel, for receiving a modulated RF carrier signal carrying a pager message signal from the selected channel and down converting the received RF carrier signal to a modulated IF carrier signal; receiving set; (b) a PLL frequency synthesizer for generating a specific local-oscillator frequency corresponding to the selected channel; (c) an IF demodulator for demodulating the IF carrier signal from the superheterodyne receiver into demodulated data representing the original encoded version of the pager message; (d) the demodulated data from the IF demodulator; Decode the PLL to obtain decoded data representing the original form of the paser message and activate the PLL frequency synthesizer and IF demodulator only when the paser is tuned to the correct channel to receive the modulated RF carrier signal carrying the paser message. A decoder; (e) may be coupled to a decoder and a PLL frequency synthesizer, control the display of decoded pager messages on the display of the pager, and generate specific local-oscillator frequencies in response to channel-change request signals from the decoder. Microprocessor that can control the PLL frequency synthesizer.

With the system configuration described above, the phaser performs an automatic band-scan operation that includes the following steps:

(1) the decoder activating the IF demodulator and the PLL frequency synthesizer to obtain demodulated data from the IF demodulator in response to the RF carrier signal currently received from the currently selected channel;

(2) the decoder confirming that the demodulated data from the IF demodulator contains a correct synchronization code;

(2-1) if it contains the correct sync code, the decoder decodes the demodulated data from the IF demodulator to obtain the original form of the pager message and associated sync data;

(2-2) Otherwise, the decoder deactivates the PLL frequency synthesizer and the IF demodulator and sends a channel-change request signal to the microprocessor so that the microprocessor can use the default channel-selection parameter. Changing to correspond to one of the following; And repeating steps (1) and (2) until a suitable channel is found.

In the above-mentioned full-band pager, the decoder is designed in accordance with ETS 300 133-4, and can support all 16 channels for pager communication, each of which is represented by the following ID numbers. : 0, 2, 4, 6, 8, A, C, E, F, D, B, 9, 7, 5, 3, 1, is selected cyclically to find one suitable for pager communication.

According to another aspect, the present invention provides an automatic band-scan method for use in a phaser, the phaser including a superheterodyne receiver and a superheterodyne receiver for receiving an RF carrier signal carrying a pager message signal. PLL frequency synthesizer for generating a local-oscillator frequency to down-convert the received RF carrier signal to an IF carrier signal, and an IF for demodulating the output IF carrier signal from the superheterodyne receiver. It includes a demodulator, and a microprocessor combined with a decoder and a PLL frequency synthesizer. The automatic band-scan method includes the following steps:

(1) activating the microprocessor to input a channel number into the channel register of the decoder;

(2) activating the microprocessor to input a channel-selection parameter corresponding to the channel number stored in the channel register to the PLL frequency synthesizer;

(3) activating the decoder to generate a phase locked signal with a PLL frequency synthesizer and a radio-frequency enabled signal with an IF demodulator;

(4) activating the PLL frequency synthesizer to generate a local-oscillator frequency in accordance with the channel-selection parameter;

(5) activating the superheterodyne receiver to down-convert the RF carrier signal received from free space with the local-oscillator frequency to an IF carrier signal;

(6) activating the IF demodulator to demodulate the IF carrier signal from the superheterodyne receiver;

(7) activating the decoder to confirm that the demodulated data from the IF demodulator contains a sync code that matches the channel number stored in the current channel register;

If the sync code is included correctly, jump to step (8); Or jump to step 9;

(8) performing the following detailed steps;

Activating the decoder to decode the demodulated data from the IF demodulator to obtain the original form and associated sync data of the pager message, and then send the sync data to the microprocessor;

Activating the microprocessor to generate a pager message corresponding to the synchronization data;

After the operation of decoding the demodulated data from the IF demodulator is completed, activating the decoder to deactivate the PLL frequency synthesizer and the IF demodulator;

(9) performing the following detailed steps;

Activating the decoder to send a channel-change request signal to the microprocessor;

Activating the microprocessor to change its default channel-selection parameter to a new one;

Activating the decoder to deactivate the PLL frequency synthesizer and the IF demodulator;

Activating the microprocessor to input new channel-selection parameters into the PLL frequency synthesizer;

Activating the decoder to activate the PLL frequency synthesizer and the IF demodulator, and modifying the channel number stored in the channel register to a new number corresponding to the newly selected channel-selection parameter; And

Step back to step (4).

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

FIG. 2 is a block diagram illustrating a full-band phaser according to a preferred embodiment of the present invention, which includes a microprocessor 21, a PLL frequency synthesizer 22, a superheterodyne receiver 23, an IF demodulator 24, and a dedicated decoder. 25, an output device 27. The superheterodyne receiver 23 may combine the RF carrier signal received from the antenna 204 with the output frequency from the PLL frequency synthesizer 22 and convert it into a conventional intermediate-frequency (IF) carrier signal. (PLL frequency synthesizer 22 operates as a local oscillator for superheterodyne receiver 23 and hereinafter the output of PLL frequency synthesizer 22 is referred to as local-oscillator frequency.) Next, superheterodyne receiver 23 The output IF carrier signal is sent via signal line 206 to IF demodulator 24 to recover the original encoded pager message signal from the paging station.

Once the RF carrier signal is received by the phaser's antenna 204, the RF carrier signal is first down-converted by the superheterodyne receiver 23 to be combined with the output frequency of the PLL frequency synthesizer 22 to generate an IF carrier signal. do. This IF carrier signal is transmitted via signal line 206 to IF demodulator 24. The superheterodyne process performed by the superheterodyne receiver 23 to obtain an IF carrier signal is a well known technique in the field of telecommunications and will not be described here. IF demodulator 24 then demodulates the IF carrier signal to recover the original encoded version of the pager message from the paging station. The demodulated data from the IF demodulator 24 is transmitted to the decoder 25 via the data bus 208 and decoded according to various standards to obtain the original form of the pager message and the associated sync signal.

Decoder 25 is also tasked with controlling the activation / deactivation of PLL frequency synthesizer 22 and IF demodulator 24. Decoder 25 uses two signals, PLEN (phase lock enable) and RFEN (radio-frequency enable), to enable / disable control of PLL frequency synthesizer 22 and IF demodulator 24, respectively. PLL frequency synthesizer 22 is activated when the PLEN signal is switched to the high-voltage state and deactivated when the PLEN signal is switched to the low-voltage state. Similarly, IF demodulator 24 is activated when the RFEN signal is switched to the high-voltage state and deactivated when the RFEN signal is switched to the low-voltage state.

The microprocessor receives the decoded data from the decoder 25 via the data bus 207 and then sends a pager message in the decoded data to the output device 27. In general, the output device 27 has a built-in speaker (not shown) to generate an alarm sound to attract the user's attention, and a digital display for displaying an incoming message or a telephone number of the side of the call receiving party. (Not shown).

PLL frequency synthesizer 22 is controlled by microprocessor 21 to generate a local-oscillator frequency that corresponds to the current default channel-selection parameter in microprocessor 21. In the design of the pager, the channel currently selected at the decoder 25 must correspond to the channel-selection parameter specified by the microprocessor 21. To this end, the decoder 25 sends a channel change request signal XCNCG to the microprocessor 21. The XCNCG signal is normally in a low-voltage state and then switched to a high-voltage state when a change in the default channel-selection parameter in the microprocessor 21 is requested. In response to the XCNCG and PLEN signals from decoder 25, microprocessor 21 may change its channel-selection parameters according to the channel currently selected at decoder 25.

The full-band phaser of the present invention performs an automatic band-scan operation to find a channel suitable for phaser communication by the following working steps. In a first step, the decoder 25 activates the PLL frequency synthesizer 22 and the IF demodulator 24 to pass the RF carrier signal received by the antenna 204 by the superheterodyne receiver 23 to the IF carrier signal. To down-convert. This IF carrier signal is transmitted via signal line 206 to IF demodulator 24 to demodulate the original encoded version of the pager message sent by the sender. If the demodulated data from the IF demodulator 24 has the correct sync code, it indicates that the currently selected channel is suitable. As a result, decoder 25 applies the necessary decoding process to the demodulated data from IF demodulator 24 to obtain the original form of the pager message sent by the sender and retrieve the decoded data via data bus 207. Transfer to microprocessor 21.

If the demodulated data from the IF demodulator 24 has an incorrect sync code, it indicates that the currently selected channel is wrong. As a result, the decoder 25 sends the high-voltage XCNCG signal to the microprocessor 21 to request a change to the current default channel-selection parameter in the microprocessor 21, during which the PLL frequency synthesizer 22 And IF demodulator 24 are deactivated. In response to the XCNCG signal, the microprocessor 21 changes its default channel-selection parameter and then sends this new channel-selection parameter over the data bus 203 to the PLL frequency synthesizer. Then, when the PLL frequency synthesizer 22 is activated again, it outputs a new local-oscillator frequency corresponding to the newly received channel-selection parameter from the microprocessor 21, which is a signal line ( Via 202 to the superheterodyne receiver 23. This new local-oscillator frequency causes the superheterodyne receiver 23 to tune to a different frequency band (i.e., another channel). The downconverting / demodulating / decoding process of the above-described signal is then repeated again, and the decoder 25 checks the synchronization code in the demodulated data from the IF demodulator 24 to confirm that it is appropriate. This operation is repeated until a suitable channel for pager communication is found.

3 is a schematic diagram illustrating an automatic band-scan operation to find a channel suitable for pager communication, performed by the full-band pager of the present invention. In this preferred embodiment, the decoding process performed by the decoder 25 is designed to comply with the ETS 300 133-4 specification, with the following ID numbers: 0, 2, 4, 6, 8, A, C It can support all 16 channels represented by, E, F, D, B, 9, 7, 5, 3, 1 respectively. When the automatic band-scan operation is performed, the phaser scans the frequency bands of these channels one by one in the order indicated above.

As shown in FIG. 3, each of the 16 channels is sequentially in the investigations A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P. It is further divided into 16 data groups that are represented. Each pager user has its own unique pager address that indicates belonging to one of the data groups. Each data group contains two to ^thirty five or more pager addresses. The local paging station propagates pager messages encapsulated into 16 data groups in channels in a periodic manner. Thus, pager messages belonging to the same data group are intermittently air-broadcasted at predetermined time intervals, eg every 12 seconds. That is, in order for a pager message to be propagated to a particular pager user, the paging station first finds a data group to which the receiver's pager address belongs, and then broadcasts the pager message to the belonging data group.

In addition, the channels shown in FIG. 3 are synchronized in such a way that transmission of the data groups of the current channel is one data group behind the data groups of the preceding channel. For example, at the time when data group B of channel 0 is propagated, data group A of channel 2 (channel after channel 0) is propagated in synchronization; When the data group C of channel 0 is propagated, the data group B of channel 2 is propagated in synchronization.

2 to 3, when the phaser is to receive data group A of channel 0, PLL frequency synthesizer 22 is required to output the local-oscillator frequency corresponding to the frequency band of channel 0. This causes the superheterodyne receiver 23 to discard all RF carrier signals in frequency bands other than the channel 0 frequency band. The picked-up RF carrier signal is then down-converted by the superheterodyne receiver 23 into an IF carrier signal, which is demodulated by the IF demodulator 24 to be originally encoded of the pager message. Get the data. The demodulated data from the IF demodulator 24 is transmitted to the decoder 25 via the data bus 208. Decoder 25 then checks whether the demodulated data from IF demodulator 24 has the correct sync code. If so, it indicates that the transmitted signal was not interfered by noise and channel 0 is a suitable channel.

As a result, the phaser tunes the wavelength to channel zero. For example, if current channel 0 propagates a pager message in data group A, decoder 25 activates PLL frequency synthesizer 22 and IF demodulator 24, thereby providing pager message in data group A in channel 0. The RF carrier signal comprising the signal is received by the pager. As mentioned above, data group A appears intermittently on channel 0 every 12 seconds. As a result, the decoder 25 activates the PLL frequency synthesizer 22 and the IF demodulator 24 every 12 seconds while the data group of paser address appears on the channel, while the data group of paser address is not propagated. If not, disable them. This reduces the power consumption of the pager while the data group of pager addresses is not propagated.

Decoder 25 includes channel register 26 shown in FIG. In this preferred embodiment, as an example, channel register 26 is a 4-bit register for storing the ID number of the currently selected channel. Decoder 25 may change the value of channel register 26 to find another channel if the currently selected channel is not suitable. Thus, when the channel-change request signal is generated, the microprocessor 21 changes the current default channel-selection parameter according to the value of the channel register 26.

4 shows the various states of the PLEN and XCNCG signals generated by the decoder 25 to map the current channel-selection parameters in the microprocessor 21 to the channel numbers stored in the channel registers 26 of the decoder 25. It is a waveform diagram for demonstrating the timing of these. 4 to 2, if the channel currently selected by the pager is wrong and the next channel is checked, the decoder 25 generates a pulse 41 on the XCNCG signal to the microprocessor 21. In response to the rising edge of pulse 41, microprocessor 21 changes its current default channel-selection parameter to the next one. Decoder 25 then switches the PLEN signal to a low-voltage state as indicated by reference numeral 43 to deactivate PLL frequency synthesizer 22. In response to the low-voltage state of the PLEN signal, the microprocessor 21 sends a new channel-selection parameter to the PLL frequency synthesizer 22 that the PLL frequency synthesizer 22 newly receives from the microprocessor 21. Generate a new local-oscillator frequency corresponding to. When decoder 25 switches the PLEN signal back to the high-voltage state as indicated by reference numeral 45, PLL frequency synthesizer 22 is activated. On the other hand, in the high-voltage state 45, the decoder 25 changes its channel number according to the channel-selection parameter newly designated in the microprocessor 21.

4, it can be seen that when decoder 25 sends another pulse 47 following pulse 41 as an XCNCG signal, microprocessor 21 again changes its default channel-selection parameter to the next one. . However, the high-voltage state in the PLEN signal is maintained for an extended period of time as shown in FIG. As a result, the channel number specified in the decoder 25 and the corresponding channel-selection parameter of the PLL frequency synthesizer 22 are not changed. This is because the decoder 25 must continue to decode the signal received from the currently selected channel for longer than the time interval between two consecutive data groups.

5A is a task flow diagram illustrating some of the work steps associated with an automatic band-scan operation performed by a pager in accordance with the present invention to scan all frequency bands of all useful channels to find a suitable channel for pager communication. to be. 5A-2, after the phaser starts operation, step 51 is performed, where the microprocessor 21 optionally defaults one of the available channels for pager communication, and then selects the selected channel. Is input to the channel register 26 of the decoder 25. In this preferred embodiment, the microprocessor 21 is one of sixteen channels 0, 2, 4, 6, 8, A, C, E, F, D, B, 9, 7, 5, 3, 1 Select to input the ID number of the selected channel into the 4-bit channel register 26 of the decoder 25. In a subsequent step 52, according to the frequency characteristic of the PLL frequency synthesizer 22, the microprocessor 21 selects the corresponding channel of the currently selected channel (the ID of this channel is currently stored in the channel register of the decoder 25). The parameter is calculated, which causes the PLL frequency synthesizer 22 to generate a corresponding local-oscillator frequency that locks the superheterodyne receiver 23 to the frequency band of the currently selected channel. The calculation of channel selection parameters for controlling the PLL frequency synthesizer 22 to generate the corresponding local-oscillator frequency will not be described in detail because it is obvious to those skilled in telecommunications. After the channel-selection parameters are obtained, these parameters are transferred from the microprocessor 21 to the PLL frequency synthesizer 22. In response to this channel-selection parameter, the PLL frequency synthesizer 22 generates the corresponding local-oscillator frequency to fix the superheterodyne receiver 23 to the frequency band of the currently selected channel.

In a subsequent step 53, the decoder 25 switches the PLEN signal to a high-voltage state so that the PLL frequency synthesizer 22 is activated to generate a local-oscillator frequency in accordance with the channel-selection parameter received from the microprocessor 21. . The output local-oscillator frequency from the PLL frequency synthesizer 22 is sent to the superheterodyne receiver 23 so that all the RF carrier signals the superheterodyne receiver 23 receives from a band other than within the frequency band of the currently selected channel. Let them go The received RF carrier signal is down-converted to an IF carrier signal by the superheterodyne receiver 23. On the other hand, the decoder 25 switches the RFEN signal to the high-voltage state so that the IF demodulator 24 is activated to demodulate the IF carrier signal to obtain a pager message in the original encoded form at the paging station.

In a subsequent step 54, demodulated data from the IF demodulator 24 is transmitted to the decoder 25 via the data bus 208. The decoder 25 checks whether the demodulated data from the IF demodulator 24 has the correct sync code. In the next step 55, if the demodulated data from the IF demodulator 24 has the correct sync signal, the operation is continued in step 56 (continued in FIG. 5B in conjunction with ⓐ) because it indicates that the currently selected channel is suitable. Going to; If not, go to step 591 (continued in FIG. 5B in connection with ⓑ).

FIG. 5B shows the work steps following the work flow of FIG. 5A. Beginning with ⓐ following step 55 where the currently selected channel is determined to be suitable, in step 56 following, the XCNCG signal is held in a low-voltage state, causing the phaser to tune to the frequency band of the currently selected channels for pager communication. Then, the demodulated data from the IF demodulator 24 is decoded to recover the pager message and the sync data. In a subsequent step 57, the decoded data is sent to the microprocessor 21. The microprocessor 21 sends a pager message in the decoded data to the output device 27 for display.

In a subsequent step 58, the decoder 25 periodically activates the PLL frequency synthesizer 22 and the IF demodulator 24 during which the RF carrier signal carrying the pager message from the currently selected channel is received. For all other times, decoder 25 deactivates PLL frequency synthesizer 22 and IF demodulator 24 to reduce power consumption.

Beginning with ⓑ following step 55 where the currently selected channel is determined to be inadequate, in step 591 that follows, the XCNCG signal is switched to a high-voltage state, such that the channel currently selected by the microprocessor 21 is unsuitable. Signals that the default channel-selection parameter should be changed to the next one. In a subsequent step 592, the microprocessor 21 changes its default channel-selection parameter to the next one in response to the XCNCG signal. In a subsequent step 593, the decoder 25 switches the PLEN signal and the RFEN signal to a low-voltage state, thereby deactivating the PLL frequency synthesizer 22 and the IF demodulator 24.

In a subsequent step 594, the microprocessor 21 inputs a new channel-selection parameter to the PLL frequency synthesizer 22. In a subsequent step 595, the decoder 25 switches the PLEN signal and the RFEN signal to a high-voltage state to activate the PLL frequency synthesizer 22 and the IF demodulator 24, and the current channel number stored in the channel register 26. Is changed to the new one corresponding to the newly specified channel-selection parameter. In a subsequent step 596, the operation returns to step 54 and repeats the steps following step 54 until a suitable channel is found.

In conclusion, the full-band phaser of the present invention is provided with a dedicated decoder that performs the necessary decoding process instead of the microprocessor as in the prior art. Dedicated decoders are designed to comply with the ETS regulations for pager communication. The dedicated decoder also has a channel switching function that assists the microprocessor in the pager to scan all of the available channels to find the appropriate channel for pager communication.

The dedicated decoder also controls the enable / disable operation of the PLL frequency synthesizer and IF demodulator in the pager. To reduce power consumption, these two components are deactivated every time they are not active. By using a dedicated decoder separate from the microprocessor, system design work becomes much simpler when compared to a technique in which a conventional microprocessor controls all of the pager functions. The microprocessor of the pager according to the invention does not need to be structurally complex to contain the necessary pager communication protocols; Thus, any product's microprocessor and PLL frequency synthesizer can be used to make the pager.

The present invention has been described with reference to preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, various modifications and similar configurations are included. Thus, the scope of the claims should be construed as broadly as possible to encompass all such variations and similar configurations.

Claims (14)

In a full band-faser with automatic band-scanning, A superheterodyne receiver designated for the frequency band of the selected channel, for receiving a modulated RF carrier signal carrying a pager message signal from the selected channel and down-converting the received RF carrier signal to a modulated IF carrier signal; ; A PLL frequency synthesizer for generating a specific local-oscillator frequency corresponding to the selected channel; An IF demodulator for demodulating the IF carrier signal from the superheterodyne receiver into demodulated data representing the original encoded version of the pager message signal; Decode the demodulated data from the IF demodulator to obtain decoded data representing the original form of the paser message, and the PLL only when the paser is tuned to the correct channel to receive the modulated RF carrier signal carrying the paser message. A decoder capable of activating the frequency synthesizer and the IF demodulator; And Coupled to the decoder and the PLL frequency synthesizer and capable of controlling the display of a decoded pager message on the pager and generating a specific local-oscillator frequency in response to a channel-change request signal from the decoder. A microprocessor capable of controlling the PLL frequency synthesizer to include; The phaser has the following steps: (1) activating the decoder to activate the IF demodulator and the PLL frequency synthesizer to obtain demodulated data from the IF demodulator in response to an RF carrier signal currently received from a currently selected channel; (2) activating the decoder to confirm that the demodulated data from the IF demodulator contains the correct synchronization code; (2-1) if it contains the correct sync code, the decoder decodes the demodulated data from the IF demodulator to obtain the original form and associated sync data of a pager message; (2-2) Otherwise, activate the decoder, deactivate the PLL frequency synthesizer and the IF demodulator, and send a channel-change request signal to the microprocessor so that the microprocessor receives a default channel-selection parameter. changing the selection parameter) to correspond to one of the available channels; And repeating steps (1) through (2) until a suitable channel is found; performing an automatic band-scanning operation that scans channels useful for finding a channel suitable for phaser communication. Band-paser. The method of claim 1, The decoder is designed according to ETS 300 133-4 and can support all 16 channels for pager communication, each of which is indicated by the following ID numbers: 0, 2, 4, 6, 8, A, C, E, F, D, B, 9, 7, 5, 3, 1, full band-pacer, characterized in that it is selected recursively to find one suitable for phaser communication. The method of claim 2, Wherein said decoder comprises a channel register for storing a channel number of a currently selected channel. The method of claim 3, wherein And the channel-change request signal is normally maintained in a low-voltage state and then switched to a high-voltage state when the currently selected channel is requested to change to the next one. The method of claim 4, wherein The decoder generates a phase locked signal to control the enable / disable state of the PLL frequency synthesizer, wherein the PLL frequency synthesizer is activated when the phase locked signal is switched to a high-voltage state, and the phase locked signal is low- Full band-pacifier, characterized in that when switched to the voltage state is deactivated. The method of claim 5, Step (2-2) is as follows: Activating the decoder to switch a channel-change request signal to a high-voltage state to change a default channel-change parameter in the microprocessor; And Activating the decoder to switch a phase locked signal to a low-voltage state to deactivate the PLL frequency synthesizer and cause the microprocessor to input a default channel-selection parameter to the PLL frequency synthesizer. Band-paser. The method of claim 1, The decoder activates and deactivates the PLL frequency synthesizer and the IF demodulator during a decoding process on the demodulated data from the IF demodulator, which is the correct pager data received from the currently selected channel. Full-pager. The method of claim 3, wherein And said channel register is a 4-bit register. The method of claim 3, wherein The decoder controls the activation / deactivation state of the IF demodulator by activating a radio-frequency activation signal, wherein the IF demodulator is activated when the radio-frequency activation signal is switched to a high-voltage state, and the radio-frequency activation signal is low. Full band-pacer, characterized in that disabled when switched to the voltage state. In a full band-faser with automatic band-scanning, A superheterodyne receiver designated for the frequency band of the selected channel, for receiving a modulated RF carrier signal carrying a pager message signal from the selected channel and down-converting the received RF carrier signal to a modulated IF carrier signal; ; A PLL frequency synthesizer for generating a specific local-oscillator frequency corresponding to the selected channel; An IF demodulator for demodulating the IF carrier signal from the superheterodyne receiver into demodulated data representing the original encoded version of the pager message signal; Decoding the demodulated data from the IF demodulator to obtain decoded data representing the original form of the pager message; Generate a radio-frequency activation signal for controlling the activation / deactivation state of the PLL frequency synthesizer, wherein the PLL frequency synthesizer is activated when the radio-frequency activation signal is switched to a high-voltage state and the radio-frequency activation signal is low -Deactivated when switched to the voltage state; A decoder that activates the PLL frequency synthesizer and the IF demodulator only when the phaser is tuned to the correct channel to receive a modulated RF carrier signal carrying a pager message; Coupled to the decoder and the PLL frequency synthesizer, and capable of controlling the display of a decoded pager message on the pager, and generating a local-oscillator frequency in response to a channel-change request signal from the decoder. A microprocessor capable of controlling a PLL frequency synthesizer, said microprocessor changing its default channel-selection parameter when said channel-change request signal is switched from a low-voltage state to a high-voltage state; The phaser has the following steps: (1) activating the decoder to activate the IF demodulator and the PLL frequency synthesizer to obtain demodulated data from the IF demodulator in response to an RF carrier signal currently received from a currently selected channel; (2) activating the decoder to confirm that the demodulated data from the IF demodulator contains the correct synchronization code; (2-1) if it contains the correct sync code, the decoder decodes the demodulated data from the IF demodulator to obtain the original form of the pager message and the combined sync data; (2-2) otherwise, activating the decoder to switch the channel-change request signal to a high-voltage state, such that the microprocessor changes its default channel-selection parameter in response to the newly selected channel. Wow; Activating the decoder to switch the channel-change request signal to a low-voltage state, thereby deactivating a PLL frequency synthesizer and causing the microprocessor to input a new default channel-selection parameter to the PLL frequency synthesizer; after that Repeating said steps (1) to (2) until the demodulated data from the IF demodulator is the pager data from the currently selected channel. The method of claim 10, The decoder is designed according to ETS 300 133-4 and can support all 16 channels for pager communication, each of which is indicated by the following ID numbers: 0, 2, 4, 6, 8, A, C, E, F, D, B, 9, 7, 5, 3, 1, full band-pacer, characterized in that it is selected recursively to find one suitable for phaser communication. The method of claim 10, And the decoder comprises a 4-bit channel register for storing the channel number of the currently selected channel. An automatic band-scan method for use in a phaser, the phaser comprising: a superheterodyne receiver for receiving RF carrier signals carrying pager message signals, and the RF carrier signal received by the superheterodyne receiver for an IF carrier. A PLL frequency synthesizer for generating a local-oscillator frequency to down-convert to the signal, an IF demodulator for demodulating the output IF carrier signal from the superheterodyne receiver, and a demodulator from the IF demodulator A decoder having a channel register for decoding the rated data, and a microprocessor coupled to the decoder and the PLL frequency synthesizer, the method comprising the following steps: (1) activating the microprocessor to input a channel number into the channel register of the decoder; (2) activating the microprocessor to input a channel-selection parameter corresponding to the channel number stored in the channel register to the PLL frequency synthesizer; (3) activating the decoder to generate a phase locked signal with a PLL frequency synthesizer and a radio-frequency enabled signal with an IF demodulator; (4) activating the PLL frequency synthesizer to generate a local-oscillator frequency in accordance with the channel-selection parameter; (5) activating the superheterodyne receiver to down-convert the RF carrier signal received from free space with the local-oscillator frequency to an IF carrier signal; (6) activating the IF demodulator to demodulate the IF carrier signal from the superheterodyne receiver; (7) activating the decoder to confirm that the demodulated data from the IF demodulator contains a sync code that matches the channel number stored in the current channel register; If the sync code is included correctly, jump to step (8); Or jump to step 9; (8) performing the following detailed steps; Activating the decoder to decode the modulated data from the IF demodulator to obtain the original form and associated sync data of the pager message, and then send the sync data to the microprocessor; Activating the microprocessor to generate a pager message corresponding to the synchronization data; And After the operation of decoding the demodulated data from the IF demodulator is completed, activating the decoder to deactivate the PLL frequency synthesizer and the IF demodulator; (9) performing the following detailed steps; Activating the decoder to send a channel-change request signal to the microprocessor; Activating the microprocessor to change its default channel-selection parameter to a new one; Activating the decoder to deactivate the PLL frequency synthesizer and the IF demodulator; Activating the microprocessor to input new channel-selection parameters into the PLL frequency synthesizer; Activating the decoder to activate the PLL frequency synthesizer and the IF demodulator, and further modifying the channel number stored in the channel register to a new number corresponding to the newly selected channel-selection parameter; And Full band-pacer comprising the step of returning to step (4). The method of claim 13, The decoder is designed according to ETS 300 133-4 and can support all 16 channels for pager communication, each of which is indicated by the following ID numbers: 0, 2, 4, 6, 8, A, C, E, F, D, B, 9, 7, 5, 3, 1, full band-pacer, characterized in that it is selected recursively to find one suitable for phaser communication.