KR19990033794A - Data input / output control device and method of variable bit rate buffer - Google Patents

Abstract

The present invention relates to an apparatus and method for controlling data input / output of a variable bit rate buffer. More particularly, the present invention provides a method of continuously controlling data input by precisely controlling a time point at which a data input operation to the buffer is performed after an overflow occurs in the variable bit rate buffer. An apparatus and method for controlling data input and output of a variable bit rate buffer that can be achieved.

The data input / output control of the variable bit rate buffer includes error correction of identification information of the last sector data read from the digital video disk when the overflow occurrence signal of the variable bit rate buffer is input, and frame synchronization detected from the sector data. The continuity of the signal and the sector data is determined, and when all three conditions are satisfied, the back track jump signal of the optical pickup apparatus is output.

Description

Data input / output control device and method of variable bit rate buffer

The present invention relates to an apparatus and method for controlling data input / output of a variable bit rate buffer. More particularly, the present invention provides a method of continuously controlling data input by precisely controlling a time point at which a data input operation to the buffer is performed after an overflow occurs in the variable bit rate buffer. An apparatus and method for controlling data input and output of a variable bit rate buffer that can be achieved.

In general, a video encoding method is classified into a coding method of a constant bit rate and a variable bit rate according to characteristics of an output bit stream. The fixed bit rate and variable bit rate encoding methods are determined by whether the amount of bits generated per unit time is fixed or variable.

Therefore, if the bit amount is variablely allocated and encoded in proportion to the complexity of the image, it is possible to maintain uniform picture quality over the entire playback section. Therefore, a compression method using a variable bit rate is adopted in a recording medium such as a DVD (Digital Video Disc). Doing. In this case, since the amount of original data is compressed at different bit rates according to the complexity of the video, the amount of data stored on the disk and the amount of data actually reproduced are not proportional.

On the other hand, in the case of decoding the data compressed at the variable bit rate, the data read from the disc is input into the DVD decoding apparatus, demodulated, and error corrected until the step of fixed bit rate. However, in the process of restoring the error-corrected data to the original image by the decoding processing unit, the variable bit rate buffer (Variable Bit Rate: hereinafter referred to as 'VBR') is used to interface the two processing methods. need.

Next, with reference to the accompanying drawings will be described in detail the reproduction operation of the data using the conventional variable bit rate buffer.

1 is a block diagram showing the configuration of a general optical disc reproducing apparatus. FIG. 2 is a circuit diagram illustrating data input / output control of the VBR buffer shown in FIG. 1.

The structure reads the data recorded on the DVD 1 storing data, the rotation drive motor 25 of the DVD 1, and the data recording surface of the DVD 1, converts the data into an electrical signal, and outputs the converted data. And an high frequency signal processor 29 for inputting an electrical signal output from the optical pickup device 3 and performing basic signal processing for reproduction.

And a servo unit 7 for controlling the driving of the motor 25 and controlling the tracking and focusing of the optical pickup device 3 by using the reproduction high frequency signal output from the high frequency signal processing unit 29, and the system; It includes a microprocessor unit (9) that governs the overall.

The reproduced high frequency signal output from the high frequency signal processor 29 is demodulated into 16 bits of data in the demodulation circuit 5, and after error correction is performed in the error correction circuit 11 in which error correction is performed in units of 16 sectors, Temporarily stored in the VBR buffer 27. The VBR buffer 27 stores data in FIFO (First-In First-Out) order and outputs the stored data. In other words, it is a memory based on the principle of outputting the first stored data for the first time.

In the above process, the data stored in the VBR buffer 27 is applied to each decoding circuit under the control of the microprocessor unit 9, the configuration of which is as follows. A video decoding circuit 13 for inputting, decoding, and outputting only video data from a playback digital signal output from the VBR buffer 27, and inputting only subtitle data from a playback digital signal under the control of the microprocessor unit 9; Graphics circuit 15 for processing and output, and audio decoding circuit 17 for inputting, decoding and outputting only an audio signal from a reproduction digital signal under the control of the microprocessor unit 9.

The video signal output from the video decoding circuit 13 is converted into an analog signal by the video digital / analog converter 19, and then converted into a broadcast signal according to the NTSC / PAL standard by the NTSC / PAL encoder 23 and output. do. The audio signal output from the audio decoding circuit 21 is also converted into an analog signal by the audio digital / analog converter 21 and then output.

Next, a description will be given of a conventional method for reproducing an optical disc according to the above configuration. When a user command is input by an external key signal input, the microprocessor unit 9 applies a control signal to each load device to control the system to the initial state of reproduction. The motor 25 is driven under the control of the servo unit 7. The driving of the motor 25 means that the DVD 1 is rotated. The optical pickup device 3 reads the recorded data while following the recording track of the rotated DVD 1, and the optical signal read out is converted into an electrical signal and input to the high frequency signal processor 29.

In this way, the signal read from the DVD 1 is input to the demodulation circuit 5 at a high speed of 26.26 Mbps, after the basic signal processing for reproducing the signal by the high frequency signal processor 29 is performed. After the signal is demodulated in the demodulation circuit 5, it is input to the VBR buffer 27 through the error correction circuit 11 or the like. At this time, the data transmission input to the VBR buffer 27 is 11.08Mbps.

On the other hand, since the VBR buffer 27 is output while the input is performed, the error correction circuit 11 receives the error-corrected data and simultaneously controls the variable bit rate signal under the control of the microprocessor unit 9. The data transmission to the video decoding circuit 13 is performed. At this time, the maximum data rate is 10.08Mbps.

That is, at this time, comparing the speed (UDR) at which data is inputted and written to the VBR buffer 27 and the output speed (VBR) at which data is written to the VBR buffer 27 are read, the input speed is always high, so that input / output is normally performed. If so, after a predetermined time elapses after the system operation, the VBR buffer 27 overflows. Therefore, in order to prevent the VBR buffer 27 from overflowing, the DVD player constantly monitors the data storage amount of the buffer, and when the data is filled to a certain level, the output is generated but the input is not controlled. .

The data input / output control process when overflow occurs of the VBR buffer 27 described above will be described in detail with reference to FIG.

First, signal processing according to the overflow control process of the VBR buffer 27 is performed between the demodulation circuit 5 shown in FIG. 1 and the error correction circuit 11 for error correction in units of 16 sectors.

The configuration includes an ID ECC 31 that determines whether or not the sector data is defective by error correcting identification information ID of the sector output from the demodulation circuit 5, and the error corrected by the ID ECC 31. The VBR processing unit 33 transmits the sector to the error correction circuit 11 and issues a back track jump command to the microprocessor unit 9 when an overflow occurs in the VBR buffer 27.

The following describes a data input / output control process when an overflow occurs in the VBR buffer 27 according to the above configuration.

Data read from the optical pickup device 3 is input to the ID-ECC 31 after predetermined signal processing by the high frequency signal processing unit 29 and the demodulation circuit 5. The ID-ECC 31 corrects and outputs the sector address. The sector data output after the error correction by the ID ECC 31 is input to the error correction circuit 11 and simultaneously input to the VBR processing section 33.

In this case, since the sector data output from the ID ECC 31 includes data of error correction of the identification information of the sector, the error corrected value ID-FLAG of the ID ECC 31 is determined to be normal. If so, the VBR processing section 33 takes a sector address from the input sector data and stores it in the address register. The next input sector data also replaces the currently input sector address with the address register when the error corrected value (ID-FLAG) appears normal.

On the other hand, after error correction of a sector address in the ID ECC 31, the sector data continuously input to the error correction circuit 11 is subjected to error correction of user data when the input sector becomes 16 sectors. The buffer 27 is output.

On the other hand, the microprocessor unit 9 monitors the data storage amount input to the VBR buffer 27 by decoding as described above, and when the data can no longer be stored in the VBR buffer 27, the VBR processing unit ( The orbit overflow generation signal is applied to 33).

The VBR processing unit 33, which inputs the overflow occurrence signal from the microprocessor unit 9, temporarily stores the address of the sector finally input to the address register of the VBR buffer 27, 9) issue a back track jump command to move the pickup device 3 one track back.

The microprocessor unit 9 which has received the back track jump command from the VBR processing section 33 outputs a control signal for causing the pickup device 3 to jump back track by one track. Therefore, the servo unit 7 makes the pickup device jump back track one track before, and the pickup device 3 reads back the already read data after the track jump.

When the process of reading back the data already read by the pickup device 3 is performed, the write operation is prohibited to the VBR buffer 27, and while the write operation is prohibited, the buffer 27 at the speed of VBR. Since only data is released, the amount of data accumulated in the VBR buffer 27 gradually decreases. In this way, the input to the VBR buffer 27 is resumed when the address after the last address just before the buffer is overflowed is input again, and data input / output is resumed at the speed of UDB-VBR again.

In more detail, the signal processing must continue to be performed whether the data read from the pickup device 3 is already read or new data, so that the data is transmitted to the high frequency signal processor 29 and the duplicated data. The identification information of the sector is again corrected by the ID ECC 31 through the inquiry path 5 and input to the VBR processing section 33.

The VBR processor 33 compares the sector address corrected by the ID ECC 31 with the sector stored in the address register of the VBR buffer 27 just before the overflow. If it is smaller than the address of the sector stored immediately before the overflow, the input sector is not taken, but if it is large, a control signal for resuming data transfer to the VBR buffer 27 is generated. This control signal is input to the microprocessor unit 9, and the microprocessor unit 9 controls the error correction circuit 11 and the VBR buffer 27 to start the data transmission to the VBR buffer 27. do.

Therefore, when data is stored in the VBR buffer 27 again, and the data can no longer be stored in the VBR buffer 27, the microprocessor unit 9 generates an overflow. Of course, the data output from the VBR buffer 27 is input to each decoding circuit under the control of the microprocessor unit 9, and is then displayed after being decoded into the original signal.

That is, the determination of the starting position at which the writing operation to the VBR buffer 27 starts again after the overflow of the conventional VBR buffer is started is made by the last sector address stored in the address register of the VBR buffer 27. The normal presence or absence of the sector data stored in the address register of the VBR buffer 27 is only performed by the result value (ID-FLAG) of error correction of the identification information of the sector in the ID ECC 31.

Therefore, when abnormal sector data is judged to be normal and finally stored in the VBR buffer 27 due to an error correction of the ID ECC 31, the next write operation to the VBR buffer 27 is the incorrect sector. Since the data is resumed after, the sector data before the VBR processing cannot be reproduced again after the VBR processing.

This is because the write operation of the VBR buffer 27 is resumed when a sector having an address larger than the address of the sector finally inputted to the VBR buffer 27 is input before the overflow occurs.

In addition, in the overflow control apparatus other than the conventional VBR buffer, even if the sector data finally stored in the buffer immediately before the overflow of the VBR buffer 27 is caused by a mechanical defect or a disk defect, the sector data may be out of the current playback track. There was no way to determine this. In other words, since the normality of sector data stored in the conventional VBR buffer is judged only by the result of error correction of the identification information of the sector data, the continuity of the input sector data after the error corrected value is determined to be normal There was no way to judge itself.

In such a case, the VBR buffer 27 is not continuously connected to the sector before the overflow occurs, and a large error occurs in the reproduction operation. In other words, since the sector data stored in the VBR buffer 27 is continuously transmitted to each decoding circuit for display until signal processing is performed, if the continuity is lost after the VBR processing in the VBR buffer 27, This is because playback is not performed.

Accordingly, an object of the present invention is to provide an apparatus and method for controlling data input / output of a variable bit rate buffer which can prevent errors in data input / output control of a VBR buffer due to a defect of a disk.

1 is a block diagram showing a configuration of a general optical disc reproducing apparatus;

2 is a circuit diagram for data input / output control of a conventional variable bit rate buffer;

3 is a circuit diagram for data input / output control of a variable bit rate buffer according to the present invention;

4 is a detailed circuit diagram of a VBR processing unit according to the present invention;

5 is an operation flowchart for data input / output control of a variable bit rate buffer according to the present invention;

* Explanation of symbols for main parts of the drawings

1: optical disc 3: optical pickup device

5, 50: demodulation circuit 7: Servo unit.

9, 61: microprocessor unit 11, 57: error correction circuit

13: video decoding circuit 15: graphics circuit

17: audio decoding circuit 19: digital to analog converter

23 NTSC / PAL Encoder 21 Digital / Analog Converter

25: motor 27, 59: VBR buffer

29: high frequency signal processor 31, 51: ID ECC

33, 53: VBR processor 55: Sync signal detector

The data input / output control device of the VBR buffer according to the present invention for achieving the above object is a memory for storing the input data having a variable bit rate, and an overflow signal for monitoring whether the overflow occurs by monitoring the amount of data in the memory Generating means, information detecting means for detecting whether the data information input to the memory is normal or a defect section, and means for generating a variable bit rate control signal by the output of the information detecting means and the overflow generating means. Characterized in that configured to include.

According to another aspect of the present invention, there is provided a method for controlling data input / output of a VBR buffer, the method comprising: temporarily storing input data having a variable bit rate, detecting an amount of the stored data to determine whether the overflow occurs; Determining whether input data is normal when overflow is determined; determining whether a sink of the input data is valid when overflow is determined; controlling data storage in the memory according to each determination result; It is made, including.

The data input / output control of the VBR buffer according to the present invention includes a frame synchronization signal included in the sector data, a sequential sequence of sector addresses, and an error-corrected value in ID-ECC under a determination condition according to whether data input to the VBR buffer is normal. It characterized by using.

In particular, the data input / output control condition of the VBR buffer according to the present invention is characterized in that it is applied when the optical pickup device backtracks jump immediately after an overflow occurs in the buffer.

Hereinafter, an apparatus and method for controlling data input / output of a VBR buffer according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram for explaining a data input / output control configuration of a VBR buffer according to the present invention, and the overall optical disk reproducing apparatus will be described with reference to FIG.

Describe the configuration.

The input / output control of the VBR buffer is performed between the demodulation circuit 50 and the error correction circuit 57 in which digital signal processing is performed. That is, the demodulated circuit is input to the ID ECC 51 by the demodulation circuit 50, and error correction of the ID information is performed by the ID ECC 51. The error corrected sectors are input to the VBR processing unit 53 and the error correction circuit 57.

In addition, the high frequency signal processing unit 29 includes a synchronization signal detection unit 55 for detecting and outputting a frame synchronization signal included in the sector from the reproduction high frequency signal subjected to the processing of the reproduction signal, and the synchronization signal detection unit 53. The frame synchronization signal output from the input signal is input to the VBR processor 53.

The VBR processing unit 53 inputs an overflow generation signal of the VBR buffer 59 from the microprocessor unit 61, and immediately after the overflow occurs, the optical pickup device 3 is transferred to the microprocessor unit 61. Generates a back track jump signal for moving to the previous track.

The sector data input to the error correction circuit 57 is stored in the VBR buffer 59 after error correction of user data in units of 16 sectors by the error correction circuit 57. The configuration thereafter is the same as in the prior art.

The detailed configuration of the VBR processor 53 is shown in FIG.

As shown, in the first logical multiplication device 65, the error correction value ID-FLAG in the ID ECC 51 and the frame synchronization signal GFS detected by the synchronization signal detection unit 55 are shown. And a value obtained by comparing the sector address currently input by the address sequencing comparison unit 63 with the address of the stored sector and comparing the continuity of the input sectors as basic information for the first determination. In other words, the address sequential comparison section 33 continues the operation of taking the sector address from the input sector data and replacing it.

When the second logical AND element 67 inputs the overflow occurrence signal of the VBR buffer 59 from the microprocessor unit 61, all of the conditions of the first logical AND element 65 are satisfied. A back track jump generation signal is output to the controller.

Next, the data input / output control configuration of the VBR buffer according to the above configuration will be described in detail.

5 is a flowchart illustrating the data input / output control of the VBR buffer according to the present invention.

Before describing the data input / output control process of the VBR buffer, the data structure of the DVD will be briefly described. The data of the DVD has a minimum data unit that can be accessed by adding IDs in predetermined sector units. In general, a one-sector structure consists of 2048 bytes of user data, 12 bytes of ID and IEC sector identification information, and 4 bytes of EDC, including 2064 bytes of sector data. These sectors become a recording sector other than 2366 bytes in total after ECC encoding for PI error correction and PO error correction, which become recording sectors for actual recording by ECC. After the modulation, the recording sectors have a synchronization signal for use as a control signal of the spindle motor rotation control. A total of 26 synchronization signals are attached at regular intervals.

Therefore, 26 synchronization signals are included in every 91 byte interval in one recording sector, and a 91-byte unit including the synchronization signal is called a synchronization frame, and a total of 26 frames exist in one sector. Therefore, if there is a defect or the like on the disk and the sector data becomes inaccurate, the detection operation of the sync frame included in the head of each frame becomes incorrect.

Next, in the description of the operation of the present invention, the optical signal read from the optical pickup device 3 which tracks the recording track of the rotating DVD 1 is converted into an electrical signal and input to the high frequency signal processing unit 29. The signal input to the high frequency signal processor 29 is input to the demodulation circuit 50 at a high speed after basic signal processing for reproduction is performed. After the signal is demodulated by the demodulation circuit 50, it is input to the VBR buffer 59 through the error correction circuit 57 or the like.

Since the VBR buffer 59 is output while the input is being performed, the variable bit rate signal processing is performed under the control of the microprocessor unit 61 while inputting error-corrected data from the error correction circuit 57. Data transmission to the video decoding circuit 13 is made.

On the other hand, comparing the speed (UDR) at which data is input to the VBR buffer (59) and the output speed (VBR) at which the data is written to the VBR buffer (59) is read, the input speed is always high. After the predetermined time elapses, the VBR buffer 59 overflows.

Therefore, the microprocessor unit 61 constantly monitors the state of the data storage amount of the buffer to prevent the overflow of the VBR buffer 59. However, when the data is filled to a certain level, the microprocessor unit 61 outputs the output but controls the input. Will be

That is, the overflow occurrence signal generated in the microprocessor unit 61 is input to the VBR processing unit 53 according to the amount of data stored in the buffer 59 (step 101 in FIG. 5), and the VBR processing unit 53 transmits the ID. The address continuity of the sectors inputted from the ECC 51 and the presence or absence of sector data inaccuracy are judged, and when the sector address stored in the address sequential comparison section 63 is in a steady state, a back track jump signal is output.

In more detail, first, the VBR processing unit 53 inputs a value for determining whether there is an error correction of the sector ID from the output value of the ID ECC 51. When the error correction value ID-FLAG of the ID ECC 51 is judged to be normal (step 103 of FIG. 5), the sector address is taken from the sector data input from the ID ECC 51, and the sector address is determined. It is determined whether the value 1 is increased from the sector address input in the previous step (step 105 of FIG. 5). That is, the continuity of the input sector is determined.

Next, the synchronization signal detection unit 55 inputs the reproduction high frequency signal output from the high frequency signal processing unit 29 to properly detect each synchronization signal of 26 frames included in one sector, and the position of the detected synchronization signal. Is judged to be correct, and inputs the signal GFS according to this determination (step 107 of FIG. 5).

In the above, when the 103, 105, and 107 steps are all satisfied, the second logic outputs the high signal from the first AND product 65 and simultaneously inputs the overflow generation signal from the microprocessor unit 9. In the product element 67, a back track jump signal is generated (step 109 of FIG. 5).

Then, a control signal is generated for performing the back track jump to the optical pickup device 3 one track before, and the sector data read from the optical pickup device 3 after the track jump is the sector immediately before the overflow occurrence. The VBR buffer 59 continues only the output operation until data is input.

The following process is the same as in the related art, but in brief, the data read out from the optical pickup device 3 has an error of identification information of the sector in the ID ECC 31 through the high frequency signal processing unit 29 and the demodulation circuit 5 again. The correction is made and input to the VBR processing section 33.

The VBR processor 33 compares the sector stored in the address register of the VBR buffer 27 immediately before the sector address overflow corrected by the ID ECC 31. If it is smaller than the address of the sector stored immediately before the overflow, the input sector is not taken, but if it is large, a control signal for resuming data transfer to the VBR buffer 27 is generated. This control signal is input to the microprocessor unit 9, and the microprocessor unit 9 controls the error correction circuit 11 and the VBR buffer 27 to start the data transmission to the VBR buffer 27. do.

Therefore, when data is stored in the VBR buffer 27 again, and the data can no longer be stored in the VBR buffer 27, the microprocessor unit 9 generates an overflow.

Of course, regardless of whether or not an overflow occurs in the VBR buffer 59, data continuously output is inputted to each decoding circuit, decoded into an original signal, and then output to a display.

As described above, the apparatus and method for controlling data input / output of the variable bit rate buffer according to the present invention suppresses the back track jump operation of the optical pickup apparatus in the defect period of the disc when an overflow occurs in the variable bit rate buffer. . To this end, in the present invention, when the error correction value of the sector ID, the sector address continuity, and the detection condition of the frame synchronization signal included in the sector are satisfied, the back track jump operation is performed so that the variable bit is performed. There is an advantage that a great effect can be obtained for continuous reproduction of data in a DVD in which data transfer at a rate is performed.

Claims (6)

A memory for storing data input at a variable bit rate, an overflow signal generating means for monitoring the amount of data in the memory to indicate whether an overflow occurs, and whether the data information input to the memory is normal or in a defect interval. And information detecting means for detecting a signal, and means for generating a variable bit rate control signal by the outputs of the information detecting means and the overflow generating means. The variable bit rate buffer data input / output control according to claim 1, wherein the information detecting means detects an error correction result signal of sector identification information, a signal indicating whether a frame synchronization signal is valid, a continuity signal of a sector address, and the like. Device. 2. The apparatus of claim 1, further comprising an optical pickup apparatus that backtraces the signal by the variable bit rate control signal. Temporarily storing the input data having a variable bit rate, determining whether the amount of stored data is an overflow, determining whether the input data is normal if the overflow is determined, and the overflow And determining whether the sink of the input data is valid, and controlling the storage of the data in the memory according to each determination result. 5. The method of claim 4, wherein the detection of the defect section of the data determines whether the sync signal of the input data is valid. 6. The variable bit rate buffer data input / output control according to claim 4 or 5, wherein the determining of normality of the data is performed by an error correction result of identification information and a sector address continuity with previous data. Way.