KR19990032769A - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a capacitor of a semiconductor memory device having hemispherical grain silicon and a manufacturing method thereof. Insulating material layers are formed on the semiconductor substrate on which the access transistor is formed, and contact holes are formed in the insulating material layers. The doped first polycrystalline silicon and the undoped first polycrystalline silicon are formed in the contact hole and the material layer, and then patterned at the same time to form a storage electrode. Subsequently, spacers are formed of undoped third polycrystalline silicon on the storage electrode, and then HSG silicon is grown on the surfaces of the second polycrystalline silicon and the third polycrystalline silicon. By growing the HSG silicon, the area of the capacitor is further increased, and the ratio of Cmin / Cmax can be increased by increasing the internal doping concentration of the HSG silicon.

Description

Capacitor Manufacturing Method of Semiconductor Memory Device

The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device using hemi-spherical grain (hereinafter referred to as "HSG") silicon.

Semiconductor memory devices can be classified into volatile random access memory (RAM) products and nonvolatile read only memory (ROM) products. Among the RAM products, in particular, DRAM (DRAM) is a unit cell. A memory device for storing data in a capacitor of C, wherein the capacitance of the capacitor, that is, the capacitance, refers to a storage capacity of the data. Accordingly, when the capacitance is insufficient, an error of incorrect reading may occur when the data is to be stored and read again. In order to prevent such data errors, a so-called refresh operation is performed to restore the data after a certain time. Since the refresh operation is affected by the capacitance, increasing the capacitance may be one of the main methods for increasing the refresh characteristics. However, as semiconductor memory devices have been highly integrated in recent years, the area of unit cells per chip is reduced, so that the area for forming a capacitor is also reduced. Therefore, it is very important in the art to increase the capacitance per unit area as the semiconductor device is highly integrated.

The capacitance is proportional to the cross-sectional area in which the storage electrode serving as the lower electrode and the plate electrode serving as the upper electrode are in contact with each other, and inversely proportional to the distance between the two electrodes. Therefore, further increasing the surface area of the storage electrode within the same limited area is one of the most important factors that can increase the capacitance. Accordingly, in this field, in order to secure more sufficient capacitance in the same area, a capacitor over bit line (hereinafter referred to as COB) process has begun to be used, and furthermore, a cylinder type, a box type, The manufacture of stacked capacitors having a three-dimensional structure such as a fin type has been achieved. However, the capacitors manufactured by improving the structure of the storage electrode have a problem in that a manufacturing process is complicated and time, cost, etc. are increased, and further, they face a limitation of a design rule due to high integration.

In order to solve the above problems, various methods for increasing the capacitance using the physical properties of materials used for the storage electrodes are being researched away from improving the structure of the storage electrodes. As one of them, a method of increasing capacitance using hemispherical silicon (hereinafter referred to as HSG) silicon has been introduced. The method includes increasing the surface area of the storage electrode by growing HSG silicon on the surface of the storage electrode using Low Pressure Chemical Vapor Deposition (LPCVD) to form irregularities on the surface of the storage electrode. to be. Briefly, a method of growing HSG silicon is described. Amorphous silicon is deposited on a semiconductor substrate, and then heated to a temperature of about 550 ° C. under a pressure of about 1 torr, and the amorphous silicon layer is convex. That is, HSG silicon. The HSG silicon has an increased surface area of about two to three times that of the flat surface before being heated to form a storage electrode having a larger surface area. In addition, it is possible to accumulate about 1.8 times as much charge as a capacitor without using conventional HSG silicon. In addition, in recent years, HSG silicon is formed by the LPCVD method, the native oxide is removed, and annealing in vacuum is performed to form HSG silicon on any surface. . However, in the growth process of HSG silicon, an N-type impurity, such as phosphorus, present in the conductive material constituting the storage electrode becomes very low in the HSG silicon. This is because the HSG silicon growth process undergoes a kind of recrystallization growth process. As such, when the concentration of phosphorus in the HSG silicon is low, a problem arises in that the capacitance varies depending on the direction in which the bias is applied to the capacitor.

In general, the upper and lower electrodes of the capacitor are composed of a plate electrode and a storage electrode, respectively, and typically, the storage electrode uses polycrystalline silicon containing an en-type impurity, and is typically polycrystalline silicon doped between 1E20 and 1E23 / Cm ^3. Use And HSG silicon is formed thereon, which is typically doped less than 1/100 to 1/1000 less than the polycrystalline silicon forming the storage electrode. As a result, electrons or holes are collected on the surface of the storage electrode by the electric field generated by the potential potential difference between the two nodes when storing data in the capacitor. However, as mentioned above, when the concentration of the en-type impurity in the HSG silicon is low, the depletion layer is formed by canceling each other with the electrons collected on the surface of the storage electrode by the electric field. This depletion layer acts as one parasitic capacitance. If the parasitic capacitance is referred to as Cd and the capacitance generated by the dielectric of the capacitor is referred to as Cc, a relationship of Cd <<Cc is established. At this time, the plate electrode, the parasitic capacitance by the depletion layer, the capacitance by the dielectric itself, and the storage electrode form a series structure, so that the total capacitance Ct becomes (Cc * Cd) / (Cc + Cd). Considering the relationship of Cd <<Cc, it can be seen that the relationship of Ct <Cc is established and the ratio of the minimum capacitance and the maximum capacitance, that is, the ratio of Cmin / Cmax, becomes small.

In DRAM products, the meaning of minimum capacitance, Cmin, is very important because DRAM uses a potential level of "HIGH" state when storing data "1". Using the "high" level means that the "high" potential level is applied to the storage electrode, which means that the potential of the storage electrode is higher than that of the plate electrode. Therefore, as described above, when the n-type doping concentration in the HSG silicon is lowered, a smaller amount of charge is charged when the data "1" is to be stored than when the data "0" is stored. This asymmetric capacitance degrades the performance of the entire semiconductor chip, for example, causing a problem in that the refresh margin of data "1" is reduced. Therefore, in order to solve the above problem, a method of increasing the doping concentration of HSG silicon by increasing the doping concentration of the polycrystalline silicon layer constituting the storage electrode has been proposed. However, as shown in FIG. 1, the doping concentration of the polycrystalline silicon layer constituting the storage electrode is inversely related to the size of the HSG silicon. In other words, when the concentration of polycrystalline silicon is increased, so-called bald defects occur, which hinder the growth of HSG silicon, and as a result, the desired surface area of the storage electrode cannot be obtained.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device that can solve the above-mentioned conventional problems.

It is still another object of the present invention to provide a method for manufacturing a capacitor of a semiconductor memory device which can further increase the surface area by using HSG silicon.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device, which can increase the ratio of Cmin / Cmax by preventing the doping concentration of HSG silicon from lowering.

1 is a graph showing the relationship between the impurity doping concentration and the HSG silicon size of the polycrystalline silicon layer constituting the storage electrode.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a semiconductor memory device according to an embodiment of the present invention.

In order to achieve the above object, the present invention comprises the steps of forming a planarization layer, an etch stop layer and a material layer on top of the semiconductor substrate; Forming contact holes in the planarization layer, an etch stop layer and a material layer; Forming a highly doped first polycrystalline silicon layer and an undoped second polycrystalline silicon layer on the contact hole-formed semiconductor substrate; Simultaneously patterning the doped first polycrystalline silicon layer and the undoped second polycrystalline silicon layer to form storage electrodes that are lower electrodes of the capacitor; Forming an undoped third layer of polycrystalline silicon on the resulting formation of said storage electrodes; Etching back the third polycrystalline silicon layer to form spacers on sidewalls of the storage electrode; Growing hemispherical grain (HSG) silicon on the surface of the undoped second / third polycrystalline silicon layer; A method of fabricating a capacitor in a semiconductor memory device, the method comprising performing an undercut process of wet etching the material layer.

Preferably, the first polycrystalline silicon layer is formed thinner than the conventional polycrystalline silicon layer for storage electrodes and forms a second polycrystalline silicon thereon to form a multilayer structure.

Preferably, the HSG silicon is partially grown only in the second polycrystalline silicon layer and the third polycrystalline silicon layer.

Subsequently, after the undercut process, the method may further include forming a plate electrode, which functions as an upper electrode of the dielectric layer and the capacitor, on the storage electrode to complete the capacitor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the present invention.

2A illustrates a step of forming a transistor and a contact hole 114 in a semiconductor substrate.

The transistor includes a gate insulating layer 104 and an active region defined by local oxide (LOCal Oxide Silicon), which is a conventional method of fabricating a device isolation layer, or device isolation layers 102 formed by a more advanced PBL process. The source and drain regions (not shown) are formed by performing an ion implantation process on the semiconductor substrate using the gate electrode 106 and the gate electrode 106 as self-aligned masks. The gate electrode 106 functions as a word line and a bit line (not shown) is formed in the drain region. In addition, a storage electrode, which is a lower electrode of the capacitor, is formed in the source region in a subsequent process. A planarization layer 108, an etch stop layer 110, and an undercut material layer 112 are formed in order to planarize the semiconductor substrate 100 in which the step is generated in the process of forming the transistor. Preferably, the etch stop layer 110 and the material layer 112 are formed of materials having an excellent etching selectivity with respect to wet etching, for example, a silicon nitride layer and a silicon oxide layer. Subsequently, the material layer 112, the etch stop layer 110, and the planarization layer 108 are simultaneously dry-etched to form a contact hole 114 exposing the source region of the transistor.

2B illustrates a step of forming a pattern of the storage electrode.

The first polycrystalline silicon layer 116 doped with impurities such as phosphorus (Phosphorus) and the second polycrystalline silicon layer 118 not doped with impurities are disposed on the contact hole 114 and the material layer 112. Form the front. Preferably, the impurity doping concentration of the first polycrystalline silicon layer 116 is doped to reach about 1E22 atom / cm ³ to reach saturation. Also preferably, the first polycrystalline silicon layer 116 is formed to a thickness of about 4000 kPa to 7000 kPa, which is thinner than the conventional thickness. Subsequently, a photolithography process is performed on the first polycrystalline silicon layer 116 and the second polycrystalline silicon layer 118 formed on the entire surface to form storage electrodes in contact with the source region of the transistor.

2C illustrates the steps of forming a spacer 120 and a seed 122.

A third polycrystalline silicon layer that is not doped with impurities is formed on the storage electrodes and the material layer 112. Subsequently, a front etch back is performed on the third polycrystalline silicon layer to separate each storage electrode. As a result of the etch back, spacers 120 are formed on both sidewalls of the storage electrode. Subsequently, a seed 122 for growing HSG silicon is formed on the entire surface of the resultant.

2D illustrates the steps of growing HSG silicon.

The HSG silicon is grown on the surface of the second polycrystalline silicon layer 118, the spacer 120 formed of the third polycrystalline silicon layer, and the surface of the material layer 112. In this case, the seed 122 is preferentially grown in the second polycrystalline silicon layer 118 and the spacer 120 than in the same oxide layer as the material layer 112. In the conventional HSG silicon growth step, as the impurity doping concentration of the polycrystalline silicon layer for the storage electrode increases, HSG silicon does not grow, that is, a defect is generated, and thus the doping concentration of the polycrystalline silicon for the storage electrode is not sufficiently increased. It was. However, in the present invention, the first polycrystalline silicon 116 for the storage electrode is sufficiently dedoped and the Bald Defect is formed by additionally forming second and third polycrystalline silicon layers 118 and 120 that are lightly doped on the top and sides thereof. Can be prevented. Subsequently, the HSG silicon is grown and then treated with POCl ₃ (Phosphorus Oxide Cl ₃ ) to diffuse phosphorus into the HSG silicon to form the doped HSG silicon 124. Then, annealing is performed at a temperature of about 600 ° C. to equalize the concentration gradient of phosphorus diffused in the HSG silicon 124. This completes the storage electrode 126 in which the doping concentration of phosphorus is uniform and irregularities are formed on the surface by HSG silicon.

2E illustrates the steps of completing the capacitor.

After the storage electrode 126 is formed, an undercut process of wet etching the material layer 112 is performed. Typically, the bottom area of the storage electrode exposed due to the undercut process is used as an effective area that can increase capacitance. Subsequently, the dielectric layer 128 of the capacitor including the oxide layer and the like, and the plate electrode 130 serving as the upper electrode of the capacitor are sequentially formed on the entire surface of the resultant in which the storage electrode is formed to complete the capacitor for the semiconductor memory device.

As described above, the present invention previously forms a sufficiently doped first polycrystalline silicon layer, and further forms an undoped second polycrystalline silicon layer and a third polycrystalline silicon layer on top and sidewalls thereof. HSG silicon is grown in the undoped second polycrystalline silicon and third polycrystalline silicon layers so that no bald defects occur. POCl ₃ treatment also diffuses a high concentration of phosphorus into the HSG silicon and then anneals to uniformize the phosphorus concentration of the storage electrode. HSG silicon can be used to increase the area of the capacitor. In addition, the ratio of Cmin / Cmax may be increased by increasing the doping concentration in the HSG silicon.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art to various modifications and changes to the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (9)

Forming a planarization layer, an etch stop layer, and a material layer on the semiconductor substrate on which the access transistor is formed; Forming a contact hole in the planarization layer, an etch stop layer, and a material layer; Forming a highly doped first polycrystalline silicon layer and an undoped second polycrystalline silicon layer on the contact hole-formed semiconductor substrate; Simultaneously patterning the doped first polycrystalline silicon layer and the undoped second polycrystalline silicon layer to form storage electrodes that are lower electrodes of the capacitor; Forming an undoped third layer of polycrystalline silicon on the resulting formation of said storage electrodes; Etching back the third polycrystalline silicon layer to form spacers on sidewalls of the storage electrode; Growing hemispherical grain (HSG) silicon on the surfaces of the undoped second polycrystalline silicon and third polycrystalline silicon layers; And an undercut process step of wet etching the material layer. 2. The method of claim 1, further comprising forming a plate electrode on the resultant substrate after the undercut process, which functions as a dielectric layer of the capacitor and a lower electrode of the capacitor, thereby completing the capacitor. The method of claim 1, wherein the hemispherical grain silicon is selectively grown only on the surfaces of the second polycrystalline silicon and the third polycrystalline silicon. The method of claim 1, wherein the first polycrystalline silicon is doped until the concentration of impurities reaches a saturation state. The method of claim 1, wherein the hemispherical silicon is grown due to seeds formed in the second polycrystalline silicon layer and the third polycrystalline silicon layer. The method of claim 1, wherein the seed formed in the material layer is removed together with the material layer by an undercut process. The method of claim 1, wherein the material layer and the etch stop layer are formed of a material having an excellent etching selectivity with respect to any wet etching. The method of claim 1, wherein the material layer and the etch stop layer are formed of a silicon nitride layer and a silicon oxide layer, respectively. The method of claim 1, wherein the hemispherical silicon is doped by a POCl ₃ process.