KR19990032085A - Lateral polarized ferroelectric random access memory, manufacturing method and driving method thereof - Google Patents

Abstract

The present invention relates to a lateral polarized ferroelectric random access memory (lateral FRAM) using the principle of polarizing a ferroelectric laterally, a method of manufacturing the same, and a driving method thereof. The lateral polarization ferroelectric random access memory according to the present invention forms a ferroelectric capacitor such as bismuthitanate having a small amount of polarization up and down but a large amount of polarization from side to side depending on the deposition characteristics of the ferroelectric, or the side polarization becomes larger than the vertical polarization. By forming a ferroelectric capacitor manufactured so as to form an impurity doped layer thin film of TFT as an electrode material of the ferroelectric capacitor, adhesion between the electrode of the ferroelectric capacitor and the TFT is ensured, and the size of the TFT is increased to the size of the upper electrode of the ferroelectric capacitor. It is not limited accordingly, and the manufacturing process is simple because the structure is simple. In addition, in manufacturing the memo cell array, adjacent memory cells are formed to be symmetrical with each other, but a common bit line, a common plate pad contact hole, and a common plate pad are formed to increase the degree of memory integration.

Description

Lateral polarized ferroelectric random access memory, manufacturing method and driving method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral thin film transistor ferroelectric random access memory, and more particularly, to a lateral polarized ferroelectric random access memory (lateral FRAM) using the principle of lateral polarization of a ferroelectric, and a manufacturing method and a driving method thereof.

In the conventional FRAM structure, as shown in FIG. 1, the CMOS transistors 10, 14b, 15, 16, and 17 and the ferroelectric capacitors 11, 12, and 13 are connected to the electrode 18b to form a single cell. It forms a cell. That is, an insulating layer 14b is formed on the channel 19 of the silicon substrate 10 having the drain 15 and the source 17 formed by impurity doping, and the gate 16 is formed in the insulating layer 14b. The formed CMOS transistor and the lower electrode 11, the ferroelectric layer 12, and the upper electrode 13 have a structure in which the ferroelectric capacitors 11, 12, 13, which are sequentially stacked, are connected. This is called a 1T-1C structure, where 1T-1C becomes one cell. Here, an insulating layer is opened on the drain 15 and the source 17 of the CMOS transistor to form a bit line 18a and a connection electrode 18b. A ferroelectric capacitor is fabricated on the CMOS substrate 10 and is surrounded by a periphery. Electrode 18c is formed on the upper portion of the transistor through an opening of an insulating layer.

However, the thin film transistor ferroelectric random access memory of the 1T-1C structure is connected to each other through the connecting electrode through the opening, not the structure in which the lower electrode of the ferroelectric capacitor and the source of the thin film transistor are directly connected. Therefore, the manufacturing process is relatively complicated, and a large cell space is required to form a memory cell, so that the degree of integration of the device is relatively low.

In addition, when the TFT is deposited on the upper electrode of the ferroelectric capacitor in order to increase the degree of integration, the adhesion between the TFTs as the upper electrode must be ensured, and the TFT must be deposited on the upper electrode, so that the TFT size is limited to the size of the upper electrode.

The present invention has been developed to solve the above problems, and the polarization direction of the ferroelectric capacitor is lateral, and the manufacturing process is simplified by directly contacting the ferroelectric electrode and the terminals of the thin film transistor, thereby limiting the size of the upper electrode of the thin film transistor. It is an object of the present invention to provide a lateral polarized ferroelectric random access memory capable of high-density integration of a device, and a manufacturing method and a driving method thereof.

1 is a vertical sectional view of a conventional ferroelectric random access memory;

2 is a vertical cross-sectional view showing a unit cell structure of a lateral polarized ferroelectric random access memory according to the present invention;

3 is a vertical cross-sectional view showing the cells of the lateral polarized ferroelectric random access memory of FIG. 2 in an array form;

4A to 4G illustrate a method of manufacturing the lateral polarized ferroelectric random access memory of FIG. 2;

5A to 5D are diagrams for describing an operation of the lateral polarized ferroelectric random access memory of FIG. 2.

5A and 5B illustrate a "write" operation;

5C and 5D illustrate a "read" operation;

6A to 6D show equivalent circuit diagrams in the “write” and “read” operations of FIGS. 5A to 5D, respectively.

And FIG. 7 is an equivalent circuit diagram of the entire lateral polarization ferroelectric random access memory of FIG.

<Description of Symbols for Main Parts of Drawings>

10. Silicon substrate 11. Bottom electrode

12. Ferroelectric layer 13. Upper electrode

14b. Insulation layer 15. Source

16.gate 17.drain

18a. Bitline 18b. Connecting electrode

18c. Plate line 19. Channel

100. Plate pad 200. Ferroelectric layer

200a. Ridge

300a. n-channel 300b. n ⁺ -doped impurity doped layer (drain)

300c. n ⁺ -doped impurity doped layer (source) 300d. electrode

400. Insulation layer 500. Gate (Wordline)

600.Bitline 700.Sensor Amplifier

1000. Ferroelectric Capacitor 2000. Select Thin Film Transistor

In order to achieve the above object, in the lateral polarization ferroelectric random access memory according to the present invention, a ferroelectric capacitor having a lateral polarization and a selection transistor for selecting the ferroelectric capacitor are formed to be directly connected to the ferroelectric capacitor, An electrode of the ferroelectric capacitor to be connected and an electrode of the selection transistor are formed of an integral semiconductor impurity layer.

In the present invention, the ferroelectric material of the ferroelectric capacitor is a capacitor manufactured by using a ferroelectric material having a greater lateral polarization than the vertical polarization such as bismuthitanate or a greater lateral polarization than the vertical polarization, wherein the ferroelectric capacitor is Board; A plate pad formed on the substrate; The ferroelectric layer formed on the plate pad and the substrate to have a stepped ridge at a position corresponding to the plate pad; And a first conductive semiconductor impurity doping layer for an electrode formed on a ridge side of the ferroelectric layer, wherein the selection transistor comprises a second conductive property for a conducting channel formed between the first conductive impurity doping layers extending from one side of the ridge. An impurity doped layer; An insulating layer formed on the first conductive impurity doping layer and the second conductive impurity doping layer; And a gate formed at a position corresponding to the second conductive impurity doping layer on the insulating layer.

In addition, another lateral polarized ferroelectric random access memory according to the present invention for achieving the above object, the substrate; Plate pads formed in a stripe shape on the substrate; A ferroelectric layer formed on the plate pad and the substrate to have stepped ridges at positions corresponding to the plate pads; The first electrode region connected to one side of the ridge is formed in a stripe shape on the ferroelectric layer except the upper portion of the ridge so as to be connected to both sides of the ridges of the ferroelectric layer. A first conductive impurity doping layer for an electrode formed to be connected to the plate pads through holes; Second conductive impurity doping layers for conduction channels formed between the first conductive impurity doping layers connected to the other sides of the ridges; An insulating layer formed on the ferroelectric layer, the first conductive impurity doped layers and the second conductive impurity doped layers; Gate lines in the insulating layer formed on a stripe in a direction crossing the plate pads to be spaced apart from the second conductive impurity doped layer so as to correspond to the second conductive impurity doped layers; And a stripe shape in a direction parallel to the plate pads on the insulating layer, wherein the second electrode region and the third electrode region of the first conductive impurity doped layer are respectively connected to the second conductive impurity doped layer. And bit lines formed to be connected through the holes formed in the third electrode region and the insulating layer, not the second electrode region connected to the other side of the ridge.

In the present invention, the ferroelectric layer is made of a material having a greater lateral polarization than a vertical polarization, such as bismuthitanate, or the ridge of the ferroelectric layer is manufactured so that the lateral polarization is larger than the vertical polarization, two adjacent memories The cells are formed in a symmetrical structure with each other so that the connection holes between the first conductive impurity doping layer and the plate pad, the plate pad, and the bit line are commonly used in the two memory cells, respectively, in one common connection hole and common plate pad. And a common bit line.

In addition, in order to achieve the above object, a method of manufacturing a lateral polarized ferroelectric random access memory according to the present invention, (A) forming a ferroelectric layer by depositing a ferroelectric material on a substrate on which plate pads are formed; (B) selectively etching the ferroelectric layer to form holes for exposing the plate pads and a ridge having a predetermined width on the ferroelectric layer; (C) forming an impurity doping layer doped with a first conductive impurity and a second conductive impurity on the ferroelectric layer, respectively; (D) selectively etching the first conductive impurity doping layer deposited on the ferroelectric layer ridge to form electrodes on both sides of the ferroelectric capacitor; (E) depositing an insulating material to a predetermined thickness on the exposed ridge and the impurity doped layer, and then forming a gate line on a corresponding position on the second conductive impurity doped layer; (F) depositing an insulating material on the gate line and the insulating material layer to form an insulating layer; And (g) forming holes for exposing the one electrode region in an insulating layer on one electrode region of the selection transistor that is not connected to the ridge side of the electrode regions of the first conductive impurity doping layer, and then depositing a conductive material. To form a bit line on the stripe in a direction parallel to the plate pads.

In the present invention, the first conductive impurity doping layer and the second conductive impurity doping layer are n ⁺ -doping layer and p-doping layer, respectively, or p ⁺ -doping layer and n-doping layer, respectively, and the ferroelectric layer It is desirable to control the capacitance of the ferroelectric capacitor by adjusting the width and height of the ridge.

In addition, in order to achieve the above object, a method of driving a lateral polarized ferroelectric random access memory according to the present invention, a substrate; Plate pads formed on the substrate in a stripe shape; A ferroelectric layer formed on the plate pad and the substrate to have stepped ridges at positions corresponding to the plate pads; The first electrode region connected to one side of the ridge is formed in a stripe shape on the ferroelectric layer except the upper portion of the ridge so as to be connected to both sides of the ridges of the ferroelectric layer. A first conductive impurity doping layer for an electrode formed to be connected to the plate pads through holes; Second conductive impurity doping layers for conduction channels formed between the first conductive impurity doping layers connected to the other sides of the ridges; An insulating layer formed on the ferroelectric layer, the first conductive impurity doped layers and the second conductive impurity doped layers; Gate lines in the insulating layer formed on a stripe in a direction crossing the plate pads to be spaced apart from the second conductive impurity doped layer so as to correspond to the second conductive impurity doped layers; And a stripe shape in a direction parallel to the plate pads on the insulating layer, wherein the second electrode region and the third electrode region of the first conductive impurity doped layer are respectively connected to the second conductive impurity doped layer. And bit lines formed to be connected through the holes formed in the third electrode region and the insulating layer instead of the second electrode region connected to the other side of the ridge. And a voltage signal is sent to the gate line to select a ferroelectric capacitor comprising a ridge of the ferroelectric layer and a first electrode region and a second electrode region of the first conductive impurity doping layer, and then between the bit line and the plate pad. Polarizing and recording the ferroelectric capacitor with an applied voltage; And selecting a ferroelectric capacitor by sending a voltage signal to the gate line, and then applying a voltage signal to the plate pad to sense and read a current flowing through the ferroelectric capacitor with a sense amplifier.

In the present invention, the writing step includes: writing “0” by polarizing the ferroelectric capacitor with a constant voltage applied to the bit line in the case of an n-channel transistor; And polarizing the ferroelectric capacitor at a constant voltage on the plate pad, and writing "1" to the plate pad. The reading may include reversing the polarization state of the ferroelectric capacitor when reading the "0". When current flows and the sensor amplifier senses the current and reads the value recorded as "1", it is desirable to sense a different current than when recorded as "0" while maintaining the polarization state of the ferroelectric capacitor. Do.

Also, in the present invention, the writing may include: writing “1” by polarizing the ferroelectric capacitor with a negative voltage applied to the bit line in the case of a p-channel transistor; And polarizing the ferroelectric capacitor with a negative voltage on the plate pad, and writing "0". The reading step includes reversing the polarization state of the ferroelectric capacitor when reading the "1". When the current flows while the sensor amplifier senses the current and reads the value recorded as "0", it may sense different current than when the polarization state of the ferroelectric capacitor is polarized to "1" while maintaining the polarization state of the ferroelectric capacitor. desirable.

Hereinafter, a lateral polarized ferroelectric random access memory according to the present invention, a manufacturing method thereof, and a driving method thereof will be described in detail with reference to the accompanying drawings.

2 is a vertical sectional view showing a schematic structure of a lateral polarized ferroelectric random access memory according to the present invention. As shown, the lateral polarization ferroelectric random access memory according to the present invention includes a ferroelectric capacitor laterally polarized on a substrate (not shown) and a thin film transistor for ferroelectric capacitor selection formed to be directly connected to the ferroelectric capacitor. It is characterized by. This will be described in detail as follows.

First, a plate pad 100 on a stripe having a function as a lower electrode of a ferroelectric capacitor is formed on a substrate (not shown). The ferroelectric layer 200 is deposited on the substrate on which the plate pad 100 is formed. In this case, since the ferroelectric layer 200 is polarized laterally, the ferroelectric layer 200 is formed to have a stepped ridge 200a. Ferroelectric materials include materials such as bismuth titanate. When this material is deposited in a thin film, the amount of polarization is weak in the up and down direction, but the polarization amount in the right and left is large, and thus the material is suitable for causing lateral polarization. In addition, since any ferroelectric material may be manufactured so that the lateral polarization is larger than the vertical polarization, the ridge 200a of the ferroelectric layer 200 is formed to cause lateral polarization of the thus-deposited ferroelectric film. A conductive material is deposited on the ferroelectric layer so that the electrodes 300c and 300d are in contact with both sides of the ridge, respectively, to form a ferroelectric capacitor structure. The conductive material used here is n ⁺ -doped material (or p ⁺ -doped material). That is, the electrodes 300c and 300d are formed of an impurity doping layer doped with n ⁺ impurities in the semiconductor layer.

Next, a thin film transistor for selecting a ferroelectric capacitor includes an n-channel (p-doped channel) 300a as a conduction channel on the ferroelectric layer 200, and source and drain electrodes on both sides of the n-channel 300a. The n ⁺ -doped impurity doped layers 300b and 300c are provided, and the gate 500 is formed with an insulating layer having a predetermined thickness interposed on the n-channel 300a.

In such a memory cell structure, one electrode of the ferroelectric capacitor and the source (or drain) of the capacitor selection thin film transistor are integrally formed with an n ⁺ -doped impurity doping layer 300c of the same material. That is, the ferroelectric capacitor and the thin film transistor for capacitor selection have a structure directly connected. The other electrode 300d of the ferroelectric capacitor is connected to the plate pad 100 through a connection hole (or opening) 250 formed in the ferroelectric layer 200. In addition, an insulating layer 400 is formed on the transistor channels 300a and the impurity doped layers 300b, 300c, and 300d. Gate 500 of each cell is connected to the insulating layer to form a gate line. In addition, the bit lines 600 having a stripe shape parallel to the plate pad 100 are formed on the insulating layer 400. The bit lines 600 connect the drains 300b of the cells through holes 450 formed in the insulating layer 400 on the n ⁺ -doped impurity doped layer 300b serving as a drain.

In particular, in the case of forming the memory cells in the form of an array, as shown in FIG. 3, adjacent memory cells are formed to form a symmetrical structure, and a common bit line that can be commonly used for two adjacent cells; A connection hole 450 with the transistor, a capacitor electrode, and a common plate pad connection hole (or opening) 250 are formed.

On the other hand, the manufacturing method of the lateral polarization ferroelectric random access memory of the above structure is as follows.

First, as shown in FIG. 4A, a plate pad 100 on a stripe is formed on a substrate (not shown), and then a ferroelectric material is deposited and selectively etched on the substrate on which the plate pad 100 is formed. A ferroelectric layer 200 having a hole 250 and a ridge 200a structure exposing the plate pad 100 is formed. Here, the capacity of the ferroelectric capacitor related to the amount of polarization is adjusted by controlling the width and height of the ridge 200a of the ferroelectric layer 200 at the time of manufacture.

Next, as shown in FIG. 4B, an impurity doped layer 300 having a p-doped region 300a and n ⁺ -doped regions 300b and 300c is formed on the ferroelectric layer 200. Here, the p-doped region 300a (n-channel) becomes a conduction channel of the capacitor select transistor, and the n ⁺ -doped regions 300b respectively become drains of the capacitor select transistor, and the n ⁺ -doped region 300c Each becomes a source of a capacitor select transistor and an electrode of a lateral ferroelectric capacitor.

Next, as illustrated in FIG. 4C, the impurity doped layer 300 ′ on the ridge 200a of the ferroelectric layer 200 is selectively etched to move the n ⁺ -doped region 300cd to one electrode of the ferroelectric capacitor. At the same time, the lateral ferroelectric capacitor structure is completed by dividing into the region 300c serving as the source of the ferroelectric capacitor selection transistor and the region of the other electrode 300d of the ferroelectric capacitor.

Next, as shown in FIG. 4D, an insulating material is deposited 400 ′ to a predetermined thickness on the divided impurity doped layer 300, and then as shown in FIG. 4E, the p-doped region 300a is shown. gate line 500 is formed at a position corresponding to (n-channel).

Next, as shown in FIG. 4F, an insulating material is deposited on the gate line 500 and the insulating material layer 400 ′ to form the insulating layer 400.

Next, as shown in Figure 4g, n ⁺ corresponding to the drain of the selection transistor to form a hole 450 exposing the doped region (300b) - n ⁺ in the insulation layer 400 on the doped region (300b) Next, a bit line 600 is formed by depositing a conductive material such as metal.

In the above manufacturing method, it is important for the ferroelectric layer 200 to secure the lateral area of the ridge 200a so as to secure the amount of polarization necessary for forming the capacitor. That is, the height and width of the ridge are important control factors that determine the capacity of the ferroelectric capacitor in relation to the amount of polarization. The TFTs formed on the ferroelectric layer 200 are formed of n-channel or p-channel TFTs. In the embodiment, n-channel TFTs were formed. Therefore, each n ⁺ − region serves as an electrode of the ferroelectric capacitor and the ferroelectric capacitor maintains a side-down form.

This lateral polarized ferroelectric random accessor memory operates as follows.

First, in the "write" operation, as shown in FIG. 5A, when the voltage signal V _G is sent to the gate line to form the n-channel 300a of the TFT, the V _DS voltage applied to the bit line is ferroelectric. When the ferroelectric layer of the capacitor is polarized, " 0 " is written, and as shown in FIG. 5B, when the voltage signal (+ V _P ) is sent to the plate pad, the ferroelectric layer is reversely polarized and " 1 " is recorded. . FIG. 6A is an equivalent circuit diagram when recording "0", and FIG. 6B is an equivalent circuit diagram when recording "1". In some cases, specifying " 1 " to polarize with the n-channel TFT results in " 0 " recording with the plate pad. Thus, since the ferroelectric layer is polarized laterally, it is called a lateral polarized ferroelectric random access memory (lateral TFT FRAM).

Next, the " read " operation sends a voltage signal V _G to the gate line to form the n-channel 300a of the TFT and applies a voltage signal + V _P to the plate pad 100 to polarize the ferroelectric capacitor. While the switching current is sensed by the sense amplifier (sese amplifier) (700) and read. For example, as shown in FIG. 5C, when reading (polarized) recorded as “0”, current flows while the polarization state is reversed, and the current is sensed in the sensor amplifier 700, as shown in FIG. 5D. If one reads (polarized) recorded as "1", the polarization is maintained as it is, and a different current flows than the case where "0" is recorded, and the sensor amplifier 700 senses a different current. 6C is an equivalent circuit diagram when reading "0", and FIG. 6D is an equivalent circuit diagram when reading "1".

A lateral polarized ferroelectric random access memory array operating as described above is shown in FIG. 7 as an equivalent circuit. Here, each memory cell is composed of a pair of ferroelectric capacitor 1000 and a thin film transistor 1200 for selecting a ferroelectric capacitor. When writing, a voltage is first applied to the gate W (n) of the selection thin film transistor 1200 to address the voltage, and a corresponding cell is written by applying a voltage to the bit line B (n) or the plate pad P (n). In the case of “reading”, a voltage is applied to the gate (or word line) W (n) first to address and a voltage is applied to the plate pad P (n) to sense the writing state of the corresponding cell in the sense amplifier S / A. Read the information as current.

As described above, the lateral polarization ferroelectric random access memory according to the present invention uses a ferroelectric capacitor, such as bismuthitanate, which has a small amount of polarization up and down but a large amount of polarization to the left and right, depending on the deposition characteristics of the ferroelectric. By forming a capacitor from other ferroelectric materials manufactured to increase side polarization, and using an impurity doped layer thin film of TFT as the electrode of the ferroelectric capacitor, adhesion between the electrode of the ferroelectric capacitor and the TFT is ensured, and the size of the TFT is ferroelectric It is not limited by the size of the capacitor upper electrode, there is an advantage that the manufacturing process is simple because the structure is simple. In addition, in fabricating the memo cell array, adjacent memory cells may be formed to be symmetrical with each other, but a common bit line, a common plate pad contact hole, and a common plate pad may be formed to further increase memory integration.

Claims (16)

A ferroelectric capacitor having a lateral polarization and a selection transistor for selecting the ferroelectric capacitor are formed to be directly connected with the ferroelectric capacitor, but the electrodes of the ferroelectric capacitor and the electrode of the selection transistor connected to each other are formed as an integral semiconductor impurity layer. Lateral polarized ferroelectric random access memory, characterized in that. The method of claim 1, The ferroelectric material of the ferroelectric capacitor is a lateral polarization ferroelectric random access memory, characterized in that the polarization occurs more lateral than the vertical direction, such as bismuthitanate. The method of claim 1, The ferroelectric of the ferroelectric capacitor is a lateral polarization ferroelectric random access memory, characterized in that the lateral polarization is made larger than the vertical polarization. The method according to any one of claims 1 to 3, The ferroelectric capacitor, Board; A plate pad formed on the substrate; The ferroelectric layer formed on the plate pad and the substrate to have a stepped ridge at a position corresponding to the plate pad; And a first conductive semiconductor impurity doping layer for an electrode formed on the ridge side of the ferroelectric layer, The selection transistor, A second conductive impurity doping layer for a conducting channel formed between the first conductive impurity doping layers extending from one side of the ridge; An insulating layer formed on the first conductive impurity doping layer and the second conductive impurity doping layer; A gate formed at a position corresponding to the second conductive impurity doping layer on the insulating layer; Lateral polarized ferroelectric random access memory, characterized in that provided. Board; Plate pads formed on the substrate in a stripe shape; A ferroelectric layer formed on the plate pad and the substrate to have stepped ridges at positions corresponding to the plate pads; The first electrode region connected to one side of the ridge is formed in a stripe shape on the ferroelectric layer except the upper portion of the ridge so as to be connected to both sides of the ridges of the ferroelectric layer. A first conductive impurity doping layer for an electrode formed to be connected to the plate pads through holes; Second conductive impurity doping layers for conduction channels formed between the first conductive impurity doping layers connected to the other sides of the ridges; An insulating layer formed on the ferroelectric layer, the first conductive impurity doped layers and the second conductive impurity doped layers; Gate lines in the insulating layer formed on a stripe in a direction crossing the plate pads to be spaced apart from the second conductive impurity doped layer so as to correspond to the second conductive impurity doped layers; And The second electrode region and the third electrode region of the first conductive impurity doped layer are formed on the insulating layer in a stripe shape in a direction parallel to the plate pads, and are connected to the second conductive impurity doped layer, respectively. Bit lines formed to be connected through the holes formed in the third electrode region and the insulating layer instead of the second electrode region connected to the other side of the ridge; Lateral polarized ferroelectric random access memory, characterized in that provided. The method of claim 5, And the ferroelectric layer is formed of bismuthitanate. Lateral polarized ferroelectric random access memory, characterized in that provided. The method of claim 5, And the ridge of the ferroelectric layer is manufactured such that the lateral polarization is larger than the vertical polarization. The method according to any one of claims 5 to 7, Two adjacent memory cells are formed in a symmetrical structure with each other so that one connection hole between the first conductive impurity doping layer and the plate pad, the plate pad, and the bit line are commonly used in the two memory cells, respectively. Lateral polarized ferroelectric random access memory, characterized in that it is formed of a common plate pad and a common bit line. (A) depositing a ferroelectric material on the substrate on which the plate pads are formed to form a ferroelectric layer; (B) selectively etching the ferroelectric layer to form holes for exposing the plate pads and a ridge having a predetermined width on the ferroelectric layer; (C) forming an impurity doping layer doped with a first conductive impurity and a second conductive impurity on the ferroelectric layer, respectively; (D) selectively etching the first conductive impurity doping layer deposited on the ferroelectric layer ridge to form electrodes on both sides of the ferroelectric capacitor; (E) depositing an insulating material to a predetermined thickness on the exposed ridge and the impurity doped layer, and then forming a gate line on a corresponding position on the second conductive impurity doped layer; (F) depositing an insulating material on the gate line and the insulating material layer to form an insulating layer; And (G) forming holes for exposing the one electrode region in an insulating layer on one electrode region of the selection transistor that is not connected to the ridge side of the electrode region of the first conductive impurity doping layer, and then depositing a conductive material Forming a bit line on the stripe in a direction parallel to the plate pads; And a lateral polarized ferroelectric random access memory. The method of claim 9, Wherein the first conductive impurity doping layer and the second conductive impurity doping layer are n ⁺ -doped layers and p-doped layers, respectively, or p ⁺ -doped layers and n-doped layers, respectively. Method of manufacturing access memory. The method of claim 9 or 10, And controlling the capacitance of the ferroelectric capacitor by adjusting the width and height of the ferroelectric layer ridge. Board; Plate pads formed on the substrate in a stripe shape; A ferroelectric layer formed on the plate pad and the substrate to have stepped ridges at positions corresponding to the plate pads; The first electrode region connected to one side of the ridge is formed in a stripe shape on the ferroelectric layer except the upper portion of the ridge so as to be connected to both sides of the ridges of the ferroelectric layer. A first conductive impurity doping layer for an electrode formed to be connected to the plate pads through holes; Second conductive impurity doping layers for conduction channels formed between the first conductive impurity doping layers connected to the other sides of the ridges; An insulating layer formed on the ferroelectric layer, the first conductive impurity doped layers and the second conductive impurity doped layers; Gate lines in the insulating layer formed on a stripe in a direction crossing the plate pads to be spaced apart from the second conductive impurity doped layer so as to correspond to the second conductive impurity doped layers; And a stripe shape in a direction parallel to the plate pads on the insulating layer, wherein the second electrode region and the third electrode region of the first conductive impurity doped layer are respectively connected to the second conductive impurity doped layer. And bit lines formed to be connected through the holes formed in the third electrode region and the insulating layer instead of the second electrode region connected to the other side of the ridge. To A voltage signal is sent to the gate line to address a ferroelectric capacitor comprising a ridge of the ferroelectric layer and a first electrode region and a second electrode region of the first conductive impurity doped layer, and then applied between the bit line and the plate pad. Selectively polarizing and recording the ferroelectric capacitor with a voltage; And Sending a voltage signal to the gate line to address the ferroelectric capacitor and then applying a voltage signal to the plate pad to sense and read a current flowing through the ferroelectric capacitor with a sense amplifier; And a method of driving a lateral polarized ferroelectric random access memory. The method of claim 12, The writing step, for an n-channel transistor, Polarizing the ferroelectric capacitor with a constant voltage applied to the bit line, and writing "0"; And Polarizing the ferroelectric capacitor at a constant voltage on the plate pad and recording a “1”; And a method of driving a lateral polarized ferroelectric random access memory. The method of claim 13, The reading step, When reading "0", the polarization state of the ferroelectric capacitor is reversed while the current flows while the sensor amplifier senses the current, and when reading "1", the polarization state of the ferroelectric capacitor Is maintained as it is, and a different current flows than the case where it is written as " 0 ", so that a different current is sensed by the sensor amplifier. The method of claim 12, The writing step, in the case of a p-channel transistor, Polarizing the ferroelectric capacitor with a negative voltage applied to the bit line, and writing "1"; And Polarizing the ferroelectric capacitor with a negative voltage on the plate pad and recording a "0"; And a method of driving a lateral polarized ferroelectric random access memory. The method of claim 15, The reading step, When reading what is written as "1", the polarization state of the ferroelectric capacitor is reversed while current flows to sense the current in the sensor amplifier, and when reading what is written as "0", the polarization state of the ferroelectric capacitor Is maintained as it is, and a different current flows from the case where it is written as "1", so that a different current is sensed by the sensor amplifier.